[MIPS] TXx9: Fix txx9_pcode initialization
[linux-2.6] / arch / mips / sibyte / Kconfig
CommitLineData
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1config SIBYTE_SB1250
2 bool
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3 select CEVT_SB1250
4 select CSRC_SB1250
38b18f72 5 select HW_HAS_PCI
7bcf7717 6 select IRQ_CPU
ca6f5494 7 select SIBYTE_ENABLE_LDT_IF_PCI
d619f38f 8 select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 9 select SIBYTE_SB1xxx_SOC
e73ea273 10 select SYS_SUPPORTS_SMP
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11
12config SIBYTE_BCM1120
13 bool
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14 select CEVT_SB1250
15 select CSRC_SB1250
7bcf7717 16 select IRQ_CPU
38b18f72 17 select SIBYTE_BCM112X
bb9b813b 18 select SIBYTE_HAS_ZBUS_PROFILING
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19 select SIBYTE_SB1xxx_SOC
20
21config SIBYTE_BCM1125
22 bool
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23 select CEVT_SB1250
24 select CSRC_SB1250
38b18f72 25 select HW_HAS_PCI
7bcf7717 26 select IRQ_CPU
38b18f72 27 select SIBYTE_BCM112X
bb9b813b 28 select SIBYTE_HAS_ZBUS_PROFILING
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29 select SIBYTE_SB1xxx_SOC
30
31config SIBYTE_BCM1125H
32 bool
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33 select CEVT_SB1250
34 select CSRC_SB1250
38b18f72 35 select HW_HAS_PCI
7bcf7717 36 select IRQ_CPU
38b18f72 37 select SIBYTE_BCM112X
ca6f5494 38 select SIBYTE_ENABLE_LDT_IF_PCI
bb9b813b 39 select SIBYTE_HAS_ZBUS_PROFILING
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40 select SIBYTE_SB1xxx_SOC
41
42config SIBYTE_BCM112X
43 bool
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44 select CEVT_SB1250
45 select CSRC_SB1250
7bcf7717 46 select IRQ_CPU
38b18f72 47 select SIBYTE_SB1xxx_SOC
bb9b813b 48 select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 49
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50config SIBYTE_BCM1x80
51 bool
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52 select CEVT_BCM1480
53 select CSRC_BCM1480
f137e463 54 select HW_HAS_PCI
7bcf7717 55 select IRQ_CPU
d619f38f 56 select SIBYTE_HAS_ZBUS_PROFILING
f137e463 57 select SIBYTE_SB1xxx_SOC
e73ea273 58 select SYS_SUPPORTS_SMP
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59
60config SIBYTE_BCM1x55
61 bool
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62 select CEVT_BCM1480
63 select CSRC_BCM1480
f137e463 64 select HW_HAS_PCI
7bcf7717 65 select IRQ_CPU
f137e463 66 select SIBYTE_SB1xxx_SOC
bb9b813b 67 select SIBYTE_HAS_ZBUS_PROFILING
e73ea273 68 select SYS_SUPPORTS_SMP
f137e463 69
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70config SIBYTE_SB1xxx_SOC
71 bool
38b18f72 72 select DMA_COHERENT
7bcf7717 73 select IRQ_CPU
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74 select SIBYTE_CFE
75 select SWAP_IO_SPACE
76 select SYS_SUPPORTS_32BIT_KERNEL
77 select SYS_SUPPORTS_64BIT_KERNEL
78
79choice
80 prompt "SiByte SOC Stepping"
81 depends on SIBYTE_SB1xxx_SOC
82
83config CPU_SB1_PASS_1
84 bool "1250 Pass1"
85 depends on SIBYTE_SB1250
86 select CPU_HAS_PREFETCH
87
88config CPU_SB1_PASS_2_1250
89 bool "1250 An"
90 depends on SIBYTE_SB1250
91 select CPU_SB1_PASS_2
92 help
93 Also called BCM1250 Pass 2
94
95config CPU_SB1_PASS_2_2
96 bool "1250 Bn"
97 depends on SIBYTE_SB1250
98 select CPU_HAS_PREFETCH
99 help
100 Also called BCM1250 Pass 2.2
101
102config CPU_SB1_PASS_4
103 bool "1250 Cn"
104 depends on SIBYTE_SB1250
105 select CPU_HAS_PREFETCH
106 help
107 Also called BCM1250 Pass 3
108
109config CPU_SB1_PASS_2_112x
110 bool "112x Hybrid"
111 depends on SIBYTE_BCM112X
112 select CPU_SB1_PASS_2
113
114config CPU_SB1_PASS_3
115 bool "112x An"
116 depends on SIBYTE_BCM112X
117 select CPU_HAS_PREFETCH
118
119endchoice
120
121config CPU_SB1_PASS_2
122 bool
123
124config SIBYTE_HAS_LDT
125 bool
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126
127config SIBYTE_ENABLE_LDT_IF_PCI
128 bool
129 select SIBYTE_HAS_LDT if PCI
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130
131config SIMULATION
132 bool "Running under simulation"
133 depends on SIBYTE_SB1xxx_SOC
134 help
135 Build a kernel suitable for running under the GDB simulator.
136 Primarily adjusts the kernel's notion of time.
137
77607635 138config SB1_CEX_ALWAYS_FATAL
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139 bool "All cache exceptions considered fatal (no recovery attempted)"
140 depends on SIBYTE_SB1xxx_SOC
141
77607635 142config SB1_CERR_STALL
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143 bool "Stall (rather than panic) on fatal cache error"
144 depends on SIBYTE_SB1xxx_SOC
145
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146config SIBYTE_CFE
147 bool "Booting from CFE"
148 depends on SIBYTE_SB1xxx_SOC
df78b5c8 149 select CFE
36a88530 150 select SYS_HAS_EARLY_PRINTK
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151 help
152 Make use of the CFE API for enumerating available memory,
153 controlling secondary CPUs, and possibly console output.
154
155config SIBYTE_CFE_CONSOLE
156 bool "Use firmware console"
157 depends on SIBYTE_CFE
158 help
159 Use the CFE API's console write routines during boot. Other console
160 options (VT console, sb1250 duart console, etc.) should not be
161 configured.
162
163config SIBYTE_STANDALONE
164 bool
165 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
36a88530 166 select SYS_HAS_EARLY_PRINTK
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167 default y
168
169config SIBYTE_STANDALONE_RAM_SIZE
170 int "Memory size (in megabytes)"
171 depends on SIBYTE_STANDALONE
172 default "32"
173
174config SIBYTE_BUS_WATCHER
175 bool "Support for Bus Watcher statistics"
176 depends on SIBYTE_SB1xxx_SOC
177 help
178 Handle and keep statistics on the bus error interrupts (COR_ECC,
179 BAD_ECC, IO_BUS).
180
181config SIBYTE_BW_TRACE
182 bool "Capture bus trace before bus error"
183 depends on SIBYTE_BUS_WATCHER
184 help
185 Run a continuous bus trace, dumping the raw data as soon as
186 a ZBbus error is detected. Cannot work if ZBbus profiling
187 is turned on, and also will interfere with JTAG-based trace
188 buffer activity. Raw buffer data is dumped to console, and
189 must be processed off-line.
190
38b18f72 191config SIBYTE_TBPROF
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192 tristate "Support for ZBbus profiling"
193 depends on SIBYTE_HAS_ZBUS_PROFILING
194
195config SIBYTE_HAS_ZBUS_PROFILING
196 bool