Commit | Line | Data |
---|---|---|
1a348ccc AG |
1 | /* |
2 | * Tehuti Networks(R) Network Driver | |
3 | * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #ifndef _TEHUTI_H | |
12 | #define _TEHUTI_H | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/ethtool.h> | |
21 | #include <linux/mii.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/uaccess.h> | |
24 | #include <linux/in.h> | |
25 | #include <linux/ip.h> | |
26 | #include <linux/tcp.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/tty.h> | |
29 | #include <linux/if_vlan.h> | |
30 | #include <linux/version.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <asm/byteorder.h> | |
34 | ||
35 | /* Compile Time Switches */ | |
36 | /* start */ | |
37 | #define BDX_TSO | |
38 | #define BDX_LLTX | |
39 | #define BDX_DELAY_WPTR | |
40 | /* #define BDX_MSI */ | |
41 | /* end */ | |
42 | ||
43 | #if !defined CONFIG_PCI_MSI | |
44 | # undef BDX_MSI | |
45 | #endif | |
46 | ||
47 | #define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ | |
48 | NETIF_MSG_PROBE | \ | |
49 | NETIF_MSG_LINK) | |
50 | ||
51 | /* ioctl ops */ | |
52 | #define BDX_OP_READ 1 | |
53 | #define BDX_OP_WRITE 2 | |
54 | ||
55 | /* RX copy break size */ | |
56 | #define BDX_COPYBREAK 257 | |
57 | ||
58 | #define DRIVER_AUTHOR "Tehuti Networks(R)" | |
59 | #define BDX_DRV_DESC "Tehuti Networks(R) Network Driver" | |
60 | #define BDX_DRV_NAME "tehuti" | |
61 | #define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC" | |
62 | #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC" | |
63 | #define BDX_DRV_VERSION "7.29.3" | |
64 | ||
65 | #ifdef BDX_MSI | |
66 | # define BDX_MSI_STRING "msi " | |
67 | #else | |
68 | # define BDX_MSI_STRING "" | |
69 | #endif | |
70 | ||
71 | /* netdev tx queue len for Luxor. default value is, btw, 1000 | |
72 | * ifcontig eth1 txqueuelen 3000 - to change it at runtime */ | |
73 | #define BDX_NDEV_TXQ_LEN 3000 | |
74 | ||
75 | #define FIFO_SIZE 4096 | |
76 | #define FIFO_EXTRA_SPACE 1024 | |
77 | ||
78 | #define MIN(x, y) ((x) < (y) ? (x) : (y)) | |
79 | ||
80 | #if BITS_PER_LONG == 64 | |
81 | # define H32_64(x) (u32) ((u64)(x) >> 32) | |
82 | # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) | |
83 | #elif BITS_PER_LONG == 32 | |
84 | # define H32_64(x) 0 | |
85 | # define L32_64(x) ((u32) (x)) | |
86 | #else /* BITS_PER_LONG == ?? */ | |
87 | # error BITS_PER_LONG is undefined. Must be 64 or 32 | |
88 | #endif /* BITS_PER_LONG */ | |
89 | ||
90 | #ifdef __BIG_ENDIAN | |
91 | # define CPU_CHIP_SWAP32(x) swab32(x) | |
92 | # define CPU_CHIP_SWAP16(x) swab16(x) | |
93 | #else | |
94 | # define CPU_CHIP_SWAP32(x) (x) | |
95 | # define CPU_CHIP_SWAP16(x) (x) | |
96 | #endif | |
97 | ||
98 | #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) | |
99 | #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) | |
100 | ||
101 | #ifndef DMA_64BIT_MASK | |
102 | # define DMA_64BIT_MASK 0xffffffffffffffffULL | |
103 | #endif | |
104 | ||
105 | #ifndef DMA_32BIT_MASK | |
106 | # define DMA_32BIT_MASK 0x00000000ffffffffULL | |
107 | #endif | |
108 | ||
109 | #ifndef NET_IP_ALIGN | |
110 | # define NET_IP_ALIGN 2 | |
111 | #endif | |
112 | ||
113 | #ifndef NETDEV_TX_OK | |
114 | # define NETDEV_TX_OK 0 | |
115 | #endif | |
116 | ||
117 | #define LUXOR_MAX_PORT 2 | |
118 | #define BDX_MAX_RX_DONE 150 | |
119 | #define BDX_TXF_DESC_SZ 16 | |
120 | #define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) | |
121 | #define BDX_MIN_TX_LEVEL 256 | |
122 | #define BDX_NO_UPD_PACKETS 40 | |
123 | ||
124 | struct pci_nic { | |
125 | int port_num; | |
126 | void __iomem *regs; | |
127 | int irq_type; | |
128 | struct bdx_priv *priv[LUXOR_MAX_PORT]; | |
129 | }; | |
130 | ||
131 | enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX }; | |
132 | ||
133 | #define PCK_TH_MULT 128 | |
134 | #define INT_COAL_MULT 2 | |
135 | ||
136 | #define BITS_MASK(nbits) ((1<<nbits)-1) | |
137 | #define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits)) | |
138 | #define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift) | |
139 | #define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift) | |
140 | #define BITS_SHIFT_CLEAR(x, nbits, nshift) \ | |
141 | ((x)&(~BITS_SHIFT_MASK(nbits, nshift))) | |
142 | ||
143 | #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) | |
144 | #define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15) | |
145 | #define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16) | |
146 | #define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20) | |
147 | ||
148 | #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \ | |
149 | ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20)) | |
150 | ||
151 | struct fifo { | |
152 | dma_addr_t da; /* physical address of fifo (used by HW) */ | |
153 | char *va; /* virtual address of fifo (used by SW) */ | |
154 | u32 rptr, wptr; /* cached values of RPTR and WPTR registers, | |
155 | they're 32 bits on both 32 and 64 archs */ | |
156 | u16 reg_CFG0, reg_CFG1; | |
157 | u16 reg_RPTR, reg_WPTR; | |
158 | u16 memsz; /* memory size allocated for fifo */ | |
159 | u16 size_mask; | |
160 | u16 pktsz; /* skb packet size to allocate */ | |
161 | u16 rcvno; /* number of buffers that come from this RXF */ | |
162 | }; | |
163 | ||
164 | struct txf_fifo { | |
165 | struct fifo m; /* minimal set of variables used by all fifos */ | |
166 | }; | |
167 | ||
168 | struct txd_fifo { | |
169 | struct fifo m; /* minimal set of variables used by all fifos */ | |
170 | }; | |
171 | ||
172 | struct rxf_fifo { | |
173 | struct fifo m; /* minimal set of variables used by all fifos */ | |
174 | }; | |
175 | ||
176 | struct rxd_fifo { | |
177 | struct fifo m; /* minimal set of variables used by all fifos */ | |
178 | }; | |
179 | ||
180 | struct rx_map { | |
181 | u64 dma; | |
182 | struct sk_buff *skb; | |
183 | }; | |
184 | ||
185 | struct rxdb { | |
186 | int *stack; | |
187 | struct rx_map *elems; | |
188 | int nelem; | |
189 | int top; | |
190 | }; | |
191 | ||
192 | union bdx_dma_addr { | |
193 | dma_addr_t dma; | |
194 | struct sk_buff *skb; | |
195 | }; | |
196 | ||
197 | /* Entry in the db. | |
198 | * if len == 0 addr is dma | |
199 | * if len != 0 addr is skb */ | |
200 | struct tx_map { | |
201 | union bdx_dma_addr addr; | |
202 | int len; | |
203 | }; | |
204 | ||
205 | /* tx database - implemented as circular fifo buffer*/ | |
206 | struct txdb { | |
207 | struct tx_map *start; /* points to the first element */ | |
208 | struct tx_map *end; /* points just AFTER the last element */ | |
209 | struct tx_map *rptr; /* points to the next element to read */ | |
210 | struct tx_map *wptr; /* points to the next element to write */ | |
211 | int size; /* number of elements in the db */ | |
212 | }; | |
213 | ||
214 | /*Internal stats structure*/ | |
215 | struct bdx_stats { | |
216 | u64 InUCast; /* 0x7200 */ | |
217 | u64 InMCast; /* 0x7210 */ | |
218 | u64 InBCast; /* 0x7220 */ | |
219 | u64 InPkts; /* 0x7230 */ | |
220 | u64 InErrors; /* 0x7240 */ | |
221 | u64 InDropped; /* 0x7250 */ | |
222 | u64 FrameTooLong; /* 0x7260 */ | |
223 | u64 FrameSequenceErrors; /* 0x7270 */ | |
224 | u64 InVLAN; /* 0x7280 */ | |
225 | u64 InDroppedDFE; /* 0x7290 */ | |
226 | u64 InDroppedIntFull; /* 0x72A0 */ | |
227 | u64 InFrameAlignErrors; /* 0x72B0 */ | |
228 | ||
229 | /* 0x72C0-0x72E0 RSRV */ | |
230 | ||
231 | u64 OutUCast; /* 0x72F0 */ | |
232 | u64 OutMCast; /* 0x7300 */ | |
233 | u64 OutBCast; /* 0x7310 */ | |
234 | u64 OutPkts; /* 0x7320 */ | |
235 | ||
236 | /* 0x7330-0x7360 RSRV */ | |
237 | ||
238 | u64 OutVLAN; /* 0x7370 */ | |
239 | u64 InUCastOctects; /* 0x7380 */ | |
240 | u64 OutUCastOctects; /* 0x7390 */ | |
241 | ||
242 | /* 0x73A0-0x73B0 RSRV */ | |
243 | ||
244 | u64 InBCastOctects; /* 0x73C0 */ | |
245 | u64 OutBCastOctects; /* 0x73D0 */ | |
246 | u64 InOctects; /* 0x73E0 */ | |
247 | u64 OutOctects; /* 0x73F0 */ | |
248 | }; | |
249 | ||
250 | struct bdx_priv { | |
251 | void __iomem *pBdxRegs; | |
252 | struct net_device *ndev; | |
253 | ||
254 | struct napi_struct napi; | |
255 | ||
256 | /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ | |
257 | struct rxd_fifo rxd_fifo0; | |
258 | struct rxf_fifo rxf_fifo0; | |
259 | struct rxdb *rxdb; /* rx dbs to store skb pointers */ | |
260 | int napi_stop; | |
261 | struct vlan_group *vlgrp; | |
262 | ||
263 | /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ | |
264 | struct txd_fifo txd_fifo0; | |
265 | struct txf_fifo txf_fifo0; | |
266 | ||
267 | struct txdb txdb; | |
268 | int tx_level; | |
269 | #ifdef BDX_DELAY_WPTR | |
270 | int tx_update_mark; | |
271 | int tx_noupd; | |
272 | #endif | |
273 | spinlock_t tx_lock; /* NETIF_F_LLTX mode */ | |
274 | ||
275 | /* rarely used */ | |
276 | u8 port; | |
277 | u32 msg_enable; | |
278 | int stats_flag; | |
279 | struct bdx_stats hw_stats; | |
280 | struct net_device_stats net_stats; | |
281 | struct pci_dev *pdev; | |
282 | ||
283 | struct pci_nic *nic; | |
284 | ||
285 | u8 txd_size; | |
286 | u8 txf_size; | |
287 | u8 rxd_size; | |
288 | u8 rxf_size; | |
289 | u32 rdintcm; | |
290 | u32 tdintcm; | |
291 | }; | |
292 | ||
293 | /* RX FREE descriptor - 64bit*/ | |
294 | struct rxf_desc { | |
295 | u32 info; /* Buffer Count + Info - described below */ | |
296 | u32 va_lo; /* VAdr[31:0] */ | |
297 | u32 va_hi; /* VAdr[63:32] */ | |
298 | u32 pa_lo; /* PAdr[31:0] */ | |
299 | u32 pa_hi; /* PAdr[63:32] */ | |
300 | u32 len; /* Buffer Length */ | |
301 | }; | |
302 | ||
303 | #define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0) | |
304 | #define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8) | |
305 | #define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15) | |
306 | #define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16) | |
307 | #define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21) | |
308 | #define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27) | |
309 | #define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) | |
310 | #define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) | |
311 | #define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) | |
38b22195 | 312 | #define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0) |
1a348ccc AG |
313 | #define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) |
314 | #define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) | |
315 | ||
316 | struct rxd_desc { | |
317 | u32 rxd_val1; | |
318 | u16 len; | |
319 | u16 rxd_vlan; | |
320 | u32 va_lo; | |
321 | u32 va_hi; | |
322 | }; | |
323 | ||
324 | /* PBL describes each virtual buffer to be */ | |
325 | /* transmitted from the host.*/ | |
326 | struct pbl { | |
327 | u32 pa_lo; | |
328 | u32 pa_hi; | |
329 | u32 len; | |
330 | }; | |
331 | ||
332 | /* First word for TXD descriptor. It means: type = 3 for regular Tx packet, | |
333 | * hw_csum = 7 for ip+udp+tcp hw checksums */ | |
334 | #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \ | |
335 | ((bc) | ((checksum)<<5) | ((vtag)<<8) | \ | |
336 | ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20)) | |
337 | ||
338 | struct txd_desc { | |
339 | u32 txd_val1; | |
340 | u16 mss; | |
341 | u16 length; | |
342 | u32 va_lo; | |
343 | u32 va_hi; | |
344 | struct pbl pbl[0]; /* Fragments */ | |
345 | } __attribute__ ((packed)); | |
346 | ||
347 | /* Register region size */ | |
348 | #define BDX_REGS_SIZE 0x1000 | |
349 | ||
350 | /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ | |
351 | #define regTXD_CFG1_0 0x4000 | |
352 | #define regRXF_CFG1_0 0x4010 | |
353 | #define regRXD_CFG1_0 0x4020 | |
354 | #define regTXF_CFG1_0 0x4030 | |
355 | #define regTXD_CFG0_0 0x4040 | |
356 | #define regRXF_CFG0_0 0x4050 | |
357 | #define regRXD_CFG0_0 0x4060 | |
358 | #define regTXF_CFG0_0 0x4070 | |
359 | #define regTXD_WPTR_0 0x4080 | |
360 | #define regRXF_WPTR_0 0x4090 | |
361 | #define regRXD_WPTR_0 0x40A0 | |
362 | #define regTXF_WPTR_0 0x40B0 | |
363 | #define regTXD_RPTR_0 0x40C0 | |
364 | #define regRXF_RPTR_0 0x40D0 | |
365 | #define regRXD_RPTR_0 0x40E0 | |
366 | #define regTXF_RPTR_0 0x40F0 | |
367 | #define regTXF_RPTR_3 0x40FC | |
368 | ||
369 | /* hardware versioning */ | |
370 | #define FW_VER 0x5010 | |
371 | #define SROM_VER 0x5020 | |
372 | #define FPGA_VER 0x5030 | |
373 | #define FPGA_SEED 0x5040 | |
374 | ||
375 | /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ | |
376 | #define regISR regISR0 | |
377 | #define regISR0 0x5100 | |
378 | ||
379 | #define regIMR regIMR0 | |
380 | #define regIMR0 0x5110 | |
381 | ||
382 | #define regRDINTCM0 0x5120 | |
383 | #define regRDINTCM2 0x5128 | |
384 | ||
385 | #define regTDINTCM0 0x5130 | |
386 | ||
387 | #define regISR_MSK0 0x5140 | |
388 | ||
389 | #define regINIT_SEMAPHORE 0x5170 | |
390 | #define regINIT_STATUS 0x5180 | |
391 | ||
392 | #define regMAC_LNK_STAT 0x0200 | |
393 | #define MAC_LINK_STAT 0x4 /* Link state */ | |
394 | ||
395 | #define regGMAC_RXF_A 0x1240 | |
396 | ||
397 | #define regUNC_MAC0_A 0x1250 | |
398 | #define regUNC_MAC1_A 0x1260 | |
399 | #define regUNC_MAC2_A 0x1270 | |
400 | ||
401 | #define regVLAN_0 0x1800 | |
402 | ||
403 | #define regMAX_FRAME_A 0x12C0 | |
404 | ||
405 | #define regRX_MAC_MCST0 0x1A80 | |
406 | #define regRX_MAC_MCST1 0x1A84 | |
407 | #define MAC_MCST_NUM 15 | |
408 | #define regRX_MCST_HASH0 0x1A00 | |
409 | #define MAC_MCST_HASH_NUM 8 | |
410 | ||
411 | #define regVPC 0x2300 | |
412 | #define regVIC 0x2320 | |
413 | #define regVGLB 0x2340 | |
414 | ||
415 | #define regCLKPLL 0x5000 | |
416 | ||
417 | /*for 10G only*/ | |
418 | #define regREVISION 0x6000 | |
419 | #define regSCRATCH 0x6004 | |
420 | #define regCTRLST 0x6008 | |
421 | #define regMAC_ADDR_0 0x600C | |
422 | #define regMAC_ADDR_1 0x6010 | |
423 | #define regFRM_LENGTH 0x6014 | |
424 | #define regPAUSE_QUANT 0x6018 | |
425 | #define regRX_FIFO_SECTION 0x601C | |
426 | #define regTX_FIFO_SECTION 0x6020 | |
427 | #define regRX_FULLNESS 0x6024 | |
428 | #define regTX_FULLNESS 0x6028 | |
429 | #define regHASHTABLE 0x602C | |
430 | #define regMDIO_ST 0x6030 | |
431 | #define regMDIO_CTL 0x6034 | |
432 | #define regMDIO_DATA 0x6038 | |
433 | #define regMDIO_ADDR 0x603C | |
434 | ||
435 | #define regRST_PORT 0x7000 | |
436 | #define regDIS_PORT 0x7010 | |
437 | #define regRST_QU 0x7020 | |
438 | #define regDIS_QU 0x7030 | |
439 | ||
440 | #define regCTRLST_TX_ENA 0x0001 | |
441 | #define regCTRLST_RX_ENA 0x0002 | |
442 | #define regCTRLST_PRM_ENA 0x0010 | |
443 | #define regCTRLST_PAD_ENA 0x0020 | |
444 | ||
445 | #define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA) | |
446 | ||
447 | #define regRX_FLT 0x1400 | |
448 | ||
449 | /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/ | |
450 | #define TX_RX_CFG1_BASE 0xffffffff /*0-31 */ | |
451 | #define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ | |
452 | #define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */ | |
453 | #define TX_RX_CFG0_SIZE 0x0003 /*1:0 */ | |
454 | ||
455 | /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ | |
456 | #define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */ | |
457 | ||
458 | /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ | |
459 | #define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */ | |
460 | ||
461 | #define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped | |
462 | * size is rounded to 16 */ | |
463 | ||
464 | /* regISR 0x0100 */ | |
465 | /* regIMR 0x0110 */ | |
466 | #define IMR_INPROG 0x80000000 /*31 */ | |
467 | #define IR_LNKCHG1 0x10000000 /*28 */ | |
468 | #define IR_LNKCHG0 0x08000000 /*27 */ | |
469 | #define IR_GPIO 0x04000000 /*26 */ | |
470 | #define IR_RFRSH 0x02000000 /*25 */ | |
471 | #define IR_RSVD 0x01000000 /*24 */ | |
472 | #define IR_SWI 0x00800000 /*23 */ | |
473 | #define IR_RX_FREE_3 0x00400000 /*22 */ | |
474 | #define IR_RX_FREE_2 0x00200000 /*21 */ | |
475 | #define IR_RX_FREE_1 0x00100000 /*20 */ | |
476 | #define IR_RX_FREE_0 0x00080000 /*19 */ | |
477 | #define IR_TX_FREE_3 0x00040000 /*18 */ | |
478 | #define IR_TX_FREE_2 0x00020000 /*17 */ | |
479 | #define IR_TX_FREE_1 0x00010000 /*16 */ | |
480 | #define IR_TX_FREE_0 0x00008000 /*15 */ | |
481 | #define IR_RX_DESC_3 0x00004000 /*14 */ | |
482 | #define IR_RX_DESC_2 0x00002000 /*13 */ | |
483 | #define IR_RX_DESC_1 0x00001000 /*12 */ | |
484 | #define IR_RX_DESC_0 0x00000800 /*11 */ | |
485 | #define IR_PSE 0x00000400 /*10 */ | |
486 | #define IR_TMR3 0x00000200 /*9 */ | |
487 | #define IR_TMR2 0x00000100 /*8 */ | |
488 | #define IR_TMR1 0x00000080 /*7 */ | |
489 | #define IR_TMR0 0x00000040 /*6 */ | |
490 | #define IR_VNT 0x00000020 /*5 */ | |
491 | #define IR_RxFL 0x00000010 /*4 */ | |
492 | #define IR_SDPERR 0x00000008 /*3 */ | |
493 | #define IR_TR 0x00000004 /*2 */ | |
494 | #define IR_PCIE_LINK 0x00000002 /*1 */ | |
495 | #define IR_PCIE_TOUT 0x00000001 /*0 */ | |
496 | ||
497 | #define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \ | |
498 | IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT) | |
499 | #define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0) | |
500 | #define IR_ALL 0xfdfffff7 | |
501 | ||
502 | #define IR_LNKCHG0_ofst 27 | |
503 | ||
504 | #define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ | |
505 | #define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ | |
506 | #define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ | |
507 | #define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ | |
508 | #define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ | |
509 | #define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ | |
510 | #define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ | |
511 | #define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ | |
512 | #define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ | |
513 | #define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ | |
514 | #define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscous mode */ | |
515 | ||
516 | #define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ | |
517 | ||
518 | #define CLKPLL_PLLLKD 0x0200 /*9 */ | |
519 | #define CLKPLL_RSTEND 0x0100 /*8 */ | |
520 | #define CLKPLL_SFTRST 0x0001 /*0 */ | |
521 | ||
522 | #define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND) | |
523 | ||
524 | /* | |
525 | * PCI-E Device Control Register (Offset 0x88) | |
526 | * Source: Luxor Data Sheet, 7.1.3.3.3 | |
527 | */ | |
528 | #define PCI_DEV_CTRL_REG 0x88 | |
529 | #define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5) | |
530 | #define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12) | |
531 | ||
532 | /* | |
533 | * PCI-E Link Status Register (Offset 0x92) | |
534 | * Source: Luxor Data Sheet, 7.1.3.3.7 | |
535 | */ | |
536 | #define PCI_LINK_STATUS_REG 0x92 | |
537 | #define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4) | |
538 | ||
539 | /* Debugging Macros */ | |
540 | ||
541 | #define ERR(fmt, args...) printk(KERN_ERR fmt, ## args) | |
542 | #define DBG2(fmt, args...) \ | |
543 | printk(KERN_ERR "%s:%-5d: " fmt, __FUNCTION__, __LINE__, ## args) | |
544 | ||
545 | #define BDX_ASSERT(x) BUG_ON(x) | |
546 | ||
547 | #ifdef DEBUG | |
548 | ||
549 | #define ENTER do { \ | |
550 | printk(KERN_ERR "%s:%-5d: ENTER\n", __FUNCTION__, __LINE__); \ | |
551 | } while (0) | |
552 | ||
553 | #define RET(args...) do { \ | |
554 | printk(KERN_ERR "%s:%-5d: RETURN\n", __FUNCTION__, __LINE__); \ | |
555 | return args; } while (0) | |
556 | ||
557 | #define DBG(fmt, args...) \ | |
558 | printk(KERN_ERR "%s:%-5d: " fmt, __FUNCTION__, __LINE__, ## args) | |
559 | #else | |
560 | #define ENTER do { } while (0) | |
561 | #define RET(args...) return args | |
562 | #define DBG(fmt, args...) do { } while (0) | |
563 | #endif | |
564 | ||
565 | #endif /* _BDX__H */ |