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1da177e4 LT |
1 | #ifndef __ASM_SH_SYSTEM_H |
2 | #define __ASM_SH_SYSTEM_H | |
3 | ||
4 | /* | |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
6 | * Copyright (C) 2002 Paul Mundt | |
7 | */ | |
8 | ||
afbfb52e | 9 | #include <linux/irqflags.h> |
310f7963 | 10 | #include <linux/compiler.h> |
e08f457c | 11 | #include <linux/linkage.h> |
e4e3b5cc | 12 | #include <asm/types.h> |
3a2e117e | 13 | #include <asm/ptrace.h> |
1da177e4 | 14 | |
98c4ecde | 15 | #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ |
1da177e4 | 16 | |
a62a3861 | 17 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) |
29847622 PM |
18 | #define __icbi() \ |
19 | { \ | |
20 | unsigned long __addr; \ | |
21 | __addr = 0xa8000000; \ | |
22 | __asm__ __volatile__( \ | |
23 | "icbi %0\n\t" \ | |
24 | : /* no output */ \ | |
25 | : "m" (__m(__addr))); \ | |
26 | } | |
27 | #endif | |
1da177e4 | 28 | |
29847622 PM |
29 | /* |
30 | * A brief note on ctrl_barrier(), the control register write barrier. | |
31 | * | |
32 | * Legacy SH cores typically require a sequence of 8 nops after | |
33 | * modification of a control register in order for the changes to take | |
34 | * effect. On newer cores (like the sh4a and sh5) this is accomplished | |
35 | * with icbi. | |
36 | * | |
37 | * Also note that on sh4a in the icbi case we can forego a synco for the | |
38 | * write barrier, as it's not necessary for control registers. | |
39 | * | |
40 | * Historically we have only done this type of barrier for the MMUCR, but | |
41 | * it's also necessary for the CCR, so we make it generic here instead. | |
42 | */ | |
a62a3861 | 43 | #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) |
29847622 PM |
44 | #define mb() __asm__ __volatile__ ("synco": : :"memory") |
45 | #define rmb() mb() | |
46 | #define wmb() __asm__ __volatile__ ("synco": : :"memory") | |
47 | #define ctrl_barrier() __icbi() | |
fdfc74f9 PM |
48 | #define read_barrier_depends() do { } while(0) |
49 | #else | |
29847622 PM |
50 | #define mb() __asm__ __volatile__ ("": : :"memory") |
51 | #define rmb() mb() | |
52 | #define wmb() __asm__ __volatile__ ("": : :"memory") | |
53 | #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") | |
1da177e4 | 54 | #define read_barrier_depends() do { } while(0) |
fdfc74f9 | 55 | #endif |
1da177e4 LT |
56 | |
57 | #ifdef CONFIG_SMP | |
58 | #define smp_mb() mb() | |
59 | #define smp_rmb() rmb() | |
60 | #define smp_wmb() wmb() | |
61 | #define smp_read_barrier_depends() read_barrier_depends() | |
62 | #else | |
63 | #define smp_mb() barrier() | |
64 | #define smp_rmb() barrier() | |
65 | #define smp_wmb() barrier() | |
66 | #define smp_read_barrier_depends() do { } while(0) | |
67 | #endif | |
68 | ||
357d5946 | 69 | #define set_mb(var, value) do { (void)xchg(&var, value); } while (0) |
1da177e4 | 70 | |
1efe4ce3 SM |
71 | #ifdef CONFIG_GUSA_RB |
72 | #include <asm/cmpxchg-grb.h> | |
73 | #else | |
74 | #include <asm/cmpxchg-irq.h> | |
75 | #endif | |
1da177e4 | 76 | |
00b3aa3f PM |
77 | extern void __xchg_called_with_bad_pointer(void); |
78 | ||
79 | #define __xchg(ptr, x, size) \ | |
80 | ({ \ | |
81 | unsigned long __xchg__res; \ | |
82 | volatile void *__xchg_ptr = (ptr); \ | |
83 | switch (size) { \ | |
84 | case 4: \ | |
85 | __xchg__res = xchg_u32(__xchg_ptr, x); \ | |
86 | break; \ | |
87 | case 1: \ | |
88 | __xchg__res = xchg_u8(__xchg_ptr, x); \ | |
89 | break; \ | |
90 | default: \ | |
91 | __xchg_called_with_bad_pointer(); \ | |
92 | __xchg__res = x; \ | |
93 | break; \ | |
94 | } \ | |
95 | \ | |
96 | __xchg__res; \ | |
97 | }) | |
98 | ||
99 | #define xchg(ptr,x) \ | |
100 | ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) | |
1da177e4 | 101 | |
e4e3b5cc TR |
102 | /* This function doesn't exist, so you'll get a linker error |
103 | * if something tries to do an invalid cmpxchg(). */ | |
104 | extern void __cmpxchg_called_with_bad_pointer(void); | |
105 | ||
106 | #define __HAVE_ARCH_CMPXCHG 1 | |
107 | ||
108 | static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, | |
109 | unsigned long new, int size) | |
110 | { | |
111 | switch (size) { | |
112 | case 4: | |
113 | return __cmpxchg_u32(ptr, old, new); | |
114 | } | |
115 | __cmpxchg_called_with_bad_pointer(); | |
116 | return old; | |
117 | } | |
118 | ||
119 | #define cmpxchg(ptr,o,n) \ | |
120 | ({ \ | |
121 | __typeof__(*(ptr)) _o_ = (o); \ | |
122 | __typeof__(*(ptr)) _n_ = (n); \ | |
123 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
124 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
125 | }) | |
126 | ||
3a2e117e PM |
127 | extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn)); |
128 | ||
1f666587 PM |
129 | extern void *set_exception_table_vec(unsigned int vec, void *handler); |
130 | ||
131 | static inline void *set_exception_table_evt(unsigned int evt, void *handler) | |
132 | { | |
133 | return set_exception_table_vec(evt >> 5, handler); | |
134 | } | |
135 | ||
bd079997 PM |
136 | /* |
137 | * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. | |
138 | */ | |
139 | #ifdef CONFIG_CPU_SH2A | |
140 | extern unsigned int instruction_size(unsigned int insn); | |
0fa70efb | 141 | #elif defined(CONFIG_SUPERH32) |
bd079997 | 142 | #define instruction_size(insn) (2) |
0fa70efb PM |
143 | #else |
144 | #define instruction_size(insn) (4) | |
bd079997 PM |
145 | #endif |
146 | ||
cbaa118e SM |
147 | extern unsigned long cached_to_uncached; |
148 | ||
1da177e4 LT |
149 | /* XXX |
150 | * disable hlt during certain critical i/o operations | |
151 | */ | |
152 | #define HAVE_DISABLE_HLT | |
153 | void disable_hlt(void); | |
154 | void enable_hlt(void); | |
155 | ||
e08f457c | 156 | void default_idle(void); |
aba1030a | 157 | void per_cpu_trap_init(void); |
e08f457c PM |
158 | |
159 | asmlinkage void break_point_trap(void); | |
5a4f7c66 PM |
160 | |
161 | #ifdef CONFIG_SUPERH32 | |
162 | #define BUILD_TRAP_HANDLER(name) \ | |
163 | asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \ | |
164 | unsigned long r6, unsigned long r7, \ | |
165 | struct pt_regs __regs) | |
166 | ||
167 | #define TRAP_HANDLER_DECL \ | |
168 | struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \ | |
b000659b PM |
169 | unsigned int vec = regs->tra; \ |
170 | (void)vec; | |
5a4f7c66 PM |
171 | #else |
172 | #define BUILD_TRAP_HANDLER(name) \ | |
173 | asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs) | |
174 | #define TRAP_HANDLER_DECL | |
175 | #endif | |
176 | ||
177 | BUILD_TRAP_HANDLER(address_error); | |
178 | BUILD_TRAP_HANDLER(debug); | |
179 | BUILD_TRAP_HANDLER(bug); | |
74d99a5e PM |
180 | BUILD_TRAP_HANDLER(fpu_error); |
181 | BUILD_TRAP_HANDLER(fpu_state_restore); | |
e08f457c | 182 | |
1da177e4 LT |
183 | #define arch_align_stack(x) (x) |
184 | ||
a62a3861 PM |
185 | #ifdef CONFIG_SUPERH32 |
186 | # include "system_32.h" | |
187 | #else | |
188 | # include "system_64.h" | |
189 | #endif | |
190 | ||
1da177e4 | 191 | #endif |