Commit | Line | Data |
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9904f22a DB |
1 | /* |
2 | * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
9904f22a DB |
19 | #include <linux/init.h> |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/workqueue.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/platform_device.h> | |
26 | ||
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/spi/spi_bitbang.h> | |
29 | ||
30 | ||
31 | /*----------------------------------------------------------------------*/ | |
32 | ||
33 | /* | |
34 | * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support. | |
35 | * Use this for GPIO or shift-register level hardware APIs. | |
36 | * | |
37 | * spi_bitbang_cs is in spi_device->controller_state, which is unavailable | |
38 | * to glue code. These bitbang setup() and cleanup() routines are always | |
39 | * used, though maybe they're called from controller-aware code. | |
40 | * | |
41 | * chipselect() and friends may use use spi_device->controller_data and | |
42 | * controller registers as appropriate. | |
43 | * | |
44 | * | |
45 | * NOTE: SPI controller pins can often be used as GPIO pins instead, | |
46 | * which means you could use a bitbang driver either to get hardware | |
47 | * working quickly, or testing for differences that aren't speed related. | |
48 | */ | |
49 | ||
50 | struct spi_bitbang_cs { | |
51 | unsigned nsecs; /* (clock cycle time)/2 */ | |
52 | u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs, | |
53 | u32 word, u8 bits); | |
54 | unsigned (*txrx_bufs)(struct spi_device *, | |
55 | u32 (*txrx_word)( | |
56 | struct spi_device *spi, | |
57 | unsigned nsecs, | |
58 | u32 word, u8 bits), | |
59 | unsigned, struct spi_transfer *); | |
60 | }; | |
61 | ||
62 | static unsigned bitbang_txrx_8( | |
63 | struct spi_device *spi, | |
64 | u32 (*txrx_word)(struct spi_device *spi, | |
65 | unsigned nsecs, | |
66 | u32 word, u8 bits), | |
67 | unsigned ns, | |
68 | struct spi_transfer *t | |
69 | ) { | |
70 | unsigned bits = spi->bits_per_word; | |
71 | unsigned count = t->len; | |
72 | const u8 *tx = t->tx_buf; | |
73 | u8 *rx = t->rx_buf; | |
74 | ||
75 | while (likely(count > 0)) { | |
76 | u8 word = 0; | |
77 | ||
78 | if (tx) | |
79 | word = *tx++; | |
80 | word = txrx_word(spi, ns, word, bits); | |
81 | if (rx) | |
82 | *rx++ = word; | |
83 | count -= 1; | |
84 | } | |
85 | return t->len - count; | |
86 | } | |
87 | ||
88 | static unsigned bitbang_txrx_16( | |
89 | struct spi_device *spi, | |
90 | u32 (*txrx_word)(struct spi_device *spi, | |
91 | unsigned nsecs, | |
92 | u32 word, u8 bits), | |
93 | unsigned ns, | |
94 | struct spi_transfer *t | |
95 | ) { | |
96 | unsigned bits = spi->bits_per_word; | |
97 | unsigned count = t->len; | |
98 | const u16 *tx = t->tx_buf; | |
99 | u16 *rx = t->rx_buf; | |
100 | ||
101 | while (likely(count > 1)) { | |
102 | u16 word = 0; | |
103 | ||
104 | if (tx) | |
105 | word = *tx++; | |
106 | word = txrx_word(spi, ns, word, bits); | |
107 | if (rx) | |
108 | *rx++ = word; | |
109 | count -= 2; | |
110 | } | |
111 | return t->len - count; | |
112 | } | |
113 | ||
114 | static unsigned bitbang_txrx_32( | |
115 | struct spi_device *spi, | |
116 | u32 (*txrx_word)(struct spi_device *spi, | |
117 | unsigned nsecs, | |
118 | u32 word, u8 bits), | |
119 | unsigned ns, | |
120 | struct spi_transfer *t | |
121 | ) { | |
122 | unsigned bits = spi->bits_per_word; | |
123 | unsigned count = t->len; | |
124 | const u32 *tx = t->tx_buf; | |
125 | u32 *rx = t->rx_buf; | |
126 | ||
127 | while (likely(count > 3)) { | |
128 | u32 word = 0; | |
129 | ||
130 | if (tx) | |
131 | word = *tx++; | |
132 | word = txrx_word(spi, ns, word, bits); | |
133 | if (rx) | |
134 | *rx++ = word; | |
135 | count -= 4; | |
136 | } | |
137 | return t->len - count; | |
138 | } | |
139 | ||
ff9f4771 | 140 | int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
4cff33f9 ID |
141 | { |
142 | struct spi_bitbang_cs *cs = spi->controller_state; | |
143 | u8 bits_per_word; | |
144 | u32 hz; | |
145 | ||
146 | if (t) { | |
147 | bits_per_word = t->bits_per_word; | |
148 | hz = t->speed_hz; | |
149 | } else { | |
150 | bits_per_word = 0; | |
151 | hz = 0; | |
152 | } | |
153 | ||
154 | /* spi_transfer level calls that work per-word */ | |
155 | if (!bits_per_word) | |
156 | bits_per_word = spi->bits_per_word; | |
157 | if (bits_per_word <= 8) | |
158 | cs->txrx_bufs = bitbang_txrx_8; | |
159 | else if (bits_per_word <= 16) | |
160 | cs->txrx_bufs = bitbang_txrx_16; | |
161 | else if (bits_per_word <= 32) | |
162 | cs->txrx_bufs = bitbang_txrx_32; | |
163 | else | |
164 | return -EINVAL; | |
165 | ||
166 | /* nsecs = (clock period)/2 */ | |
167 | if (!hz) | |
168 | hz = spi->max_speed_hz; | |
1e316d75 DB |
169 | if (hz) { |
170 | cs->nsecs = (1000000000/2) / hz; | |
171 | if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000)) | |
172 | return -EINVAL; | |
173 | } | |
4cff33f9 ID |
174 | |
175 | return 0; | |
176 | } | |
ff9f4771 | 177 | EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer); |
4cff33f9 | 178 | |
9904f22a DB |
179 | /** |
180 | * spi_bitbang_setup - default setup for per-word I/O loops | |
181 | */ | |
182 | int spi_bitbang_setup(struct spi_device *spi) | |
183 | { | |
184 | struct spi_bitbang_cs *cs = spi->controller_state; | |
185 | struct spi_bitbang *bitbang; | |
4cff33f9 | 186 | int retval; |
9904f22a | 187 | |
ccf77cc4 DB |
188 | bitbang = spi_master_get_devdata(spi->master); |
189 | ||
dccd573b DB |
190 | /* Bitbangers can support SPI_CS_HIGH, SPI_3WIRE, and so on; |
191 | * add those to master->flags, and provide the other support. | |
ccf77cc4 | 192 | */ |
dccd573b | 193 | if ((spi->mode & ~(SPI_CPOL|SPI_CPHA|bitbang->flags)) != 0) |
ccf77cc4 DB |
194 | return -EINVAL; |
195 | ||
9904f22a | 196 | if (!cs) { |
e94b1766 | 197 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
9904f22a DB |
198 | if (!cs) |
199 | return -ENOMEM; | |
200 | spi->controller_state = cs; | |
201 | } | |
9904f22a DB |
202 | |
203 | if (!spi->bits_per_word) | |
204 | spi->bits_per_word = 8; | |
205 | ||
9904f22a DB |
206 | /* per-word shift register access, in hardware or bitbanging */ |
207 | cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; | |
208 | if (!cs->txrx_word) | |
209 | return -EINVAL; | |
210 | ||
7f8c7619 | 211 | retval = bitbang->setup_transfer(spi, NULL); |
4cff33f9 ID |
212 | if (retval < 0) |
213 | return retval; | |
9904f22a | 214 | |
1e316d75 | 215 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", |
9904f22a DB |
216 | __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), |
217 | spi->bits_per_word, 2 * cs->nsecs); | |
218 | ||
219 | /* NOTE we _need_ to call chipselect() early, ideally with adapter | |
220 | * setup, unless the hardware defaults cooperate to avoid confusion | |
221 | * between normal (active low) and inverted chipselects. | |
222 | */ | |
223 | ||
224 | /* deselect chip (low or high) */ | |
225 | spin_lock(&bitbang->lock); | |
226 | if (!bitbang->busy) { | |
8275c642 | 227 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); |
9904f22a DB |
228 | ndelay(cs->nsecs); |
229 | } | |
230 | spin_unlock(&bitbang->lock); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | EXPORT_SYMBOL_GPL(spi_bitbang_setup); | |
235 | ||
236 | /** | |
237 | * spi_bitbang_cleanup - default cleanup for per-word I/O loops | |
238 | */ | |
0ffa0285 | 239 | void spi_bitbang_cleanup(struct spi_device *spi) |
9904f22a DB |
240 | { |
241 | kfree(spi->controller_state); | |
242 | } | |
243 | EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); | |
244 | ||
245 | static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) | |
246 | { | |
247 | struct spi_bitbang_cs *cs = spi->controller_state; | |
248 | unsigned nsecs = cs->nsecs; | |
249 | ||
250 | return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); | |
251 | } | |
252 | ||
253 | /*----------------------------------------------------------------------*/ | |
254 | ||
255 | /* | |
256 | * SECOND PART ... simple transfer queue runner. | |
257 | * | |
258 | * This costs a task context per controller, running the queue by | |
259 | * performing each transfer in sequence. Smarter hardware can queue | |
260 | * several DMA transfers at once, and process several controller queues | |
261 | * in parallel; this driver doesn't match such hardware very well. | |
262 | * | |
263 | * Drivers can provide word-at-a-time i/o primitives, or provide | |
264 | * transfer-at-a-time ones to leverage dma or fifo hardware. | |
265 | */ | |
c4028958 | 266 | static void bitbang_work(struct work_struct *work) |
9904f22a | 267 | { |
c4028958 DH |
268 | struct spi_bitbang *bitbang = |
269 | container_of(work, struct spi_bitbang, work); | |
9904f22a DB |
270 | unsigned long flags; |
271 | ||
272 | spin_lock_irqsave(&bitbang->lock, flags); | |
273 | bitbang->busy = 1; | |
274 | while (!list_empty(&bitbang->queue)) { | |
275 | struct spi_message *m; | |
276 | struct spi_device *spi; | |
277 | unsigned nsecs; | |
8275c642 | 278 | struct spi_transfer *t = NULL; |
9904f22a | 279 | unsigned tmp; |
8275c642 | 280 | unsigned cs_change; |
9904f22a | 281 | int status; |
4cff33f9 ID |
282 | int (*setup_transfer)(struct spi_device *, |
283 | struct spi_transfer *); | |
9904f22a DB |
284 | |
285 | m = container_of(bitbang->queue.next, struct spi_message, | |
286 | queue); | |
287 | list_del_init(&m->queue); | |
288 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
289 | ||
8275c642 VW |
290 | /* FIXME this is made-up ... the correct value is known to |
291 | * word-at-a-time bitbang code, and presumably chipselect() | |
292 | * should enforce these requirements too? | |
293 | */ | |
294 | nsecs = 100; | |
9904f22a DB |
295 | |
296 | spi = m->spi; | |
9904f22a | 297 | tmp = 0; |
8275c642 | 298 | cs_change = 1; |
9904f22a | 299 | status = 0; |
4cff33f9 | 300 | setup_transfer = NULL; |
9904f22a | 301 | |
8275c642 | 302 | list_for_each_entry (t, &m->transfers, transfer_list) { |
9904f22a | 303 | |
4cff33f9 ID |
304 | /* override or restore speed and wordsize */ |
305 | if (t->speed_hz || t->bits_per_word) { | |
306 | setup_transfer = bitbang->setup_transfer; | |
307 | if (!setup_transfer) { | |
308 | status = -ENOPROTOOPT; | |
309 | break; | |
310 | } | |
311 | } | |
312 | if (setup_transfer) { | |
313 | status = setup_transfer(spi, t); | |
314 | if (status < 0) | |
315 | break; | |
316 | } | |
317 | ||
8275c642 VW |
318 | /* set up default clock polarity, and activate chip; |
319 | * this implicitly updates clock and spi modes as | |
320 | * previously recorded for this device via setup(). | |
321 | * (and also deselects any other chip that might be | |
322 | * selected ...) | |
323 | */ | |
324 | if (cs_change) { | |
325 | bitbang->chipselect(spi, BITBANG_CS_ACTIVE); | |
9904f22a DB |
326 | ndelay(nsecs); |
327 | } | |
8275c642 | 328 | cs_change = t->cs_change; |
9904f22a DB |
329 | if (!t->tx_buf && !t->rx_buf && t->len) { |
330 | status = -EINVAL; | |
331 | break; | |
332 | } | |
333 | ||
8275c642 VW |
334 | /* transfer data. the lower level code handles any |
335 | * new dma mappings it needs. our caller always gave | |
336 | * us dma-safe buffers. | |
337 | */ | |
9904f22a | 338 | if (t->len) { |
8275c642 VW |
339 | /* REVISIT dma API still needs a designated |
340 | * DMA_ADDR_INVALID; ~0 might be better. | |
9904f22a | 341 | */ |
8275c642 VW |
342 | if (!m->is_dma_mapped) |
343 | t->rx_dma = t->tx_dma = 0; | |
9904f22a DB |
344 | status = bitbang->txrx_bufs(spi, t); |
345 | } | |
346 | if (status != t->len) { | |
347 | if (status > 0) | |
348 | status = -EMSGSIZE; | |
349 | break; | |
350 | } | |
351 | m->actual_length += status; | |
352 | status = 0; | |
353 | ||
354 | /* protocol tweaks before next transfer */ | |
355 | if (t->delay_usecs) | |
356 | udelay(t->delay_usecs); | |
357 | ||
8275c642 | 358 | if (!cs_change) |
9904f22a | 359 | continue; |
8275c642 VW |
360 | if (t->transfer_list.next == &m->transfers) |
361 | break; | |
9904f22a | 362 | |
8275c642 VW |
363 | /* sometimes a short mid-message deselect of the chip |
364 | * may be needed to terminate a mode or command | |
365 | */ | |
366 | ndelay(nsecs); | |
367 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
368 | ndelay(nsecs); | |
9904f22a DB |
369 | } |
370 | ||
9904f22a DB |
371 | m->status = status; |
372 | m->complete(m->context); | |
373 | ||
4cff33f9 ID |
374 | /* restore speed and wordsize */ |
375 | if (setup_transfer) | |
376 | setup_transfer(spi, NULL); | |
377 | ||
8275c642 VW |
378 | /* normally deactivate chipselect ... unless no error and |
379 | * cs_change has hinted that the next message will probably | |
380 | * be for this chip too. | |
381 | */ | |
382 | if (!(status == 0 && cs_change)) { | |
383 | ndelay(nsecs); | |
384 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
385 | ndelay(nsecs); | |
386 | } | |
9904f22a DB |
387 | |
388 | spin_lock_irqsave(&bitbang->lock, flags); | |
389 | } | |
390 | bitbang->busy = 0; | |
391 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
392 | } | |
393 | ||
394 | /** | |
395 | * spi_bitbang_transfer - default submit to transfer queue | |
396 | */ | |
397 | int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m) | |
398 | { | |
399 | struct spi_bitbang *bitbang; | |
400 | unsigned long flags; | |
1e316d75 | 401 | int status = 0; |
9904f22a DB |
402 | |
403 | m->actual_length = 0; | |
404 | m->status = -EINPROGRESS; | |
405 | ||
406 | bitbang = spi_master_get_devdata(spi->master); | |
9904f22a DB |
407 | |
408 | spin_lock_irqsave(&bitbang->lock, flags); | |
1e316d75 DB |
409 | if (!spi->max_speed_hz) |
410 | status = -ENETDOWN; | |
411 | else { | |
412 | list_add_tail(&m->queue, &bitbang->queue); | |
413 | queue_work(bitbang->workqueue, &bitbang->work); | |
414 | } | |
9904f22a DB |
415 | spin_unlock_irqrestore(&bitbang->lock, flags); |
416 | ||
1e316d75 | 417 | return status; |
9904f22a DB |
418 | } |
419 | EXPORT_SYMBOL_GPL(spi_bitbang_transfer); | |
420 | ||
421 | /*----------------------------------------------------------------------*/ | |
422 | ||
423 | /** | |
424 | * spi_bitbang_start - start up a polled/bitbanging SPI master driver | |
425 | * @bitbang: driver handle | |
426 | * | |
427 | * Caller should have zero-initialized all parts of the structure, and then | |
428 | * provided callbacks for chip selection and I/O loops. If the master has | |
429 | * a transfer method, its final step should call spi_bitbang_transfer; or, | |
430 | * that's the default if the transfer routine is not initialized. It should | |
431 | * also set up the bus number and number of chipselects. | |
432 | * | |
433 | * For i/o loops, provide callbacks either per-word (for bitbanging, or for | |
434 | * hardware that basically exposes a shift register) or per-spi_transfer | |
435 | * (which takes better advantage of hardware like fifos or DMA engines). | |
436 | * | |
7f8c7619 HPN |
437 | * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup, |
438 | * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi | |
439 | * master methods. Those methods are the defaults if the bitbang->txrx_bufs | |
440 | * routine isn't initialized. | |
9904f22a DB |
441 | * |
442 | * This routine registers the spi_master, which will process requests in a | |
443 | * dedicated task, keeping IRQs unblocked most of the time. To stop | |
444 | * processing those requests, call spi_bitbang_stop(). | |
445 | */ | |
446 | int spi_bitbang_start(struct spi_bitbang *bitbang) | |
447 | { | |
448 | int status; | |
449 | ||
450 | if (!bitbang->master || !bitbang->chipselect) | |
451 | return -EINVAL; | |
452 | ||
c4028958 | 453 | INIT_WORK(&bitbang->work, bitbang_work); |
9904f22a DB |
454 | spin_lock_init(&bitbang->lock); |
455 | INIT_LIST_HEAD(&bitbang->queue); | |
456 | ||
457 | if (!bitbang->master->transfer) | |
458 | bitbang->master->transfer = spi_bitbang_transfer; | |
459 | if (!bitbang->txrx_bufs) { | |
460 | bitbang->use_dma = 0; | |
461 | bitbang->txrx_bufs = spi_bitbang_bufs; | |
462 | if (!bitbang->master->setup) { | |
ff9f4771 KG |
463 | if (!bitbang->setup_transfer) |
464 | bitbang->setup_transfer = | |
465 | spi_bitbang_setup_transfer; | |
9904f22a DB |
466 | bitbang->master->setup = spi_bitbang_setup; |
467 | bitbang->master->cleanup = spi_bitbang_cleanup; | |
468 | } | |
469 | } else if (!bitbang->master->setup) | |
470 | return -EINVAL; | |
471 | ||
472 | /* this task is the only thing to touch the SPI bits */ | |
473 | bitbang->busy = 0; | |
474 | bitbang->workqueue = create_singlethread_workqueue( | |
49dce689 | 475 | bitbang->master->dev.parent->bus_id); |
9904f22a DB |
476 | if (bitbang->workqueue == NULL) { |
477 | status = -EBUSY; | |
478 | goto err1; | |
479 | } | |
480 | ||
481 | /* driver may get busy before register() returns, especially | |
482 | * if someone registered boardinfo for devices | |
483 | */ | |
484 | status = spi_register_master(bitbang->master); | |
485 | if (status < 0) | |
486 | goto err2; | |
487 | ||
488 | return status; | |
489 | ||
490 | err2: | |
491 | destroy_workqueue(bitbang->workqueue); | |
492 | err1: | |
493 | return status; | |
494 | } | |
495 | EXPORT_SYMBOL_GPL(spi_bitbang_start); | |
496 | ||
497 | /** | |
498 | * spi_bitbang_stop - stops the task providing spi communication | |
499 | */ | |
500 | int spi_bitbang_stop(struct spi_bitbang *bitbang) | |
501 | { | |
a836f585 | 502 | spi_unregister_master(bitbang->master); |
9904f22a | 503 | |
a836f585 | 504 | WARN_ON(!list_empty(&bitbang->queue)); |
9904f22a DB |
505 | |
506 | destroy_workqueue(bitbang->workqueue); | |
507 | ||
9904f22a DB |
508 | return 0; |
509 | } | |
510 | EXPORT_SYMBOL_GPL(spi_bitbang_stop); | |
511 | ||
512 | MODULE_LICENSE("GPL"); | |
513 |