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1da177e4 LT |
1 | /* include/asm-arm/arch-lh7a40x/dma.h |
2 | * | |
2295196c | 3 | * Copyright (C) 2005 Marc Singer |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | */ | |
2295196c MS |
10 | |
11 | typedef enum { | |
12 | DMA_M2M0 = 0, | |
13 | DMA_M2M1 = 1, | |
14 | DMA_M2P0 = 2, /* Tx */ | |
15 | DMA_M2P1 = 3, /* Rx */ | |
16 | DMA_M2P2 = 4, /* Tx */ | |
17 | DMA_M2P3 = 5, /* Rx */ | |
18 | DMA_M2P4 = 6, /* Tx - AC97 */ | |
19 | DMA_M2P5 = 7, /* Rx - AC97 */ | |
20 | DMA_M2P6 = 8, /* Tx */ | |
21 | DMA_M2P7 = 9, /* Rx */ | |
22 | } dma_device_t; | |
23 | ||
24 | #define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ | |
25 | ||
26 | #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) | |
27 | #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) | |
28 | ||
29 | #define DMAC_GIR_MMI1 (1<<11) | |
30 | #define DMAC_GIR_MMI0 (1<<10) | |
31 | #define DMAC_GIR_MPI8 (1<<9) | |
32 | #define DMAC_GIR_MPI9 (1<<8) | |
33 | #define DMAC_GIR_MPI6 (1<<7) | |
34 | #define DMAC_GIR_MPI7 (1<<6) | |
35 | #define DMAC_GIR_MPI4 (1<<5) | |
36 | #define DMAC_GIR_MPI5 (1<<4) | |
37 | #define DMAC_GIR_MPI2 (1<<3) | |
38 | #define DMAC_GIR_MPI3 (1<<2) | |
39 | #define DMAC_GIR_MPI0 (1<<1) | |
40 | #define DMAC_GIR_MPI1 (1<<0) | |
41 | ||
42 | #define DMAC_M2P0 0x0000 | |
43 | #define DMAC_M2P1 0x0040 | |
44 | #define DMAC_M2P2 0x0080 | |
45 | #define DMAC_M2P3 0x00c0 | |
46 | #define DMAC_M2P4 0x0240 | |
47 | #define DMAC_M2P5 0x0200 | |
48 | #define DMAC_M2P6 0x02c0 | |
49 | #define DMAC_M2P7 0x0280 | |
50 | #define DMAC_M2P8 0x0340 | |
51 | #define DMAC_M2P9 0x0300 | |
52 | #define DMAC_M2M0 0x0100 | |
53 | #define DMAC_M2M1 0x0140 | |
54 | ||
55 | #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) | |
56 | #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) | |
57 | #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) | |
58 | #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) | |
59 | #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) | |
60 | #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) | |
61 | #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) | |
62 | #define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) | |
63 | #define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) | |
64 | #define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) | |
65 | #define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) | |
66 | ||
67 | #define DMAC_PCONTROL_ENABLE (1<<4) | |
68 | ||
69 | #define DMAC_PORT_USB 0 | |
70 | #define DMAC_PORT_SDMMC 1 | |
71 | #define DMAC_PORT_AC97_1 2 | |
72 | #define DMAC_PORT_AC97_2 3 | |
73 | #define DMAC_PORT_AC97_3 4 | |
74 | #define DMAC_PORT_UART1 6 | |
75 | #define DMAC_PORT_UART2 7 | |
76 | #define DMAC_PORT_UART3 8 | |
77 | ||
78 | #define DMAC_PSTATUS_CURRSTATE_SHIFT 4 | |
79 | #define DMAC_PSTATUS_CURRSTATE_MASK 0x3 | |
80 | ||
81 | #define DMAC_PSTATUS_NEXTBUF (1<<6) | |
82 | #define DMAC_PSTATUS_STALLRINT (1<<0) | |
83 | ||
84 | #define DMAC_INT_CHE (1<<3) | |
85 | #define DMAC_INT_NFB (1<<1) | |
86 | #define DMAC_INT_STALL (1<<0) |