[linux-2.6] / arch / powerpc / platforms / cell / celleb_scc_epci.c

/*
 * Support for SCC external PCI
 *
 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/pci_regs.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>

#include "celleb_scc.h"
#include "celleb_pci.h"

#define MAX_PCI_DEVICES   32
#define MAX_PCI_FUNCTIONS  8

#define iob()  __asm__ __volatile__("eieio; sync":::"memory")

static inline PCI_IO_ADDR celleb_epci_get_epci_base(
					struct pci_controller *hose)
{
	/*
	 * Note:
	 * Celleb epci uses cfg_addr as a base address for
	 * epci control registers.
	 */

	return hose->cfg_addr;
}

static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
					struct pci_controller *hose)
{
	/*
	 * Note:
	 * Celleb epci uses cfg_data as a base address for
	 * configuration area for epci devices.
	 */

	return hose->cfg_data;
}

static inline void clear_and_disable_master_abort_interrupt(
					struct pci_controller *hose)
{
	PCI_IO_ADDR epci_base;
	PCI_IO_ADDR reg;
	epci_base = celleb_epci_get_epci_base(hose);
	reg = epci_base + PCI_COMMAND;
	out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
}

static int celleb_epci_check_abort(struct pci_controller *hose,
				   PCI_IO_ADDR addr)
{
	PCI_IO_ADDR reg;
	PCI_IO_ADDR epci_base;
	u32 val;

	iob();
	epci_base = celleb_epci_get_epci_base(hose);

	reg = epci_base + PCI_COMMAND;
	val = in_be32(reg);

	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
		out_be32(reg,
			 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));

		/* clear PCI Controller error, FRE, PMFE */
		reg = epci_base + SCC_EPCI_STATUS;
		out_be32(reg, SCC_EPCI_INT_PAI);

		reg = epci_base + SCC_EPCI_VCSR;
		val = in_be32(reg) & 0xffff;
		val |= SCC_EPCI_VCSR_FRE;
		out_be32(reg, val);

		reg = epci_base + SCC_EPCI_VISTAT;
		out_be32(reg, SCC_EPCI_VISTAT_PMFE);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	return PCIBIOS_SUCCESSFUL;
}

static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
		struct pci_controller *hose, unsigned int devfn, int where)
{
	PCI_IO_ADDR addr;

	if (bus != hose->bus)
		addr = celleb_epci_get_epci_cfg(hose) +
		       (((bus->number & 0xff) << 16)
			| ((devfn & 0xff) << 8)
			| (where & 0xff)
			| 0x01000000);
	else
		addr = celleb_epci_get_epci_cfg(hose) +
		       (((devfn & 0xff) << 8) | (where & 0xff));

	pr_debug("EPCI: config_addr = 0x%p\n", addr);

	return addr;
}

static int celleb_epci_read_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 *val)
{
	PCI_IO_ADDR epci_base;
	PCI_IO_ADDR addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);

	if (!celleb_epci_get_epci_cfg(hose))
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		epci_base = celleb_epci_get_epci_base(hose);
		addr = epci_base + where;

		switch (size) {
		case 1:
			*val = in_8(addr);
			break;
		case 2:
			*val = in_be16(addr);
			break;
		case 4:
			*val = in_be32(addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(bus, hose, devfn, where);

		switch (size) {
		case 1:
			*val = in_8(addr);
			break;
		case 2:
			*val = in_le16(addr);
			break;
		case 4:
			*val = in_le32(addr);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	pr_debug("EPCI: "
		 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
		 addr, devfn, where, size, *val);

	return celleb_epci_check_abort(hose, NULL);
}

static int celleb_epci_write_config(struct pci_bus *bus,
			unsigned int devfn, int where, int size, u32 val)
{
	PCI_IO_ADDR epci_base;
	PCI_IO_ADDR addr;
	struct device_node *node;
	struct pci_controller *hose;

	/* allignment check */
	BUG_ON(where % size);

	node = (struct device_node *)bus->sysdata;
	hose = pci_find_hose_for_OF_device(node);


	if (!celleb_epci_get_epci_cfg(hose))
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (bus->number == hose->first_busno && devfn == 0) {
		/* EPCI controller self */

		epci_base = celleb_epci_get_epci_base(hose);
		addr = epci_base + where;

		switch (size) {
		case 1:
			out_8(addr, val);
			break;
		case 2:
			out_be16(addr, val);
			break;
		case 4:
			out_be32(addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}

	} else {

		clear_and_disable_master_abort_interrupt(hose);
		addr = celleb_epci_make_config_addr(bus, hose, devfn, where);

		switch (size) {
		case 1:
			out_8(addr, val);
			break;
		case 2:
			out_le16(addr, val);
			break;
		case 4:
			out_le32(addr, val);
			break;
		default:
			return PCIBIOS_DEVICE_NOT_FOUND;
		}
	}

	return celleb_epci_check_abort(hose, addr);
}

struct pci_ops celleb_epci_ops = {
	.read = celleb_epci_read_config,
	.write = celleb_epci_write_config,
};

/* to be moved in FW */
static int __init celleb_epci_init(struct pci_controller *hose)
{
	u32 val;
	PCI_IO_ADDR reg;
	PCI_IO_ADDR epci_base;
	int hwres = 0;

	epci_base = celleb_epci_get_epci_base(hose);

	/* PCI core reset(Internal bus and PCI clock) */
	reg = epci_base + SCC_EPCI_CKCTRL;
	val = in_be32(reg);
	if (val == 0x00030101)
		hwres = 1;
	else {
		val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set PCI core clock */
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
		out_be32(reg, val);

		/* release PCI core reset (internal bus) */
		val = in_be32(reg);
		val |= SCC_EPCI_CKCTRL_CRST0;
		out_be32(reg, val);

		/* set PCI clock select */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val &= ~SCC_EPCI_CLKRST_CKS_MASK;
		val |= SCC_EPCI_CLKRST_CKS_2;
		out_be32(reg, val);

		/* set arbiter */
		reg = epci_base + SCC_EPCI_ABTSET;
		out_be32(reg, 0x0f1f001f);	/* temporary value */

		/* buffer on */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_BC;
		out_be32(reg, val);

		/* PCI clock enable */
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCKEN;
		out_be32(reg, val);

		/* release PCI core reset (all) */
		reg = epci_base + SCC_EPCI_CKCTRL;
		val = in_be32(reg);
		val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
		out_be32(reg, val);

		/* set base translation registers. (already set by Beat) */

		/* set base address masks. (already set by Beat) */
	}

	/* release interrupt masks and clear all interrupts */
	reg = epci_base + SCC_EPCI_INTSET;
	out_be32(reg, 0x013f011f);	/* all interrupts enable */
	reg = epci_base + SCC_EPCI_VIENAB;
	val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
	out_be32(reg, val);
	reg = epci_base + SCC_EPCI_STATUS;
	out_be32(reg, 0xffffffff);
	reg = epci_base + SCC_EPCI_VISTAT;
	out_be32(reg, 0xffffffff);

	/* disable PCI->IB address translation */
	reg = epci_base + SCC_EPCI_VCSR;
	val = in_be32(reg);
	val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
	out_be32(reg, val);

	/* set base addresses. (no need to set?) */

	/* memory space, bus master enable */
	reg = epci_base + PCI_COMMAND;
	val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
	out_be32(reg, val);

	/* endian mode setup */
	reg = epci_base + SCC_EPCI_ECMODE;
	val = 0x00550155;
	out_be32(reg, val);

	/* set control option */
	reg = epci_base + SCC_EPCI_CNTOPT;
	val = in_be32(reg);
	val |= SCC_EPCI_CNTOPT_O2PMB;
	out_be32(reg, val);

	/* XXX: temporay: set registers for address conversion setup */
	reg = epci_base + SCC_EPCI_CNF10_REG;
	out_be32(reg, 0x80000008);
	reg = epci_base + SCC_EPCI_CNF14_REG;
	out_be32(reg, 0x40000008);

	reg = epci_base + SCC_EPCI_BAM0;
	out_be32(reg, 0x80000000);
	reg = epci_base + SCC_EPCI_BAM1;
	out_be32(reg, 0xe0000000);

	reg = epci_base + SCC_EPCI_PVBAT;
	out_be32(reg, 0x80000000);

	if (!hwres) {
		/* release external PCI reset */
		reg = epci_base + SCC_EPCI_CLKRST;
		val = in_be32(reg);
		val |= SCC_EPCI_CLKRST_PCIRST;
		out_be32(reg, val);
	}

	return 0;
}

static int __init celleb_setup_epci(struct device_node *node,
				    struct pci_controller *hose)
{
	struct resource r;

	pr_debug("PCI: celleb_setup_epci()\n");

	/*
	 * Note:
	 * Celleb epci uses cfg_addr and cfg_data member of
	 * pci_controller structure in irregular way.
	 *
	 * cfg_addr is used to map for control registers of
	 * celleb epci.
	 *
	 * cfg_data is used for configuration area of devices
	 * on Celleb epci buses.
	 */

	if (of_address_to_resource(node, 0, &r))
		goto error;
	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_addr)
		goto error;
	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_addr, (r.end - r.start + 1));

	if (of_address_to_resource(node, 2, &r))
		goto error;
	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
	if (!hose->cfg_data)
		goto error;
	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
		 r.start, (unsigned long)hose->cfg_data, (r.end - r.start + 1));

	hose->ops = &celleb_epci_ops;
	celleb_epci_init(hose);

	return 0;

error:
	if (hose->cfg_addr)
		iounmap(hose->cfg_addr);

	if (hose->cfg_data)
		iounmap(hose->cfg_data);
	return 1;
}

struct celleb_phb_spec celleb_epci_spec __initdata = {
	.setup = celleb_setup_epci,
	.ops = &spiderpci_ops,
	.iowa_init = &spiderpci_iowa_init,
	.iowa_data = (void *)0,
};
Commit	Line	Data
551a3d87 IK	1	/*
	2	* Support for SCC external PCI
	3	*
	4	* (C) Copyright 2004-2007 TOSHIBA CORPORATION
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#undef DEBUG
	22
	23	#include <linux/kernel.h>
	24	#include <linux/threads.h>
	25	#include <linux/pci.h>
	26	#include <linux/init.h>
	27	#include <linux/pci_regs.h>
	28	#include <linux/bootmem.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/irq.h>
	32	#include <asm/prom.h>
551a3d87 IK	33	#include <asm/pci-bridge.h>
	34	#include <asm/ppc-pci.h>
	35
11eef455 IK	36	#include "celleb_scc.h"
11eef455 IK	37	#include "celleb_pci.h"
551a3d87 IK	38
	39	#define MAX_PCI_DEVICES 32
	40	#define MAX_PCI_FUNCTIONS 8
	41
	42	#define iob() __asm__ __volatile__("eieio; sync":::"memory")
	43
da0bd34e	44	static inline PCI_IO_ADDR celleb_epci_get_epci_base(
8388374f IK	45	struct pci_controller *hose)
	46	{
	47	/*
	48	* Note:
	49	* Celleb epci uses cfg_addr as a base address for
	50	* epci control registers.
	51	*/
	52
	53	return hose->cfg_addr;
	54	}
	55
da0bd34e	56	static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
8388374f IK	57	struct pci_controller *hose)
	58	{
	59	/*
	60	* Note:
	61	* Celleb epci uses cfg_data as a base address for
	62	* configuration area for epci devices.
	63	*/
	64
	65	return hose->cfg_data;
	66	}
551a3d87	67
551a3d87 IK	68	static inline void clear_and_disable_master_abort_interrupt(
	69	struct pci_controller *hose)
	70	{
da0bd34e IK	71	PCI_IO_ADDR epci_base;
da0bd34e IK	72	PCI_IO_ADDR reg;
8388374f IK	73	epci_base = celleb_epci_get_epci_base(hose);
	74	reg = epci_base + PCI_COMMAND;
	75	out_be32(reg, in_be32(reg) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
551a3d87 IK	76	}
	77
	78	static int celleb_epci_check_abort(struct pci_controller *hose,
da0bd34e	79	PCI_IO_ADDR addr)
551a3d87	80	{
da0bd34e IK	81	PCI_IO_ADDR reg;
da0bd34e IK	82	PCI_IO_ADDR epci_base;
551a3d87 IK	83	u32 val;
	84
	85	iob();
8388374f	86	epci_base = celleb_epci_get_epci_base(hose);
551a3d87 IK	87
	88	reg = epci_base + PCI_COMMAND;
	89	val = in_be32(reg);
	90
	91	if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
	92	out_be32(reg,
	93	(val & 0xffff) \| (PCI_STATUS_REC_MASTER_ABORT << 16));
	94
	95	/* clear PCI Controller error, FRE, PMFE */
	96	reg = epci_base + SCC_EPCI_STATUS;
	97	out_be32(reg, SCC_EPCI_INT_PAI);
	98
	99	reg = epci_base + SCC_EPCI_VCSR;
	100	val = in_be32(reg) & 0xffff;
	101	val \|= SCC_EPCI_VCSR_FRE;
	102	out_be32(reg, val);
	103
	104	reg = epci_base + SCC_EPCI_VISTAT;
	105	out_be32(reg, SCC_EPCI_VISTAT_PMFE);
	106	return PCIBIOS_DEVICE_NOT_FOUND;
	107	}
	108
	109	return PCIBIOS_SUCCESSFUL;
	110	}
	111
11eef455 IK	112	static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
11eef455 IK	113	struct pci_controller *hose, unsigned int devfn, int where)
551a3d87	114	{
da0bd34e	115	PCI_IO_ADDR addr;
551a3d87	116
0f6e74a3	117	if (bus != hose->bus)
8388374f	118	addr = celleb_epci_get_epci_cfg(hose) +
551a3d87	119	(((bus->number & 0xff) << 16)
2fe37a6e IK	120	\| ((devfn & 0xff) << 8)
	121	\| (where & 0xff)
	122	\| 0x01000000);
551a3d87	123	else
8388374f	124	addr = celleb_epci_get_epci_cfg(hose) +
551a3d87 IK	125	(((devfn & 0xff) << 8) \| (where & 0xff));
551a3d87 IK	126
f1fda895	127	pr_debug("EPCI: config_addr = 0x%p\n", addr);
551a3d87 IK	128
	129	return addr;
	130	}
	131
	132	static int celleb_epci_read_config(struct pci_bus *bus,
2fe37a6e	133	unsigned int devfn, int where, int size, u32 *val)
551a3d87	134	{
da0bd34e IK	135	PCI_IO_ADDR epci_base;
da0bd34e IK	136	PCI_IO_ADDR addr;
551a3d87 IK	137	struct device_node *node;
	138	struct pci_controller *hose;
	139
	140	/* allignment check */
	141	BUG_ON(where % size);
	142
	143	node = (struct device_node *)bus->sysdata;
	144	hose = pci_find_hose_for_OF_device(node);
	145
8388374f	146	if (!celleb_epci_get_epci_cfg(hose))
551a3d87 IK	147	return PCIBIOS_DEVICE_NOT_FOUND;
	148
	149	if (bus->number == hose->first_busno && devfn == 0) {
	150	/* EPCI controller self */
	151
8388374f IK	152	epci_base = celleb_epci_get_epci_base(hose);
8388374f IK	153	addr = epci_base + where;
551a3d87 IK	154
	155	switch (size) {
	156	case 1:
f1fda895	157	*val = in_8(addr);
551a3d87 IK	158	break;
551a3d87 IK	159	case 2:
f1fda895	160	*val = in_be16(addr);
551a3d87 IK	161	break;
551a3d87 IK	162	case 4:
f1fda895	163	*val = in_be32(addr);
551a3d87 IK	164	break;
	165	default:
	166	return PCIBIOS_DEVICE_NOT_FOUND;
	167	}
	168
	169	} else {
	170
	171	clear_and_disable_master_abort_interrupt(hose);
0f6e74a3	172	addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
551a3d87 IK	173
	174	switch (size) {
	175	case 1:
f1fda895	176	*val = in_8(addr);
551a3d87 IK	177	break;
551a3d87 IK	178	case 2:
f1fda895	179	*val = in_le16(addr);
551a3d87 IK	180	break;
551a3d87 IK	181	case 4:
f1fda895	182	*val = in_le32(addr);
551a3d87 IK	183	break;
	184	default:
	185	return PCIBIOS_DEVICE_NOT_FOUND;
	186	}
	187	}
	188
	189	pr_debug("EPCI: "
8388374f	190	"addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
551a3d87 IK	191	addr, devfn, where, size, *val);
551a3d87 IK	192
f1fda895	193	return celleb_epci_check_abort(hose, NULL);
551a3d87 IK	194	}
	195
	196	static int celleb_epci_write_config(struct pci_bus *bus,
	197	unsigned int devfn, int where, int size, u32 val)
	198	{
da0bd34e IK	199	PCI_IO_ADDR epci_base;
da0bd34e IK	200	PCI_IO_ADDR addr;
551a3d87 IK	201	struct device_node *node;
	202	struct pci_controller *hose;
	203
	204	/* allignment check */
	205	BUG_ON(where % size);
	206
	207	node = (struct device_node *)bus->sysdata;
	208	hose = pci_find_hose_for_OF_device(node);
	209
8388374f IK	210
8388374f IK	211	if (!celleb_epci_get_epci_cfg(hose))
551a3d87 IK	212	return PCIBIOS_DEVICE_NOT_FOUND;
	213
	214	if (bus->number == hose->first_busno && devfn == 0) {
	215	/* EPCI controller self */
	216
8388374f IK	217	epci_base = celleb_epci_get_epci_base(hose);
8388374f IK	218	addr = epci_base + where;
551a3d87 IK	219
	220	switch (size) {
	221	case 1:
f1fda895	222	out_8(addr, val);
551a3d87 IK	223	break;
551a3d87 IK	224	case 2:
f1fda895	225	out_be16(addr, val);
551a3d87 IK	226	break;
551a3d87 IK	227	case 4:
f1fda895	228	out_be32(addr, val);
551a3d87 IK	229	break;
	230	default:
	231	return PCIBIOS_DEVICE_NOT_FOUND;
	232	}
	233
	234	} else {
	235
	236	clear_and_disable_master_abort_interrupt(hose);
0f6e74a3	237	addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
551a3d87 IK	238
	239	switch (size) {
	240	case 1:
f1fda895	241	out_8(addr, val);
551a3d87 IK	242	break;
551a3d87 IK	243	case 2:
f1fda895	244	out_le16(addr, val);
551a3d87 IK	245	break;
551a3d87 IK	246	case 4:
f1fda895	247	out_le32(addr, val);
551a3d87 IK	248	break;
	249	default:
	250	return PCIBIOS_DEVICE_NOT_FOUND;
	251	}
	252	}
	253
	254	return celleb_epci_check_abort(hose, addr);
	255	}
	256
	257	struct pci_ops celleb_epci_ops = {
3e02aebb NL	258	.read = celleb_epci_read_config,
3e02aebb NL	259	.write = celleb_epci_write_config,
551a3d87 IK	260	};
	261
	262	/* to be moved in FW */
a4ebd017	263	static int __init celleb_epci_init(struct pci_controller *hose)
551a3d87 IK	264	{
551a3d87 IK	265	u32 val;
da0bd34e IK	266	PCI_IO_ADDR reg;
da0bd34e IK	267	PCI_IO_ADDR epci_base;
551a3d87 IK	268	int hwres = 0;
551a3d87 IK	269
8388374f	270	epci_base = celleb_epci_get_epci_base(hose);
551a3d87 IK	271
	272	/* PCI core reset(Internal bus and PCI clock) */
	273	reg = epci_base + SCC_EPCI_CKCTRL;
	274	val = in_be32(reg);
	275	if (val == 0x00030101)
	276	hwres = 1;
	277	else {
	278	val &= ~(SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
	279	out_be32(reg, val);
	280
	281	/* set PCI core clock */
	282	val = in_be32(reg);
	283	val \|= (SCC_EPCI_CKCTRL_OCLKEN \| SCC_EPCI_CKCTRL_LCLKEN);
	284	out_be32(reg, val);
	285
	286	/* release PCI core reset (internal bus) */
	287	val = in_be32(reg);
	288	val \|= SCC_EPCI_CKCTRL_CRST0;
	289	out_be32(reg, val);
	290
	291	/* set PCI clock select */
	292	reg = epci_base + SCC_EPCI_CLKRST;
	293	val = in_be32(reg);
	294	val &= ~SCC_EPCI_CLKRST_CKS_MASK;
	295	val \|= SCC_EPCI_CLKRST_CKS_2;
	296	out_be32(reg, val);
	297
	298	/* set arbiter */
	299	reg = epci_base + SCC_EPCI_ABTSET;
	300	out_be32(reg, 0x0f1f001f); /* temporary value */
	301
	302	/* buffer on */
	303	reg = epci_base + SCC_EPCI_CLKRST;
	304	val = in_be32(reg);
	305	val \|= SCC_EPCI_CLKRST_BC;
	306	out_be32(reg, val);
	307
	308	/* PCI clock enable */
	309	val = in_be32(reg);
	310	val \|= SCC_EPCI_CLKRST_PCKEN;
	311	out_be32(reg, val);
	312
	313	/* release PCI core reset (all) */
	314	reg = epci_base + SCC_EPCI_CKCTRL;
	315	val = in_be32(reg);
	316	val \|= (SCC_EPCI_CKCTRL_CRST0 \| SCC_EPCI_CKCTRL_CRST1);
	317	out_be32(reg, val);
	318
	319	/* set base translation registers. (already set by Beat) */
	320
	321	/* set base address masks. (already set by Beat) */
	322	}
	323
	324	/* release interrupt masks and clear all interrupts */
	325	reg = epci_base + SCC_EPCI_INTSET;
	326	out_be32(reg, 0x013f011f); /* all interrupts enable */
	327	reg = epci_base + SCC_EPCI_VIENAB;
	328	val = SCC_EPCI_VIENAB_PMPEE \| SCC_EPCI_VIENAB_PMFEE;
	329	out_be32(reg, val);
	330	reg = epci_base + SCC_EPCI_STATUS;
	331	out_be32(reg, 0xffffffff);
	332	reg = epci_base + SCC_EPCI_VISTAT;
	333	out_be32(reg, 0xffffffff);
	334
335	/* disable PCI->IB address translation */
336	reg = epci_base + SCC_EPCI_VCSR;
337	val = in_be32(reg);
338	val &= ~(SCC_EPCI_VCSR_DR \| SCC_EPCI_VCSR_AT);
339	out_be32(reg, val);
340
341	/* set base addresses. (no need to set?) */
342
343	/* memory space, bus master enable */
344	reg = epci_base + PCI_COMMAND;
345	val = PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
346	out_be32(reg, val);
347
348	/* endian mode setup */
349	reg = epci_base + SCC_EPCI_ECMODE;
350	val = 0x00550155;
351	out_be32(reg, val);
352
353	/* set control option */
354	reg = epci_base + SCC_EPCI_CNTOPT;
355	val = in_be32(reg);
356	val \|= SCC_EPCI_CNTOPT_O2PMB;
357	out_be32(reg, val);
358
359	/* XXX: temporay: set registers for address conversion setup */
360	reg = epci_base + SCC_EPCI_CNF10_REG;
361	out_be32(reg, 0x80000008);
362	reg = epci_base + SCC_EPCI_CNF14_REG;
363	out_be32(reg, 0x40000008);
364
365	reg = epci_base + SCC_EPCI_BAM0;
366	out_be32(reg, 0x80000000);
367	reg = epci_base + SCC_EPCI_BAM1;
368	out_be32(reg, 0xe0000000);
369
370	reg = epci_base + SCC_EPCI_PVBAT;
371	out_be32(reg, 0x80000000);
372
373	if (!hwres) {
374	/* release external PCI reset */
375	reg = epci_base + SCC_EPCI_CLKRST;
376	val = in_be32(reg);
377	val \|= SCC_EPCI_CLKRST_PCIRST;
378	out_be32(reg, val);
379	}
380
381	return 0;
382	}
383
6ec859e1 IK	384	static int __init celleb_setup_epci(struct device_node *node,
6ec859e1 IK	385	struct pci_controller *hose)
551a3d87 IK	386	{
	387	struct resource r;
	388
	389	pr_debug("PCI: celleb_setup_epci()\n");
	390
8388374f IK	391	/*
	392	* Note:
	393	* Celleb epci uses cfg_addr and cfg_data member of
	394	* pci_controller structure in irregular way.
	395	*
	396	* cfg_addr is used to map for control registers of
	397	* celleb epci.
	398	*
	399	* cfg_data is used for configuration area of devices
	400	* on Celleb epci buses.
	401	*/
	402
551a3d87 IK	403	if (of_address_to_resource(node, 0, &r))
	404	goto error;
	405	hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
	406	if (!hose->cfg_addr)
	407	goto error;
	408	pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
11eef455	409	r.start, (unsigned long)hose->cfg_addr, (r.end - r.start + 1));
551a3d87 IK	410
	411	if (of_address_to_resource(node, 2, &r))
	412	goto error;
	413	hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
	414	if (!hose->cfg_data)
	415	goto error;
	416	pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
11eef455	417	r.start, (unsigned long)hose->cfg_data, (r.end - r.start + 1));
551a3d87	418
da0bd34e	419	hose->ops = &celleb_epci_ops;
551a3d87 IK	420	celleb_epci_init(hose);
	421
	422	return 0;
	423
	424	error:
da0bd34e IK	425	if (hose->cfg_addr)
	426	iounmap(hose->cfg_addr);
	427
	428	if (hose->cfg_data)
	429	iounmap(hose->cfg_data);
551a3d87 IK	430	return 1;
551a3d87 IK	431	}
6ec859e1 IK	432
	433	struct celleb_phb_spec celleb_epci_spec __initdata = {
	434	.setup = celleb_setup_epci,
	435	.ops = &spiderpci_ops,
	436	.iowa_init = &spiderpci_iowa_init,
	437	.iowa_data = (void *)0,
	438	};