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e0c9905e SS |
1 | /* |
2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/workqueue.h> | |
e0c9905e | 29 | #include <linux/delay.h> |
2f1a74e5 | 30 | #include <linux/clk.h> |
a7bb3909 | 31 | #include <linux/gpio.h> |
e0c9905e SS |
32 | |
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
e0c9905e | 35 | #include <asm/delay.h> |
e0c9905e | 36 | |
dcea83ad | 37 | #include <mach/dma.h> |
a09e64fb RK |
38 | #include <mach/regs-ssp.h> |
39 | #include <mach/ssp.h> | |
40 | #include <mach/pxa2xx_spi.h> | |
e0c9905e SS |
41 | |
42 | MODULE_AUTHOR("Stephen Street"); | |
037cdafe | 43 | MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); |
e0c9905e | 44 | MODULE_LICENSE("GPL"); |
7e38c3c4 | 45 | MODULE_ALIAS("platform:pxa2xx-spi"); |
e0c9905e SS |
46 | |
47 | #define MAX_BUSES 3 | |
48 | ||
f1f640a9 VS |
49 | #define RX_THRESH_DFLT 8 |
50 | #define TX_THRESH_DFLT 8 | |
51 | #define TIMOUT_DFLT 1000 | |
52 | ||
7e964455 NF |
53 | #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR) |
54 | #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK) | |
20b918dc | 55 | #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0) |
7e964455 | 56 | #define MAX_DMA_LEN 8191 |
7ad0ba91 | 57 | #define DMA_ALIGNMENT 8 |
e0c9905e | 58 | |
b97c74bd NF |
59 | /* |
60 | * for testing SSCR1 changes that require SSP restart, basically | |
61 | * everything except the service and interrupt enables, the pxa270 developer | |
62 | * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this | |
63 | * list, but the PXA255 dev man says all bits without really meaning the | |
64 | * service and interrupt enables | |
65 | */ | |
66 | #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | |
8d94cc50 | 67 | | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ |
b97c74bd NF |
68 | | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ |
69 | | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ | |
70 | | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ | |
71 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | |
8d94cc50 | 72 | |
e0c9905e | 73 | #define DEFINE_SSP_REG(reg, off) \ |
cf43369d DB |
74 | static inline u32 read_##reg(void const __iomem *p) \ |
75 | { return __raw_readl(p + (off)); } \ | |
76 | \ | |
77 | static inline void write_##reg(u32 v, void __iomem *p) \ | |
78 | { __raw_writel(v, p + (off)); } | |
e0c9905e SS |
79 | |
80 | DEFINE_SSP_REG(SSCR0, 0x00) | |
81 | DEFINE_SSP_REG(SSCR1, 0x04) | |
82 | DEFINE_SSP_REG(SSSR, 0x08) | |
83 | DEFINE_SSP_REG(SSITR, 0x0c) | |
84 | DEFINE_SSP_REG(SSDR, 0x10) | |
85 | DEFINE_SSP_REG(SSTO, 0x28) | |
86 | DEFINE_SSP_REG(SSPSP, 0x2c) | |
87 | ||
88 | #define START_STATE ((void*)0) | |
89 | #define RUNNING_STATE ((void*)1) | |
90 | #define DONE_STATE ((void*)2) | |
91 | #define ERROR_STATE ((void*)-1) | |
92 | ||
93 | #define QUEUE_RUNNING 0 | |
94 | #define QUEUE_STOPPED 1 | |
95 | ||
96 | struct driver_data { | |
97 | /* Driver model hookup */ | |
98 | struct platform_device *pdev; | |
99 | ||
2f1a74e5 | 100 | /* SSP Info */ |
101 | struct ssp_device *ssp; | |
102 | ||
e0c9905e SS |
103 | /* SPI framework hookup */ |
104 | enum pxa_ssp_type ssp_type; | |
105 | struct spi_master *master; | |
106 | ||
107 | /* PXA hookup */ | |
108 | struct pxa2xx_spi_master *master_info; | |
109 | ||
110 | /* DMA setup stuff */ | |
111 | int rx_channel; | |
112 | int tx_channel; | |
113 | u32 *null_dma_buf; | |
114 | ||
115 | /* SSP register addresses */ | |
cf43369d | 116 | void __iomem *ioaddr; |
e0c9905e SS |
117 | u32 ssdr_physical; |
118 | ||
119 | /* SSP masks*/ | |
120 | u32 dma_cr1; | |
121 | u32 int_cr1; | |
122 | u32 clear_sr; | |
123 | u32 mask_sr; | |
124 | ||
125 | /* Driver message queue */ | |
126 | struct workqueue_struct *workqueue; | |
127 | struct work_struct pump_messages; | |
128 | spinlock_t lock; | |
129 | struct list_head queue; | |
130 | int busy; | |
131 | int run; | |
132 | ||
133 | /* Message Transfer pump */ | |
134 | struct tasklet_struct pump_transfers; | |
135 | ||
136 | /* Current message transfer state info */ | |
137 | struct spi_message* cur_msg; | |
138 | struct spi_transfer* cur_transfer; | |
139 | struct chip_data *cur_chip; | |
140 | size_t len; | |
141 | void *tx; | |
142 | void *tx_end; | |
143 | void *rx; | |
144 | void *rx_end; | |
145 | int dma_mapped; | |
146 | dma_addr_t rx_dma; | |
147 | dma_addr_t tx_dma; | |
148 | size_t rx_map_len; | |
149 | size_t tx_map_len; | |
9708c121 SS |
150 | u8 n_bytes; |
151 | u32 dma_width; | |
8d94cc50 SS |
152 | int (*write)(struct driver_data *drv_data); |
153 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
154 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
155 | void (*cs_control)(u32 command); | |
156 | }; | |
157 | ||
158 | struct chip_data { | |
159 | u32 cr0; | |
160 | u32 cr1; | |
e0c9905e SS |
161 | u32 psp; |
162 | u32 timeout; | |
163 | u8 n_bytes; | |
164 | u32 dma_width; | |
165 | u32 dma_burst_size; | |
166 | u32 threshold; | |
167 | u32 dma_threshold; | |
168 | u8 enable_dma; | |
9708c121 SS |
169 | u8 bits_per_word; |
170 | u32 speed_hz; | |
a7bb3909 EM |
171 | int gpio_cs; |
172 | int gpio_cs_inverted; | |
8d94cc50 SS |
173 | int (*write)(struct driver_data *drv_data); |
174 | int (*read)(struct driver_data *drv_data); | |
e0c9905e SS |
175 | void (*cs_control)(u32 command); |
176 | }; | |
177 | ||
6d5aefb8 | 178 | static void pump_messages(struct work_struct *work); |
e0c9905e | 179 | |
a7bb3909 EM |
180 | static void cs_assert(struct driver_data *drv_data) |
181 | { | |
182 | struct chip_data *chip = drv_data->cur_chip; | |
183 | ||
184 | if (chip->cs_control) { | |
185 | chip->cs_control(PXA2XX_CS_ASSERT); | |
186 | return; | |
187 | } | |
188 | ||
189 | if (gpio_is_valid(chip->gpio_cs)) | |
190 | gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); | |
191 | } | |
192 | ||
193 | static void cs_deassert(struct driver_data *drv_data) | |
194 | { | |
195 | struct chip_data *chip = drv_data->cur_chip; | |
196 | ||
197 | if (chip->cs_control) { | |
2b2562d3 | 198 | chip->cs_control(PXA2XX_CS_DEASSERT); |
a7bb3909 EM |
199 | return; |
200 | } | |
201 | ||
202 | if (gpio_is_valid(chip->gpio_cs)) | |
203 | gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); | |
204 | } | |
205 | ||
e0c9905e SS |
206 | static int flush(struct driver_data *drv_data) |
207 | { | |
208 | unsigned long limit = loops_per_jiffy << 1; | |
209 | ||
cf43369d | 210 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
211 | |
212 | do { | |
213 | while (read_SSSR(reg) & SSSR_RNE) { | |
214 | read_SSDR(reg); | |
215 | } | |
306c68aa | 216 | } while ((read_SSSR(reg) & SSSR_BSY) && --limit); |
e0c9905e SS |
217 | write_SSSR(SSSR_ROR, reg); |
218 | ||
219 | return limit; | |
220 | } | |
221 | ||
8d94cc50 | 222 | static int null_writer(struct driver_data *drv_data) |
e0c9905e | 223 | { |
cf43369d | 224 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 225 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e | 226 | |
8d94cc50 SS |
227 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
228 | || (drv_data->tx == drv_data->tx_end)) | |
229 | return 0; | |
230 | ||
231 | write_SSDR(0, reg); | |
232 | drv_data->tx += n_bytes; | |
233 | ||
234 | return 1; | |
e0c9905e SS |
235 | } |
236 | ||
8d94cc50 | 237 | static int null_reader(struct driver_data *drv_data) |
e0c9905e | 238 | { |
cf43369d | 239 | void __iomem *reg = drv_data->ioaddr; |
9708c121 | 240 | u8 n_bytes = drv_data->n_bytes; |
e0c9905e SS |
241 | |
242 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 243 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
244 | read_SSDR(reg); |
245 | drv_data->rx += n_bytes; | |
246 | } | |
8d94cc50 SS |
247 | |
248 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
249 | } |
250 | ||
8d94cc50 | 251 | static int u8_writer(struct driver_data *drv_data) |
e0c9905e | 252 | { |
cf43369d | 253 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 254 | |
8d94cc50 SS |
255 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
256 | || (drv_data->tx == drv_data->tx_end)) | |
257 | return 0; | |
258 | ||
259 | write_SSDR(*(u8 *)(drv_data->tx), reg); | |
260 | ++drv_data->tx; | |
261 | ||
262 | return 1; | |
e0c9905e SS |
263 | } |
264 | ||
8d94cc50 | 265 | static int u8_reader(struct driver_data *drv_data) |
e0c9905e | 266 | { |
cf43369d | 267 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
268 | |
269 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 270 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
271 | *(u8 *)(drv_data->rx) = read_SSDR(reg); |
272 | ++drv_data->rx; | |
273 | } | |
8d94cc50 SS |
274 | |
275 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
276 | } |
277 | ||
8d94cc50 | 278 | static int u16_writer(struct driver_data *drv_data) |
e0c9905e | 279 | { |
cf43369d | 280 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 281 | |
8d94cc50 SS |
282 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
283 | || (drv_data->tx == drv_data->tx_end)) | |
284 | return 0; | |
285 | ||
286 | write_SSDR(*(u16 *)(drv_data->tx), reg); | |
287 | drv_data->tx += 2; | |
288 | ||
289 | return 1; | |
e0c9905e SS |
290 | } |
291 | ||
8d94cc50 | 292 | static int u16_reader(struct driver_data *drv_data) |
e0c9905e | 293 | { |
cf43369d | 294 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
295 | |
296 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 297 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
298 | *(u16 *)(drv_data->rx) = read_SSDR(reg); |
299 | drv_data->rx += 2; | |
300 | } | |
8d94cc50 SS |
301 | |
302 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e | 303 | } |
8d94cc50 SS |
304 | |
305 | static int u32_writer(struct driver_data *drv_data) | |
e0c9905e | 306 | { |
cf43369d | 307 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 308 | |
8d94cc50 SS |
309 | if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00) |
310 | || (drv_data->tx == drv_data->tx_end)) | |
311 | return 0; | |
312 | ||
313 | write_SSDR(*(u32 *)(drv_data->tx), reg); | |
314 | drv_data->tx += 4; | |
315 | ||
316 | return 1; | |
e0c9905e SS |
317 | } |
318 | ||
8d94cc50 | 319 | static int u32_reader(struct driver_data *drv_data) |
e0c9905e | 320 | { |
cf43369d | 321 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
322 | |
323 | while ((read_SSSR(reg) & SSSR_RNE) | |
8d94cc50 | 324 | && (drv_data->rx < drv_data->rx_end)) { |
e0c9905e SS |
325 | *(u32 *)(drv_data->rx) = read_SSDR(reg); |
326 | drv_data->rx += 4; | |
327 | } | |
8d94cc50 SS |
328 | |
329 | return drv_data->rx == drv_data->rx_end; | |
e0c9905e SS |
330 | } |
331 | ||
332 | static void *next_transfer(struct driver_data *drv_data) | |
333 | { | |
334 | struct spi_message *msg = drv_data->cur_msg; | |
335 | struct spi_transfer *trans = drv_data->cur_transfer; | |
336 | ||
337 | /* Move to next transfer */ | |
338 | if (trans->transfer_list.next != &msg->transfers) { | |
339 | drv_data->cur_transfer = | |
340 | list_entry(trans->transfer_list.next, | |
341 | struct spi_transfer, | |
342 | transfer_list); | |
343 | return RUNNING_STATE; | |
344 | } else | |
345 | return DONE_STATE; | |
346 | } | |
347 | ||
348 | static int map_dma_buffers(struct driver_data *drv_data) | |
349 | { | |
350 | struct spi_message *msg = drv_data->cur_msg; | |
351 | struct device *dev = &msg->spi->dev; | |
352 | ||
353 | if (!drv_data->cur_chip->enable_dma) | |
354 | return 0; | |
355 | ||
356 | if (msg->is_dma_mapped) | |
357 | return drv_data->rx_dma && drv_data->tx_dma; | |
358 | ||
359 | if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx)) | |
360 | return 0; | |
361 | ||
362 | /* Modify setup if rx buffer is null */ | |
363 | if (drv_data->rx == NULL) { | |
364 | *drv_data->null_dma_buf = 0; | |
365 | drv_data->rx = drv_data->null_dma_buf; | |
366 | drv_data->rx_map_len = 4; | |
367 | } else | |
368 | drv_data->rx_map_len = drv_data->len; | |
369 | ||
370 | ||
371 | /* Modify setup if tx buffer is null */ | |
372 | if (drv_data->tx == NULL) { | |
373 | *drv_data->null_dma_buf = 0; | |
374 | drv_data->tx = drv_data->null_dma_buf; | |
375 | drv_data->tx_map_len = 4; | |
376 | } else | |
377 | drv_data->tx_map_len = drv_data->len; | |
378 | ||
393df744 NF |
379 | /* Stream map the tx buffer. Always do DMA_TO_DEVICE first |
380 | * so we flush the cache *before* invalidating it, in case | |
381 | * the tx and rx buffers overlap. | |
382 | */ | |
e0c9905e | 383 | drv_data->tx_dma = dma_map_single(dev, drv_data->tx, |
393df744 NF |
384 | drv_data->tx_map_len, DMA_TO_DEVICE); |
385 | if (dma_mapping_error(dev, drv_data->tx_dma)) | |
386 | return 0; | |
e0c9905e | 387 | |
393df744 NF |
388 | /* Stream map the rx buffer */ |
389 | drv_data->rx_dma = dma_map_single(dev, drv_data->rx, | |
e0c9905e | 390 | drv_data->rx_map_len, DMA_FROM_DEVICE); |
393df744 NF |
391 | if (dma_mapping_error(dev, drv_data->rx_dma)) { |
392 | dma_unmap_single(dev, drv_data->tx_dma, | |
393 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
e0c9905e SS |
394 | return 0; |
395 | } | |
396 | ||
397 | return 1; | |
398 | } | |
399 | ||
400 | static void unmap_dma_buffers(struct driver_data *drv_data) | |
401 | { | |
402 | struct device *dev; | |
403 | ||
404 | if (!drv_data->dma_mapped) | |
405 | return; | |
406 | ||
407 | if (!drv_data->cur_msg->is_dma_mapped) { | |
408 | dev = &drv_data->cur_msg->spi->dev; | |
409 | dma_unmap_single(dev, drv_data->rx_dma, | |
410 | drv_data->rx_map_len, DMA_FROM_DEVICE); | |
411 | dma_unmap_single(dev, drv_data->tx_dma, | |
412 | drv_data->tx_map_len, DMA_TO_DEVICE); | |
413 | } | |
414 | ||
415 | drv_data->dma_mapped = 0; | |
416 | } | |
417 | ||
418 | /* caller already set message->status; dma and pio irqs are blocked */ | |
5daa3ba0 | 419 | static void giveback(struct driver_data *drv_data) |
e0c9905e SS |
420 | { |
421 | struct spi_transfer* last_transfer; | |
5daa3ba0 SS |
422 | unsigned long flags; |
423 | struct spi_message *msg; | |
e0c9905e | 424 | |
5daa3ba0 SS |
425 | spin_lock_irqsave(&drv_data->lock, flags); |
426 | msg = drv_data->cur_msg; | |
427 | drv_data->cur_msg = NULL; | |
428 | drv_data->cur_transfer = NULL; | |
5daa3ba0 SS |
429 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
430 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
431 | ||
432 | last_transfer = list_entry(msg->transfers.prev, | |
e0c9905e SS |
433 | struct spi_transfer, |
434 | transfer_list); | |
435 | ||
8423597d NF |
436 | /* Delay if requested before any change in chip select */ |
437 | if (last_transfer->delay_usecs) | |
438 | udelay(last_transfer->delay_usecs); | |
439 | ||
440 | /* Drop chip select UNLESS cs_change is true or we are returning | |
441 | * a message with an error, or next message is for another chip | |
442 | */ | |
e0c9905e | 443 | if (!last_transfer->cs_change) |
a7bb3909 | 444 | cs_deassert(drv_data); |
8423597d NF |
445 | else { |
446 | struct spi_message *next_msg; | |
447 | ||
448 | /* Holding of cs was hinted, but we need to make sure | |
449 | * the next message is for the same chip. Don't waste | |
450 | * time with the following tests unless this was hinted. | |
451 | * | |
452 | * We cannot postpone this until pump_messages, because | |
453 | * after calling msg->complete (below) the driver that | |
454 | * sent the current message could be unloaded, which | |
455 | * could invalidate the cs_control() callback... | |
456 | */ | |
457 | ||
458 | /* get a pointer to the next message, if any */ | |
459 | spin_lock_irqsave(&drv_data->lock, flags); | |
460 | if (list_empty(&drv_data->queue)) | |
461 | next_msg = NULL; | |
462 | else | |
463 | next_msg = list_entry(drv_data->queue.next, | |
464 | struct spi_message, queue); | |
465 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
466 | ||
467 | /* see if the next and current messages point | |
468 | * to the same chip | |
469 | */ | |
470 | if (next_msg && next_msg->spi != msg->spi) | |
471 | next_msg = NULL; | |
472 | if (!next_msg || msg->state == ERROR_STATE) | |
a7bb3909 | 473 | cs_deassert(drv_data); |
8423597d | 474 | } |
e0c9905e | 475 | |
5daa3ba0 SS |
476 | msg->state = NULL; |
477 | if (msg->complete) | |
478 | msg->complete(msg->context); | |
a7bb3909 EM |
479 | |
480 | drv_data->cur_chip = NULL; | |
e0c9905e SS |
481 | } |
482 | ||
cf43369d | 483 | static int wait_ssp_rx_stall(void const __iomem *ioaddr) |
e0c9905e SS |
484 | { |
485 | unsigned long limit = loops_per_jiffy << 1; | |
486 | ||
306c68aa | 487 | while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit) |
e0c9905e SS |
488 | cpu_relax(); |
489 | ||
490 | return limit; | |
491 | } | |
492 | ||
493 | static int wait_dma_channel_stop(int channel) | |
494 | { | |
495 | unsigned long limit = loops_per_jiffy << 1; | |
496 | ||
306c68aa | 497 | while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) |
e0c9905e SS |
498 | cpu_relax(); |
499 | ||
500 | return limit; | |
501 | } | |
502 | ||
cf43369d | 503 | static void dma_error_stop(struct driver_data *drv_data, const char *msg) |
e0c9905e | 504 | { |
cf43369d | 505 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 506 | |
8d94cc50 SS |
507 | /* Stop and reset */ |
508 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
509 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
510 | write_SSSR(drv_data->clear_sr, reg); | |
511 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
512 | if (drv_data->ssp_type != PXA25x_SSP) | |
513 | write_SSTO(0, reg); | |
514 | flush(drv_data); | |
515 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 516 | |
8d94cc50 | 517 | unmap_dma_buffers(drv_data); |
e0c9905e | 518 | |
8d94cc50 | 519 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 520 | |
8d94cc50 SS |
521 | drv_data->cur_msg->state = ERROR_STATE; |
522 | tasklet_schedule(&drv_data->pump_transfers); | |
523 | } | |
524 | ||
525 | static void dma_transfer_complete(struct driver_data *drv_data) | |
526 | { | |
cf43369d | 527 | void __iomem *reg = drv_data->ioaddr; |
8d94cc50 SS |
528 | struct spi_message *msg = drv_data->cur_msg; |
529 | ||
530 | /* Clear and disable interrupts on SSP and DMA channels*/ | |
531 | write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); | |
532 | write_SSSR(drv_data->clear_sr, reg); | |
533 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
534 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
535 | ||
536 | if (wait_dma_channel_stop(drv_data->rx_channel) == 0) | |
537 | dev_err(&drv_data->pdev->dev, | |
538 | "dma_handler: dma rx channel stop failed\n"); | |
539 | ||
540 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
541 | dev_err(&drv_data->pdev->dev, | |
542 | "dma_transfer: ssp rx stall failed\n"); | |
543 | ||
544 | unmap_dma_buffers(drv_data); | |
545 | ||
546 | /* update the buffer pointer for the amount completed in dma */ | |
547 | drv_data->rx += drv_data->len - | |
548 | (DCMD(drv_data->rx_channel) & DCMD_LENGTH); | |
549 | ||
550 | /* read trailing data from fifo, it does not matter how many | |
551 | * bytes are in the fifo just read until buffer is full | |
552 | * or fifo is empty, which ever occurs first */ | |
553 | drv_data->read(drv_data); | |
554 | ||
555 | /* return count of what was actually read */ | |
556 | msg->actual_length += drv_data->len - | |
557 | (drv_data->rx_end - drv_data->rx); | |
558 | ||
8423597d NF |
559 | /* Transfer delays and chip select release are |
560 | * handled in pump_transfers or giveback | |
561 | */ | |
8d94cc50 SS |
562 | |
563 | /* Move to next transfer */ | |
564 | msg->state = next_transfer(drv_data); | |
565 | ||
566 | /* Schedule transfer tasklet */ | |
567 | tasklet_schedule(&drv_data->pump_transfers); | |
568 | } | |
569 | ||
570 | static void dma_handler(int channel, void *data) | |
571 | { | |
572 | struct driver_data *drv_data = data; | |
573 | u32 irq_status = DCSR(channel) & DMA_INT_MASK; | |
574 | ||
575 | if (irq_status & DCSR_BUSERR) { | |
e0c9905e SS |
576 | |
577 | if (channel == drv_data->tx_channel) | |
8d94cc50 SS |
578 | dma_error_stop(drv_data, |
579 | "dma_handler: " | |
580 | "bad bus address on tx channel"); | |
e0c9905e | 581 | else |
8d94cc50 SS |
582 | dma_error_stop(drv_data, |
583 | "dma_handler: " | |
584 | "bad bus address on rx channel"); | |
585 | return; | |
e0c9905e SS |
586 | } |
587 | ||
588 | /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */ | |
8d94cc50 SS |
589 | if ((channel == drv_data->tx_channel) |
590 | && (irq_status & DCSR_ENDINTR) | |
591 | && (drv_data->ssp_type == PXA25x_SSP)) { | |
e0c9905e SS |
592 | |
593 | /* Wait for rx to stall */ | |
594 | if (wait_ssp_rx_stall(drv_data->ioaddr) == 0) | |
595 | dev_err(&drv_data->pdev->dev, | |
596 | "dma_handler: ssp rx stall failed\n"); | |
597 | ||
8d94cc50 SS |
598 | /* finish this transfer, start the next */ |
599 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
600 | } |
601 | } | |
602 | ||
603 | static irqreturn_t dma_transfer(struct driver_data *drv_data) | |
604 | { | |
605 | u32 irq_status; | |
cf43369d | 606 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
607 | |
608 | irq_status = read_SSSR(reg) & drv_data->mask_sr; | |
609 | if (irq_status & SSSR_ROR) { | |
8d94cc50 | 610 | dma_error_stop(drv_data, "dma_transfer: fifo overrun"); |
e0c9905e SS |
611 | return IRQ_HANDLED; |
612 | } | |
613 | ||
614 | /* Check for false positive timeout */ | |
8d94cc50 SS |
615 | if ((irq_status & SSSR_TINT) |
616 | && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { | |
e0c9905e SS |
617 | write_SSSR(SSSR_TINT, reg); |
618 | return IRQ_HANDLED; | |
619 | } | |
620 | ||
621 | if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { | |
622 | ||
8d94cc50 SS |
623 | /* Clear and disable timeout interrupt, do the rest in |
624 | * dma_transfer_complete */ | |
e0c9905e SS |
625 | if (drv_data->ssp_type != PXA25x_SSP) |
626 | write_SSTO(0, reg); | |
e0c9905e | 627 | |
8d94cc50 SS |
628 | /* finish this transfer, start the next */ |
629 | dma_transfer_complete(drv_data); | |
e0c9905e SS |
630 | |
631 | return IRQ_HANDLED; | |
632 | } | |
633 | ||
634 | /* Opps problem detected */ | |
635 | return IRQ_NONE; | |
636 | } | |
637 | ||
8d94cc50 | 638 | static void int_error_stop(struct driver_data *drv_data, const char* msg) |
e0c9905e | 639 | { |
cf43369d | 640 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 641 | |
8d94cc50 SS |
642 | /* Stop and reset SSP */ |
643 | write_SSSR(drv_data->clear_sr, reg); | |
644 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
645 | if (drv_data->ssp_type != PXA25x_SSP) | |
646 | write_SSTO(0, reg); | |
647 | flush(drv_data); | |
648 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
e0c9905e | 649 | |
8d94cc50 | 650 | dev_err(&drv_data->pdev->dev, "%s\n", msg); |
e0c9905e | 651 | |
8d94cc50 SS |
652 | drv_data->cur_msg->state = ERROR_STATE; |
653 | tasklet_schedule(&drv_data->pump_transfers); | |
654 | } | |
5daa3ba0 | 655 | |
8d94cc50 SS |
656 | static void int_transfer_complete(struct driver_data *drv_data) |
657 | { | |
cf43369d | 658 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 659 | |
8d94cc50 SS |
660 | /* Stop SSP */ |
661 | write_SSSR(drv_data->clear_sr, reg); | |
662 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
663 | if (drv_data->ssp_type != PXA25x_SSP) | |
664 | write_SSTO(0, reg); | |
e0c9905e | 665 | |
8d94cc50 SS |
666 | /* Update total byte transfered return count actual bytes read */ |
667 | drv_data->cur_msg->actual_length += drv_data->len - | |
668 | (drv_data->rx_end - drv_data->rx); | |
e0c9905e | 669 | |
8423597d NF |
670 | /* Transfer delays and chip select release are |
671 | * handled in pump_transfers or giveback | |
672 | */ | |
e0c9905e | 673 | |
8d94cc50 SS |
674 | /* Move to next transfer */ |
675 | drv_data->cur_msg->state = next_transfer(drv_data); | |
e0c9905e | 676 | |
8d94cc50 SS |
677 | /* Schedule transfer tasklet */ |
678 | tasklet_schedule(&drv_data->pump_transfers); | |
679 | } | |
e0c9905e | 680 | |
8d94cc50 SS |
681 | static irqreturn_t interrupt_transfer(struct driver_data *drv_data) |
682 | { | |
cf43369d | 683 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e | 684 | |
8d94cc50 SS |
685 | u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? |
686 | drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; | |
e0c9905e | 687 | |
8d94cc50 | 688 | u32 irq_status = read_SSSR(reg) & irq_mask; |
e0c9905e | 689 | |
8d94cc50 SS |
690 | if (irq_status & SSSR_ROR) { |
691 | int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); | |
692 | return IRQ_HANDLED; | |
693 | } | |
e0c9905e | 694 | |
8d94cc50 SS |
695 | if (irq_status & SSSR_TINT) { |
696 | write_SSSR(SSSR_TINT, reg); | |
697 | if (drv_data->read(drv_data)) { | |
698 | int_transfer_complete(drv_data); | |
699 | return IRQ_HANDLED; | |
700 | } | |
701 | } | |
e0c9905e | 702 | |
8d94cc50 SS |
703 | /* Drain rx fifo, Fill tx fifo and prevent overruns */ |
704 | do { | |
705 | if (drv_data->read(drv_data)) { | |
706 | int_transfer_complete(drv_data); | |
707 | return IRQ_HANDLED; | |
708 | } | |
709 | } while (drv_data->write(drv_data)); | |
e0c9905e | 710 | |
8d94cc50 SS |
711 | if (drv_data->read(drv_data)) { |
712 | int_transfer_complete(drv_data); | |
713 | return IRQ_HANDLED; | |
714 | } | |
e0c9905e | 715 | |
8d94cc50 SS |
716 | if (drv_data->tx == drv_data->tx_end) { |
717 | write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); | |
718 | /* PXA25x_SSP has no timeout, read trailing bytes */ | |
719 | if (drv_data->ssp_type == PXA25x_SSP) { | |
720 | if (!wait_ssp_rx_stall(reg)) | |
721 | { | |
722 | int_error_stop(drv_data, "interrupt_transfer: " | |
723 | "rx stall failed"); | |
724 | return IRQ_HANDLED; | |
725 | } | |
726 | if (!drv_data->read(drv_data)) | |
727 | { | |
728 | int_error_stop(drv_data, | |
729 | "interrupt_transfer: " | |
730 | "trailing byte read failed"); | |
731 | return IRQ_HANDLED; | |
732 | } | |
733 | int_transfer_complete(drv_data); | |
e0c9905e | 734 | } |
e0c9905e SS |
735 | } |
736 | ||
5daa3ba0 SS |
737 | /* We did something */ |
738 | return IRQ_HANDLED; | |
e0c9905e SS |
739 | } |
740 | ||
7d12e780 | 741 | static irqreturn_t ssp_int(int irq, void *dev_id) |
e0c9905e | 742 | { |
c7bec5ab | 743 | struct driver_data *drv_data = dev_id; |
cf43369d | 744 | void __iomem *reg = drv_data->ioaddr; |
e0c9905e SS |
745 | |
746 | if (!drv_data->cur_msg) { | |
5daa3ba0 SS |
747 | |
748 | write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); | |
749 | write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); | |
750 | if (drv_data->ssp_type != PXA25x_SSP) | |
751 | write_SSTO(0, reg); | |
752 | write_SSSR(drv_data->clear_sr, reg); | |
753 | ||
e0c9905e | 754 | dev_err(&drv_data->pdev->dev, "bad message state " |
8d94cc50 | 755 | "in interrupt handler\n"); |
5daa3ba0 | 756 | |
e0c9905e SS |
757 | /* Never fail */ |
758 | return IRQ_HANDLED; | |
759 | } | |
760 | ||
761 | return drv_data->transfer_handler(drv_data); | |
762 | } | |
763 | ||
cf43369d DB |
764 | static int set_dma_burst_and_threshold(struct chip_data *chip, |
765 | struct spi_device *spi, | |
8d94cc50 SS |
766 | u8 bits_per_word, u32 *burst_code, |
767 | u32 *threshold) | |
768 | { | |
769 | struct pxa2xx_spi_chip *chip_info = | |
770 | (struct pxa2xx_spi_chip *)spi->controller_data; | |
771 | int bytes_per_word; | |
772 | int burst_bytes; | |
773 | int thresh_words; | |
774 | int req_burst_size; | |
775 | int retval = 0; | |
776 | ||
777 | /* Set the threshold (in registers) to equal the same amount of data | |
778 | * as represented by burst size (in bytes). The computation below | |
779 | * is (burst_size rounded up to nearest 8 byte, word or long word) | |
780 | * divided by (bytes/register); the tx threshold is the inverse of | |
781 | * the rx, so that there will always be enough data in the rx fifo | |
782 | * to satisfy a burst, and there will always be enough space in the | |
783 | * tx fifo to accept a burst (a tx burst will overwrite the fifo if | |
784 | * there is not enough space), there must always remain enough empty | |
785 | * space in the rx fifo for any data loaded to the tx fifo. | |
786 | * Whenever burst_size (in bytes) equals bits/word, the fifo threshold | |
787 | * will be 8, or half the fifo; | |
788 | * The threshold can only be set to 2, 4 or 8, but not 16, because | |
789 | * to burst 16 to the tx fifo, the fifo would have to be empty; | |
790 | * however, the minimum fifo trigger level is 1, and the tx will | |
791 | * request service when the fifo is at this level, with only 15 spaces. | |
792 | */ | |
793 | ||
794 | /* find bytes/word */ | |
795 | if (bits_per_word <= 8) | |
796 | bytes_per_word = 1; | |
797 | else if (bits_per_word <= 16) | |
798 | bytes_per_word = 2; | |
799 | else | |
800 | bytes_per_word = 4; | |
801 | ||
802 | /* use struct pxa2xx_spi_chip->dma_burst_size if available */ | |
803 | if (chip_info) | |
804 | req_burst_size = chip_info->dma_burst_size; | |
805 | else { | |
806 | switch (chip->dma_burst_size) { | |
807 | default: | |
808 | /* if the default burst size is not set, | |
809 | * do it now */ | |
810 | chip->dma_burst_size = DCMD_BURST8; | |
811 | case DCMD_BURST8: | |
812 | req_burst_size = 8; | |
813 | break; | |
814 | case DCMD_BURST16: | |
815 | req_burst_size = 16; | |
816 | break; | |
817 | case DCMD_BURST32: | |
818 | req_burst_size = 32; | |
819 | break; | |
820 | } | |
821 | } | |
822 | if (req_burst_size <= 8) { | |
823 | *burst_code = DCMD_BURST8; | |
824 | burst_bytes = 8; | |
825 | } else if (req_burst_size <= 16) { | |
826 | if (bytes_per_word == 1) { | |
827 | /* don't burst more than 1/2 the fifo */ | |
828 | *burst_code = DCMD_BURST8; | |
829 | burst_bytes = 8; | |
830 | retval = 1; | |
831 | } else { | |
832 | *burst_code = DCMD_BURST16; | |
833 | burst_bytes = 16; | |
834 | } | |
835 | } else { | |
836 | if (bytes_per_word == 1) { | |
837 | /* don't burst more than 1/2 the fifo */ | |
838 | *burst_code = DCMD_BURST8; | |
839 | burst_bytes = 8; | |
840 | retval = 1; | |
841 | } else if (bytes_per_word == 2) { | |
842 | /* don't burst more than 1/2 the fifo */ | |
843 | *burst_code = DCMD_BURST16; | |
844 | burst_bytes = 16; | |
845 | retval = 1; | |
846 | } else { | |
847 | *burst_code = DCMD_BURST32; | |
848 | burst_bytes = 32; | |
849 | } | |
850 | } | |
851 | ||
852 | thresh_words = burst_bytes / bytes_per_word; | |
853 | ||
854 | /* thresh_words will be between 2 and 8 */ | |
855 | *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT) | |
856 | | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT); | |
857 | ||
858 | return retval; | |
859 | } | |
860 | ||
2f1a74e5 | 861 | static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate) |
862 | { | |
863 | unsigned long ssp_clk = clk_get_rate(ssp->clk); | |
864 | ||
865 | if (ssp->type == PXA25x_SSP) | |
866 | return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8; | |
867 | else | |
868 | return ((ssp_clk / rate - 1) & 0xfff) << 8; | |
869 | } | |
870 | ||
e0c9905e SS |
871 | static void pump_transfers(unsigned long data) |
872 | { | |
873 | struct driver_data *drv_data = (struct driver_data *)data; | |
874 | struct spi_message *message = NULL; | |
875 | struct spi_transfer *transfer = NULL; | |
876 | struct spi_transfer *previous = NULL; | |
877 | struct chip_data *chip = NULL; | |
2f1a74e5 | 878 | struct ssp_device *ssp = drv_data->ssp; |
cf43369d | 879 | void __iomem *reg = drv_data->ioaddr; |
9708c121 SS |
880 | u32 clk_div = 0; |
881 | u8 bits = 0; | |
882 | u32 speed = 0; | |
883 | u32 cr0; | |
8d94cc50 SS |
884 | u32 cr1; |
885 | u32 dma_thresh = drv_data->cur_chip->dma_threshold; | |
886 | u32 dma_burst = drv_data->cur_chip->dma_burst_size; | |
e0c9905e SS |
887 | |
888 | /* Get current state information */ | |
889 | message = drv_data->cur_msg; | |
890 | transfer = drv_data->cur_transfer; | |
891 | chip = drv_data->cur_chip; | |
892 | ||
893 | /* Handle for abort */ | |
894 | if (message->state == ERROR_STATE) { | |
895 | message->status = -EIO; | |
5daa3ba0 | 896 | giveback(drv_data); |
e0c9905e SS |
897 | return; |
898 | } | |
899 | ||
900 | /* Handle end of message */ | |
901 | if (message->state == DONE_STATE) { | |
902 | message->status = 0; | |
5daa3ba0 | 903 | giveback(drv_data); |
e0c9905e SS |
904 | return; |
905 | } | |
906 | ||
8423597d | 907 | /* Delay if requested at end of transfer before CS change */ |
e0c9905e SS |
908 | if (message->state == RUNNING_STATE) { |
909 | previous = list_entry(transfer->transfer_list.prev, | |
910 | struct spi_transfer, | |
911 | transfer_list); | |
912 | if (previous->delay_usecs) | |
913 | udelay(previous->delay_usecs); | |
8423597d NF |
914 | |
915 | /* Drop chip select only if cs_change is requested */ | |
916 | if (previous->cs_change) | |
a7bb3909 | 917 | cs_deassert(drv_data); |
e0c9905e SS |
918 | } |
919 | ||
7e964455 NF |
920 | /* Check for transfers that need multiple DMA segments */ |
921 | if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { | |
922 | ||
923 | /* reject already-mapped transfers; PIO won't always work */ | |
924 | if (message->is_dma_mapped | |
925 | || transfer->rx_dma || transfer->tx_dma) { | |
926 | dev_err(&drv_data->pdev->dev, | |
927 | "pump_transfers: mapped transfer length " | |
20b918dc | 928 | "of %u is greater than %d\n", |
7e964455 NF |
929 | transfer->len, MAX_DMA_LEN); |
930 | message->status = -EINVAL; | |
931 | giveback(drv_data); | |
932 | return; | |
933 | } | |
934 | ||
935 | /* warn ... we force this to PIO mode */ | |
936 | if (printk_ratelimit()) | |
937 | dev_warn(&message->spi->dev, "pump_transfers: " | |
938 | "DMA disabled for transfer length %ld " | |
939 | "greater than %d\n", | |
940 | (long)drv_data->len, MAX_DMA_LEN); | |
8d94cc50 SS |
941 | } |
942 | ||
e0c9905e SS |
943 | /* Setup the transfer state based on the type of transfer */ |
944 | if (flush(drv_data) == 0) { | |
945 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
946 | message->status = -EIO; | |
5daa3ba0 | 947 | giveback(drv_data); |
e0c9905e SS |
948 | return; |
949 | } | |
9708c121 SS |
950 | drv_data->n_bytes = chip->n_bytes; |
951 | drv_data->dma_width = chip->dma_width; | |
e0c9905e SS |
952 | drv_data->tx = (void *)transfer->tx_buf; |
953 | drv_data->tx_end = drv_data->tx + transfer->len; | |
954 | drv_data->rx = transfer->rx_buf; | |
955 | drv_data->rx_end = drv_data->rx + transfer->len; | |
956 | drv_data->rx_dma = transfer->rx_dma; | |
957 | drv_data->tx_dma = transfer->tx_dma; | |
8d94cc50 | 958 | drv_data->len = transfer->len & DCMD_LENGTH; |
e0c9905e SS |
959 | drv_data->write = drv_data->tx ? chip->write : null_writer; |
960 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
9708c121 SS |
961 | |
962 | /* Change speed and bit per word on a per transfer */ | |
8d94cc50 | 963 | cr0 = chip->cr0; |
9708c121 SS |
964 | if (transfer->speed_hz || transfer->bits_per_word) { |
965 | ||
9708c121 SS |
966 | bits = chip->bits_per_word; |
967 | speed = chip->speed_hz; | |
968 | ||
969 | if (transfer->speed_hz) | |
970 | speed = transfer->speed_hz; | |
971 | ||
972 | if (transfer->bits_per_word) | |
973 | bits = transfer->bits_per_word; | |
974 | ||
2f1a74e5 | 975 | clk_div = ssp_get_clk_div(ssp, speed); |
9708c121 SS |
976 | |
977 | if (bits <= 8) { | |
978 | drv_data->n_bytes = 1; | |
979 | drv_data->dma_width = DCMD_WIDTH1; | |
980 | drv_data->read = drv_data->read != null_reader ? | |
981 | u8_reader : null_reader; | |
982 | drv_data->write = drv_data->write != null_writer ? | |
983 | u8_writer : null_writer; | |
984 | } else if (bits <= 16) { | |
985 | drv_data->n_bytes = 2; | |
986 | drv_data->dma_width = DCMD_WIDTH2; | |
987 | drv_data->read = drv_data->read != null_reader ? | |
988 | u16_reader : null_reader; | |
989 | drv_data->write = drv_data->write != null_writer ? | |
990 | u16_writer : null_writer; | |
991 | } else if (bits <= 32) { | |
992 | drv_data->n_bytes = 4; | |
993 | drv_data->dma_width = DCMD_WIDTH4; | |
994 | drv_data->read = drv_data->read != null_reader ? | |
995 | u32_reader : null_reader; | |
996 | drv_data->write = drv_data->write != null_writer ? | |
997 | u32_writer : null_writer; | |
998 | } | |
8d94cc50 SS |
999 | /* if bits/word is changed in dma mode, then must check the |
1000 | * thresholds and burst also */ | |
1001 | if (chip->enable_dma) { | |
1002 | if (set_dma_burst_and_threshold(chip, message->spi, | |
1003 | bits, &dma_burst, | |
1004 | &dma_thresh)) | |
1005 | if (printk_ratelimit()) | |
1006 | dev_warn(&message->spi->dev, | |
7e964455 | 1007 | "pump_transfers: " |
8d94cc50 SS |
1008 | "DMA burst size reduced to " |
1009 | "match bits_per_word\n"); | |
1010 | } | |
9708c121 SS |
1011 | |
1012 | cr0 = clk_div | |
1013 | | SSCR0_Motorola | |
5daa3ba0 | 1014 | | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
9708c121 SS |
1015 | | SSCR0_SSE |
1016 | | (bits > 16 ? SSCR0_EDSS : 0); | |
9708c121 SS |
1017 | } |
1018 | ||
e0c9905e SS |
1019 | message->state = RUNNING_STATE; |
1020 | ||
7e964455 NF |
1021 | /* Try to map dma buffer and do a dma transfer if successful, but |
1022 | * only if the length is non-zero and less than MAX_DMA_LEN. | |
1023 | * | |
1024 | * Zero-length non-descriptor DMA is illegal on PXA2xx; force use | |
1025 | * of PIO instead. Care is needed above because the transfer may | |
1026 | * have have been passed with buffers that are already dma mapped. | |
1027 | * A zero-length transfer in PIO mode will not try to write/read | |
1028 | * to/from the buffers | |
1029 | * | |
1030 | * REVISIT large transfers are exactly where we most want to be | |
1031 | * using DMA. If this happens much, split those transfers into | |
1032 | * multiple DMA segments rather than forcing PIO. | |
1033 | */ | |
1034 | drv_data->dma_mapped = 0; | |
1035 | if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN) | |
1036 | drv_data->dma_mapped = map_dma_buffers(drv_data); | |
1037 | if (drv_data->dma_mapped) { | |
e0c9905e SS |
1038 | |
1039 | /* Ensure we have the correct interrupt handler */ | |
1040 | drv_data->transfer_handler = dma_transfer; | |
1041 | ||
1042 | /* Setup rx DMA Channel */ | |
1043 | DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; | |
1044 | DSADR(drv_data->rx_channel) = drv_data->ssdr_physical; | |
1045 | DTADR(drv_data->rx_channel) = drv_data->rx_dma; | |
1046 | if (drv_data->rx == drv_data->null_dma_buf) | |
1047 | /* No target address increment */ | |
1048 | DCMD(drv_data->rx_channel) = DCMD_FLOWSRC | |
9708c121 | 1049 | | drv_data->dma_width |
8d94cc50 | 1050 | | dma_burst |
e0c9905e SS |
1051 | | drv_data->len; |
1052 | else | |
1053 | DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR | |
1054 | | DCMD_FLOWSRC | |
9708c121 | 1055 | | drv_data->dma_width |
8d94cc50 | 1056 | | dma_burst |
e0c9905e SS |
1057 | | drv_data->len; |
1058 | ||
1059 | /* Setup tx DMA Channel */ | |
1060 | DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; | |
1061 | DSADR(drv_data->tx_channel) = drv_data->tx_dma; | |
1062 | DTADR(drv_data->tx_channel) = drv_data->ssdr_physical; | |
1063 | if (drv_data->tx == drv_data->null_dma_buf) | |
1064 | /* No source address increment */ | |
1065 | DCMD(drv_data->tx_channel) = DCMD_FLOWTRG | |
9708c121 | 1066 | | drv_data->dma_width |
8d94cc50 | 1067 | | dma_burst |
e0c9905e SS |
1068 | | drv_data->len; |
1069 | else | |
1070 | DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR | |
1071 | | DCMD_FLOWTRG | |
9708c121 | 1072 | | drv_data->dma_width |
8d94cc50 | 1073 | | dma_burst |
e0c9905e SS |
1074 | | drv_data->len; |
1075 | ||
1076 | /* Enable dma end irqs on SSP to detect end of transfer */ | |
1077 | if (drv_data->ssp_type == PXA25x_SSP) | |
1078 | DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN; | |
1079 | ||
8d94cc50 SS |
1080 | /* Clear status and start DMA engine */ |
1081 | cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; | |
e0c9905e SS |
1082 | write_SSSR(drv_data->clear_sr, reg); |
1083 | DCSR(drv_data->rx_channel) |= DCSR_RUN; | |
1084 | DCSR(drv_data->tx_channel) |= DCSR_RUN; | |
e0c9905e SS |
1085 | } else { |
1086 | /* Ensure we have the correct interrupt handler */ | |
1087 | drv_data->transfer_handler = interrupt_transfer; | |
1088 | ||
8d94cc50 SS |
1089 | /* Clear status */ |
1090 | cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; | |
e0c9905e | 1091 | write_SSSR(drv_data->clear_sr, reg); |
8d94cc50 SS |
1092 | } |
1093 | ||
1094 | /* see if we need to reload the config registers */ | |
1095 | if ((read_SSCR0(reg) != cr0) | |
1096 | || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) != | |
1097 | (cr1 & SSCR1_CHANGE_MASK)) { | |
1098 | ||
b97c74bd | 1099 | /* stop the SSP, and update the other bits */ |
8d94cc50 | 1100 | write_SSCR0(cr0 & ~SSCR0_SSE, reg); |
e0c9905e SS |
1101 | if (drv_data->ssp_type != PXA25x_SSP) |
1102 | write_SSTO(chip->timeout, reg); | |
b97c74bd NF |
1103 | /* first set CR1 without interrupt and service enables */ |
1104 | write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg); | |
1105 | /* restart the SSP */ | |
8d94cc50 | 1106 | write_SSCR0(cr0, reg); |
b97c74bd | 1107 | |
8d94cc50 SS |
1108 | } else { |
1109 | if (drv_data->ssp_type != PXA25x_SSP) | |
1110 | write_SSTO(chip->timeout, reg); | |
e0c9905e | 1111 | } |
b97c74bd | 1112 | |
a7bb3909 | 1113 | cs_assert(drv_data); |
b97c74bd NF |
1114 | |
1115 | /* after chip select, release the data by enabling service | |
1116 | * requests and interrupts, without changing any mode bits */ | |
1117 | write_SSCR1(cr1, reg); | |
e0c9905e SS |
1118 | } |
1119 | ||
6d5aefb8 | 1120 | static void pump_messages(struct work_struct *work) |
e0c9905e | 1121 | { |
6d5aefb8 DH |
1122 | struct driver_data *drv_data = |
1123 | container_of(work, struct driver_data, pump_messages); | |
e0c9905e SS |
1124 | unsigned long flags; |
1125 | ||
1126 | /* Lock queue and check for queue work */ | |
1127 | spin_lock_irqsave(&drv_data->lock, flags); | |
1128 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
1129 | drv_data->busy = 0; | |
1130 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1131 | return; | |
1132 | } | |
1133 | ||
1134 | /* Make sure we are not already running a message */ | |
1135 | if (drv_data->cur_msg) { | |
1136 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1137 | return; | |
1138 | } | |
1139 | ||
1140 | /* Extract head of queue */ | |
1141 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
1142 | struct spi_message, queue); | |
1143 | list_del_init(&drv_data->cur_msg->queue); | |
e0c9905e SS |
1144 | |
1145 | /* Initial message state*/ | |
1146 | drv_data->cur_msg->state = START_STATE; | |
1147 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
1148 | struct spi_transfer, | |
1149 | transfer_list); | |
1150 | ||
8d94cc50 SS |
1151 | /* prepare to setup the SSP, in pump_transfers, using the per |
1152 | * chip configuration */ | |
e0c9905e | 1153 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
e0c9905e SS |
1154 | |
1155 | /* Mark as busy and launch transfers */ | |
1156 | tasklet_schedule(&drv_data->pump_transfers); | |
5daa3ba0 SS |
1157 | |
1158 | drv_data->busy = 1; | |
1159 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
e0c9905e SS |
1160 | } |
1161 | ||
1162 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
1163 | { | |
1164 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1165 | unsigned long flags; | |
1166 | ||
1167 | spin_lock_irqsave(&drv_data->lock, flags); | |
1168 | ||
1169 | if (drv_data->run == QUEUE_STOPPED) { | |
1170 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1171 | return -ESHUTDOWN; | |
1172 | } | |
1173 | ||
1174 | msg->actual_length = 0; | |
1175 | msg->status = -EINPROGRESS; | |
1176 | msg->state = START_STATE; | |
1177 | ||
1178 | list_add_tail(&msg->queue, &drv_data->queue); | |
1179 | ||
1180 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1181 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1182 | ||
1183 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
dccd573b DB |
1188 | /* the spi->mode bits understood by this driver: */ |
1189 | #define MODEBITS (SPI_CPOL | SPI_CPHA) | |
1190 | ||
a7bb3909 EM |
1191 | static int setup_cs(struct spi_device *spi, struct chip_data *chip, |
1192 | struct pxa2xx_spi_chip *chip_info) | |
1193 | { | |
1194 | int err = 0; | |
1195 | ||
1196 | if (chip == NULL || chip_info == NULL) | |
1197 | return 0; | |
1198 | ||
1199 | /* NOTE: setup() can be called multiple times, possibly with | |
1200 | * different chip_info, release previously requested GPIO | |
1201 | */ | |
1202 | if (gpio_is_valid(chip->gpio_cs)) | |
1203 | gpio_free(chip->gpio_cs); | |
1204 | ||
1205 | /* If (*cs_control) is provided, ignore GPIO chip select */ | |
1206 | if (chip_info->cs_control) { | |
1207 | chip->cs_control = chip_info->cs_control; | |
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | if (gpio_is_valid(chip_info->gpio_cs)) { | |
1212 | err = gpio_request(chip_info->gpio_cs, "SPI_CS"); | |
1213 | if (err) { | |
1214 | dev_err(&spi->dev, "failed to request chip select " | |
1215 | "GPIO%d\n", chip_info->gpio_cs); | |
1216 | return err; | |
1217 | } | |
1218 | ||
1219 | chip->gpio_cs = chip_info->gpio_cs; | |
1220 | chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; | |
1221 | ||
1222 | err = gpio_direction_output(chip->gpio_cs, | |
1223 | !chip->gpio_cs_inverted); | |
1224 | } | |
1225 | ||
1226 | return err; | |
1227 | } | |
1228 | ||
e0c9905e SS |
1229 | static int setup(struct spi_device *spi) |
1230 | { | |
1231 | struct pxa2xx_spi_chip *chip_info = NULL; | |
1232 | struct chip_data *chip; | |
1233 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
2f1a74e5 | 1234 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e | 1235 | unsigned int clk_div; |
f1f640a9 VS |
1236 | uint tx_thres = TX_THRESH_DFLT; |
1237 | uint rx_thres = RX_THRESH_DFLT; | |
e0c9905e SS |
1238 | |
1239 | if (!spi->bits_per_word) | |
1240 | spi->bits_per_word = 8; | |
1241 | ||
1242 | if (drv_data->ssp_type != PXA25x_SSP | |
8d94cc50 SS |
1243 | && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) { |
1244 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1245 | "b/w not 4-32 for type non-PXA25x_SSP\n", | |
1246 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1247 | return -EINVAL; |
8d94cc50 SS |
1248 | } |
1249 | else if (drv_data->ssp_type == PXA25x_SSP | |
1250 | && (spi->bits_per_word < 4 | |
1251 | || spi->bits_per_word > 16)) { | |
1252 | dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d " | |
1253 | "b/w not 4-16 for type PXA25x_SSP\n", | |
1254 | drv_data->ssp_type, spi->bits_per_word); | |
e0c9905e | 1255 | return -EINVAL; |
8d94cc50 | 1256 | } |
e0c9905e | 1257 | |
dccd573b DB |
1258 | if (spi->mode & ~MODEBITS) { |
1259 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
1260 | spi->mode & ~MODEBITS); | |
1261 | return -EINVAL; | |
1262 | } | |
1263 | ||
8d94cc50 | 1264 | /* Only alloc on first setup */ |
e0c9905e | 1265 | chip = spi_get_ctldata(spi); |
8d94cc50 | 1266 | if (!chip) { |
e0c9905e | 1267 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
8d94cc50 SS |
1268 | if (!chip) { |
1269 | dev_err(&spi->dev, | |
1270 | "failed setup: can't allocate chip data\n"); | |
e0c9905e | 1271 | return -ENOMEM; |
8d94cc50 | 1272 | } |
e0c9905e | 1273 | |
a7bb3909 | 1274 | chip->gpio_cs = -1; |
e0c9905e | 1275 | chip->enable_dma = 0; |
f1f640a9 | 1276 | chip->timeout = TIMOUT_DFLT; |
e0c9905e SS |
1277 | chip->dma_burst_size = drv_data->master_info->enable_dma ? |
1278 | DCMD_BURST8 : 0; | |
e0c9905e SS |
1279 | } |
1280 | ||
8d94cc50 SS |
1281 | /* protocol drivers may change the chip settings, so... |
1282 | * if chip_info exists, use it */ | |
1283 | chip_info = spi->controller_data; | |
1284 | ||
e0c9905e | 1285 | /* chip_info isn't always needed */ |
8d94cc50 | 1286 | chip->cr1 = 0; |
e0c9905e | 1287 | if (chip_info) { |
f1f640a9 VS |
1288 | if (chip_info->timeout) |
1289 | chip->timeout = chip_info->timeout; | |
1290 | if (chip_info->tx_threshold) | |
1291 | tx_thres = chip_info->tx_threshold; | |
1292 | if (chip_info->rx_threshold) | |
1293 | rx_thres = chip_info->rx_threshold; | |
1294 | chip->enable_dma = drv_data->master_info->enable_dma; | |
e0c9905e | 1295 | chip->dma_threshold = 0; |
e0c9905e SS |
1296 | if (chip_info->enable_loopback) |
1297 | chip->cr1 = SSCR1_LBM; | |
1298 | } | |
1299 | ||
f1f640a9 VS |
1300 | chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | |
1301 | (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); | |
1302 | ||
8d94cc50 SS |
1303 | /* set dma burst and threshold outside of chip_info path so that if |
1304 | * chip_info goes away after setting chip->enable_dma, the | |
1305 | * burst and threshold can still respond to changes in bits_per_word */ | |
1306 | if (chip->enable_dma) { | |
1307 | /* set up legal burst and threshold for dma */ | |
1308 | if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word, | |
1309 | &chip->dma_burst_size, | |
1310 | &chip->dma_threshold)) { | |
1311 | dev_warn(&spi->dev, "in setup: DMA burst size reduced " | |
1312 | "to match bits_per_word\n"); | |
1313 | } | |
1314 | } | |
1315 | ||
2f1a74e5 | 1316 | clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz); |
9708c121 | 1317 | chip->speed_hz = spi->max_speed_hz; |
e0c9905e SS |
1318 | |
1319 | chip->cr0 = clk_div | |
1320 | | SSCR0_Motorola | |
5daa3ba0 SS |
1321 | | SSCR0_DataSize(spi->bits_per_word > 16 ? |
1322 | spi->bits_per_word - 16 : spi->bits_per_word) | |
e0c9905e SS |
1323 | | SSCR0_SSE |
1324 | | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); | |
7f6ee1ad JC |
1325 | chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); |
1326 | chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) | |
1327 | | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); | |
e0c9905e SS |
1328 | |
1329 | /* NOTE: PXA25x_SSP _could_ use external clocking ... */ | |
1330 | if (drv_data->ssp_type != PXA25x_SSP) | |
f1f640a9 | 1331 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1332 | spi->bits_per_word, |
2f1a74e5 | 1333 | clk_get_rate(ssp->clk) |
e0c9905e | 1334 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1335 | spi->mode & 0x3, |
1336 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e | 1337 | else |
f1f640a9 | 1338 | dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n", |
e0c9905e | 1339 | spi->bits_per_word, |
f1f640a9 | 1340 | clk_get_rate(ssp->clk) / 2 |
e0c9905e | 1341 | / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)), |
f1f640a9 VS |
1342 | spi->mode & 0x3, |
1343 | chip->enable_dma ? "DMA" : "PIO"); | |
e0c9905e SS |
1344 | |
1345 | if (spi->bits_per_word <= 8) { | |
1346 | chip->n_bytes = 1; | |
1347 | chip->dma_width = DCMD_WIDTH1; | |
1348 | chip->read = u8_reader; | |
1349 | chip->write = u8_writer; | |
1350 | } else if (spi->bits_per_word <= 16) { | |
1351 | chip->n_bytes = 2; | |
1352 | chip->dma_width = DCMD_WIDTH2; | |
1353 | chip->read = u16_reader; | |
1354 | chip->write = u16_writer; | |
1355 | } else if (spi->bits_per_word <= 32) { | |
1356 | chip->cr0 |= SSCR0_EDSS; | |
1357 | chip->n_bytes = 4; | |
1358 | chip->dma_width = DCMD_WIDTH4; | |
1359 | chip->read = u32_reader; | |
1360 | chip->write = u32_writer; | |
1361 | } else { | |
1362 | dev_err(&spi->dev, "invalid wordsize\n"); | |
e0c9905e SS |
1363 | return -ENODEV; |
1364 | } | |
9708c121 | 1365 | chip->bits_per_word = spi->bits_per_word; |
e0c9905e SS |
1366 | |
1367 | spi_set_ctldata(spi, chip); | |
1368 | ||
a7bb3909 | 1369 | return setup_cs(spi, chip, chip_info); |
e0c9905e SS |
1370 | } |
1371 | ||
0ffa0285 | 1372 | static void cleanup(struct spi_device *spi) |
e0c9905e | 1373 | { |
0ffa0285 | 1374 | struct chip_data *chip = spi_get_ctldata(spi); |
e0c9905e | 1375 | |
7348d82a DR |
1376 | if (!chip) |
1377 | return; | |
1378 | ||
a7bb3909 EM |
1379 | if (gpio_is_valid(chip->gpio_cs)) |
1380 | gpio_free(chip->gpio_cs); | |
1381 | ||
e0c9905e SS |
1382 | kfree(chip); |
1383 | } | |
1384 | ||
d1e44d9c | 1385 | static int __init init_queue(struct driver_data *drv_data) |
e0c9905e SS |
1386 | { |
1387 | INIT_LIST_HEAD(&drv_data->queue); | |
1388 | spin_lock_init(&drv_data->lock); | |
1389 | ||
1390 | drv_data->run = QUEUE_STOPPED; | |
1391 | drv_data->busy = 0; | |
1392 | ||
1393 | tasklet_init(&drv_data->pump_transfers, | |
1394 | pump_transfers, (unsigned long)drv_data); | |
1395 | ||
6d5aefb8 | 1396 | INIT_WORK(&drv_data->pump_messages, pump_messages); |
e0c9905e | 1397 | drv_data->workqueue = create_singlethread_workqueue( |
6c7377ab | 1398 | dev_name(drv_data->master->dev.parent)); |
e0c9905e SS |
1399 | if (drv_data->workqueue == NULL) |
1400 | return -EBUSY; | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | static int start_queue(struct driver_data *drv_data) | |
1406 | { | |
1407 | unsigned long flags; | |
1408 | ||
1409 | spin_lock_irqsave(&drv_data->lock, flags); | |
1410 | ||
1411 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1412 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1413 | return -EBUSY; | |
1414 | } | |
1415 | ||
1416 | drv_data->run = QUEUE_RUNNING; | |
1417 | drv_data->cur_msg = NULL; | |
1418 | drv_data->cur_transfer = NULL; | |
1419 | drv_data->cur_chip = NULL; | |
1420 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1421 | ||
1422 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | static int stop_queue(struct driver_data *drv_data) | |
1428 | { | |
1429 | unsigned long flags; | |
1430 | unsigned limit = 500; | |
1431 | int status = 0; | |
1432 | ||
1433 | spin_lock_irqsave(&drv_data->lock, flags); | |
1434 | ||
1435 | /* This is a bit lame, but is optimized for the common execution path. | |
1436 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1437 | * execution path (pump_messages) would be required to call wake_up or | |
1438 | * friends on every SPI message. Do this instead */ | |
1439 | drv_data->run = QUEUE_STOPPED; | |
1440 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1441 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1442 | msleep(10); | |
1443 | spin_lock_irqsave(&drv_data->lock, flags); | |
1444 | } | |
1445 | ||
1446 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1447 | status = -EBUSY; | |
1448 | ||
1449 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1450 | ||
1451 | return status; | |
1452 | } | |
1453 | ||
1454 | static int destroy_queue(struct driver_data *drv_data) | |
1455 | { | |
1456 | int status; | |
1457 | ||
1458 | status = stop_queue(drv_data); | |
8d94cc50 SS |
1459 | /* we are unloading the module or failing to load (only two calls |
1460 | * to this routine), and neither call can handle a return value. | |
1461 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1462 | * block until all work is done. If the reason that stop_queue | |
1463 | * timed out is that the work will never finish, then it does no | |
1464 | * good to call destroy_workqueue, so return anyway. */ | |
e0c9905e SS |
1465 | if (status != 0) |
1466 | return status; | |
1467 | ||
1468 | destroy_workqueue(drv_data->workqueue); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
d1e44d9c | 1473 | static int __init pxa2xx_spi_probe(struct platform_device *pdev) |
e0c9905e SS |
1474 | { |
1475 | struct device *dev = &pdev->dev; | |
1476 | struct pxa2xx_spi_master *platform_info; | |
1477 | struct spi_master *master; | |
65a00a20 | 1478 | struct driver_data *drv_data; |
2f1a74e5 | 1479 | struct ssp_device *ssp; |
65a00a20 | 1480 | int status; |
e0c9905e SS |
1481 | |
1482 | platform_info = dev->platform_data; | |
1483 | ||
2f1a74e5 | 1484 | ssp = ssp_request(pdev->id, pdev->name); |
1485 | if (ssp == NULL) { | |
1486 | dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id); | |
e0c9905e SS |
1487 | return -ENODEV; |
1488 | } | |
1489 | ||
1490 | /* Allocate master with space for drv_data and null dma buffer */ | |
1491 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1492 | if (!master) { | |
65a00a20 | 1493 | dev_err(&pdev->dev, "cannot alloc spi_master\n"); |
2f1a74e5 | 1494 | ssp_free(ssp); |
e0c9905e SS |
1495 | return -ENOMEM; |
1496 | } | |
1497 | drv_data = spi_master_get_devdata(master); | |
1498 | drv_data->master = master; | |
1499 | drv_data->master_info = platform_info; | |
1500 | drv_data->pdev = pdev; | |
2f1a74e5 | 1501 | drv_data->ssp = ssp; |
e0c9905e SS |
1502 | |
1503 | master->bus_num = pdev->id; | |
1504 | master->num_chipselect = platform_info->num_chipselect; | |
7ad0ba91 | 1505 | master->dma_alignment = DMA_ALIGNMENT; |
e0c9905e SS |
1506 | master->cleanup = cleanup; |
1507 | master->setup = setup; | |
1508 | master->transfer = transfer; | |
1509 | ||
2f1a74e5 | 1510 | drv_data->ssp_type = ssp->type; |
e0c9905e SS |
1511 | drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data + |
1512 | sizeof(struct driver_data)), 8); | |
1513 | ||
2f1a74e5 | 1514 | drv_data->ioaddr = ssp->mmio_base; |
1515 | drv_data->ssdr_physical = ssp->phys_base + SSDR; | |
1516 | if (ssp->type == PXA25x_SSP) { | |
e0c9905e SS |
1517 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; |
1518 | drv_data->dma_cr1 = 0; | |
1519 | drv_data->clear_sr = SSSR_ROR; | |
1520 | drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1521 | } else { | |
1522 | drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; | |
1523 | drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE; | |
1524 | drv_data->clear_sr = SSSR_ROR | SSSR_TINT; | |
1525 | drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; | |
1526 | } | |
1527 | ||
6c7377ab | 1528 | status = request_irq(ssp->irq, ssp_int, 0, dev_name(dev), drv_data); |
e0c9905e | 1529 | if (status < 0) { |
65a00a20 | 1530 | dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); |
e0c9905e SS |
1531 | goto out_error_master_alloc; |
1532 | } | |
1533 | ||
1534 | /* Setup DMA if requested */ | |
1535 | drv_data->tx_channel = -1; | |
1536 | drv_data->rx_channel = -1; | |
1537 | if (platform_info->enable_dma) { | |
1538 | ||
1539 | /* Get two DMA channels (rx and tx) */ | |
1540 | drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx", | |
1541 | DMA_PRIO_HIGH, | |
1542 | dma_handler, | |
1543 | drv_data); | |
1544 | if (drv_data->rx_channel < 0) { | |
1545 | dev_err(dev, "problem (%d) requesting rx channel\n", | |
1546 | drv_data->rx_channel); | |
1547 | status = -ENODEV; | |
1548 | goto out_error_irq_alloc; | |
1549 | } | |
1550 | drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx", | |
1551 | DMA_PRIO_MEDIUM, | |
1552 | dma_handler, | |
1553 | drv_data); | |
1554 | if (drv_data->tx_channel < 0) { | |
1555 | dev_err(dev, "problem (%d) requesting tx channel\n", | |
1556 | drv_data->tx_channel); | |
1557 | status = -ENODEV; | |
1558 | goto out_error_dma_alloc; | |
1559 | } | |
1560 | ||
2f1a74e5 | 1561 | DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel; |
1562 | DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel; | |
e0c9905e SS |
1563 | } |
1564 | ||
1565 | /* Enable SOC clock */ | |
2f1a74e5 | 1566 | clk_enable(ssp->clk); |
e0c9905e SS |
1567 | |
1568 | /* Load default SSP configuration */ | |
1569 | write_SSCR0(0, drv_data->ioaddr); | |
f1f640a9 VS |
1570 | write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) | |
1571 | SSCR1_TxTresh(TX_THRESH_DFLT), | |
1572 | drv_data->ioaddr); | |
e0c9905e SS |
1573 | write_SSCR0(SSCR0_SerClkDiv(2) |
1574 | | SSCR0_Motorola | |
1575 | | SSCR0_DataSize(8), | |
1576 | drv_data->ioaddr); | |
1577 | if (drv_data->ssp_type != PXA25x_SSP) | |
1578 | write_SSTO(0, drv_data->ioaddr); | |
1579 | write_SSPSP(0, drv_data->ioaddr); | |
1580 | ||
1581 | /* Initial and start queue */ | |
1582 | status = init_queue(drv_data); | |
1583 | if (status != 0) { | |
1584 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1585 | goto out_error_clock_enabled; | |
1586 | } | |
1587 | status = start_queue(drv_data); | |
1588 | if (status != 0) { | |
1589 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1590 | goto out_error_clock_enabled; | |
1591 | } | |
1592 | ||
1593 | /* Register with the SPI framework */ | |
1594 | platform_set_drvdata(pdev, drv_data); | |
1595 | status = spi_register_master(master); | |
1596 | if (status != 0) { | |
1597 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1598 | goto out_error_queue_alloc; | |
1599 | } | |
1600 | ||
1601 | return status; | |
1602 | ||
1603 | out_error_queue_alloc: | |
1604 | destroy_queue(drv_data); | |
1605 | ||
1606 | out_error_clock_enabled: | |
2f1a74e5 | 1607 | clk_disable(ssp->clk); |
e0c9905e SS |
1608 | |
1609 | out_error_dma_alloc: | |
1610 | if (drv_data->tx_channel != -1) | |
1611 | pxa_free_dma(drv_data->tx_channel); | |
1612 | if (drv_data->rx_channel != -1) | |
1613 | pxa_free_dma(drv_data->rx_channel); | |
1614 | ||
1615 | out_error_irq_alloc: | |
2f1a74e5 | 1616 | free_irq(ssp->irq, drv_data); |
e0c9905e SS |
1617 | |
1618 | out_error_master_alloc: | |
1619 | spi_master_put(master); | |
2f1a74e5 | 1620 | ssp_free(ssp); |
e0c9905e SS |
1621 | return status; |
1622 | } | |
1623 | ||
1624 | static int pxa2xx_spi_remove(struct platform_device *pdev) | |
1625 | { | |
1626 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
51e911e2 | 1627 | struct ssp_device *ssp; |
e0c9905e SS |
1628 | int status = 0; |
1629 | ||
1630 | if (!drv_data) | |
1631 | return 0; | |
51e911e2 | 1632 | ssp = drv_data->ssp; |
e0c9905e SS |
1633 | |
1634 | /* Remove the queue */ | |
1635 | status = destroy_queue(drv_data); | |
1636 | if (status != 0) | |
8d94cc50 SS |
1637 | /* the kernel does not check the return status of this |
1638 | * this routine (mod->exit, within the kernel). Therefore | |
1639 | * nothing is gained by returning from here, the module is | |
1640 | * going away regardless, and we should not leave any more | |
1641 | * resources allocated than necessary. We cannot free the | |
1642 | * message memory in drv_data->queue, but we can release the | |
1643 | * resources below. I think the kernel should honor -EBUSY | |
1644 | * returns but... */ | |
1645 | dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not " | |
1646 | "complete, message memory not freed\n"); | |
e0c9905e SS |
1647 | |
1648 | /* Disable the SSP at the peripheral and SOC level */ | |
1649 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1650 | clk_disable(ssp->clk); |
e0c9905e SS |
1651 | |
1652 | /* Release DMA */ | |
1653 | if (drv_data->master_info->enable_dma) { | |
2f1a74e5 | 1654 | DRCMR(ssp->drcmr_rx) = 0; |
1655 | DRCMR(ssp->drcmr_tx) = 0; | |
e0c9905e SS |
1656 | pxa_free_dma(drv_data->tx_channel); |
1657 | pxa_free_dma(drv_data->rx_channel); | |
1658 | } | |
1659 | ||
1660 | /* Release IRQ */ | |
2f1a74e5 | 1661 | free_irq(ssp->irq, drv_data); |
1662 | ||
1663 | /* Release SSP */ | |
1664 | ssp_free(ssp); | |
e0c9905e SS |
1665 | |
1666 | /* Disconnect from the SPI framework */ | |
1667 | spi_unregister_master(drv_data->master); | |
1668 | ||
1669 | /* Prevent double remove */ | |
1670 | platform_set_drvdata(pdev, NULL); | |
1671 | ||
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | static void pxa2xx_spi_shutdown(struct platform_device *pdev) | |
1676 | { | |
1677 | int status = 0; | |
1678 | ||
1679 | if ((status = pxa2xx_spi_remove(pdev)) != 0) | |
1680 | dev_err(&pdev->dev, "shutdown failed with %d\n", status); | |
1681 | } | |
1682 | ||
1683 | #ifdef CONFIG_PM | |
e0c9905e SS |
1684 | |
1685 | static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1686 | { | |
1687 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1688 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1689 | int status = 0; |
1690 | ||
e0c9905e SS |
1691 | status = stop_queue(drv_data); |
1692 | if (status != 0) | |
1693 | return status; | |
1694 | write_SSCR0(0, drv_data->ioaddr); | |
2f1a74e5 | 1695 | clk_disable(ssp->clk); |
e0c9905e SS |
1696 | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static int pxa2xx_spi_resume(struct platform_device *pdev) | |
1701 | { | |
1702 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
2f1a74e5 | 1703 | struct ssp_device *ssp = drv_data->ssp; |
e0c9905e SS |
1704 | int status = 0; |
1705 | ||
148da331 DR |
1706 | if (drv_data->rx_channel != -1) |
1707 | DRCMR(drv_data->ssp->drcmr_rx) = | |
1708 | DRCMR_MAPVLD | drv_data->rx_channel; | |
1709 | if (drv_data->tx_channel != -1) | |
1710 | DRCMR(drv_data->ssp->drcmr_tx) = | |
1711 | DRCMR_MAPVLD | drv_data->tx_channel; | |
1712 | ||
e0c9905e | 1713 | /* Enable the SSP clock */ |
0cf942d7 | 1714 | clk_enable(ssp->clk); |
e0c9905e SS |
1715 | |
1716 | /* Start the queue running */ | |
1717 | status = start_queue(drv_data); | |
1718 | if (status != 0) { | |
1719 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1720 | return status; | |
1721 | } | |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | #else | |
1726 | #define pxa2xx_spi_suspend NULL | |
1727 | #define pxa2xx_spi_resume NULL | |
1728 | #endif /* CONFIG_PM */ | |
1729 | ||
1730 | static struct platform_driver driver = { | |
1731 | .driver = { | |
1732 | .name = "pxa2xx-spi", | |
e0c9905e SS |
1733 | .owner = THIS_MODULE, |
1734 | }, | |
d1e44d9c | 1735 | .remove = pxa2xx_spi_remove, |
e0c9905e SS |
1736 | .shutdown = pxa2xx_spi_shutdown, |
1737 | .suspend = pxa2xx_spi_suspend, | |
1738 | .resume = pxa2xx_spi_resume, | |
1739 | }; | |
1740 | ||
1741 | static int __init pxa2xx_spi_init(void) | |
1742 | { | |
d1e44d9c | 1743 | return platform_driver_probe(&driver, pxa2xx_spi_probe); |
e0c9905e SS |
1744 | } |
1745 | module_init(pxa2xx_spi_init); | |
1746 | ||
1747 | static void __exit pxa2xx_spi_exit(void) | |
1748 | { | |
1749 | platform_driver_unregister(&driver); | |
1750 | } | |
1751 | module_exit(pxa2xx_spi_exit); |