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7b11fb51 PA |
1 | /* |
2 | * Defines x86 CPU feature bits | |
3 | */ | |
4 | #ifndef _ASM_X86_CPUFEATURE_H | |
5 | #define _ASM_X86_CPUFEATURE_H | |
6 | ||
7b11fb51 PA |
7 | #include <asm/required-features.h> |
8 | ||
9 | #define NCAPINTS 8 /* N 32-bit words worth of info */ | |
10 | ||
11 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
12 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ | |
13 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ | |
14 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ | |
15 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ | |
16 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ | |
17 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ | |
18 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ | |
19 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ | |
20 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ | |
21 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ | |
22 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ | |
23 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ | |
24 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ | |
25 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ | |
26 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ | |
27 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ | |
28 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ | |
29 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ | |
30 | #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ | |
31 | #define X86_FEATURE_DS (0*32+21) /* Debug Store */ | |
32 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ | |
33 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ | |
34 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ | |
35 | /* of FPU context), and CR4.OSFXSR available */ | |
36 | #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ | |
37 | #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ | |
38 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ | |
39 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ | |
40 | #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ | |
41 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ | |
42 | ||
43 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
44 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
45 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ | |
46 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ | |
47 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ | |
48 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ | |
019c3e7c | 49 | #define X86_FEATURE_GBPAGES (1*32+26) /* GB pages */ |
7b11fb51 PA |
50 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
51 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ | |
52 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ | |
53 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ | |
54 | ||
55 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
56 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ | |
57 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ | |
58 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ | |
59 | ||
60 | /* Other features, Linux-defined mapping, word 3 */ | |
61 | /* This range is used for feature bits which conflict or are synthesized */ | |
62 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ | |
63 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
64 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
65 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
66 | /* cpu types for specific tunings: */ | |
67 | #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */ | |
68 | #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */ | |
69 | #define X86_FEATURE_P3 (3*32+ 6) /* P3 */ | |
70 | #define X86_FEATURE_P4 (3*32+ 7) /* P4 */ | |
71 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ | |
72 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ | |
73 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ | |
74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | |
75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | |
76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | |
77 | /* 14 free */ | |
68071a96 | 78 | /* 15 free */ |
7b11fb51 | 79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |
de421863 | 80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ |
707fa8ed | 81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ |
7b11fb51 PA |
82 | |
83 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
84 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | |
85 | #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ | |
86 | #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ | |
87 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ | |
88 | #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ | |
89 | #define X86_FEATURE_CID (4*32+10) /* Context ID */ | |
90 | #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ | |
91 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ | |
92 | #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ | |
93 | ||
94 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
95 | #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ | |
96 | #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ | |
97 | #define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ | |
98 | #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ | |
99 | #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ | |
100 | #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ | |
101 | #define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */ | |
102 | #define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */ | |
103 | #define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */ | |
104 | #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */ | |
105 | ||
106 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
107 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | |
108 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | |
109 | ||
110 | /* | |
111 | * Auxiliary flags: Linux defined - For features scattered in various | |
112 | * CPUID levels like 0x6, 0xA etc | |
113 | */ | |
114 | #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ | |
115 | ||
fa1408e4 PA |
116 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
117 | ||
118 | #include <linux/bitops.h> | |
119 | ||
120 | extern const char * const x86_cap_flags[NCAPINTS*32]; | |
121 | extern const char * const x86_power_flags[32]; | |
122 | ||
0f8d2b92 IM |
123 | #define test_cpu_cap(c, bit) \ |
124 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
125 | ||
7b11fb51 PA |
126 | #define cpu_has(c, bit) \ |
127 | (__builtin_constant_p(bit) && \ | |
128 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ | |
129 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ | |
130 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ | |
131 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | |
132 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | |
133 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | |
134 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ | |
135 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ | |
136 | ? 1 : \ | |
0f8d2b92 IM |
137 | test_cpu_cap(c, bit)) |
138 | ||
7b11fb51 PA |
139 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
140 | ||
53756d37 JF |
141 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
142 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
7d851c8d AK |
143 | #define setup_clear_cpu_cap(bit) do { \ |
144 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
145 | set_bit(bit, cleared_cpu_caps); \ | |
146 | } while (0) | |
404ee5b1 AK |
147 | #define setup_force_cpu_cap(bit) do { \ |
148 | set_cpu_cap(&boot_cpu_data, bit); \ | |
149 | clear_bit(bit, cleared_cpu_caps); \ | |
150 | } while (0) | |
53756d37 | 151 | |
7b11fb51 PA |
152 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
153 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) | |
154 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) | |
155 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) | |
156 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
157 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) | |
158 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) | |
159 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
160 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) | |
161 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) | |
162 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) | |
163 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) | |
164 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
165 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
166 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) | |
167 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) | |
168 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) | |
169 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) | |
170 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) | |
171 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) | |
172 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) | |
173 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) | |
174 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) | |
175 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) | |
176 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) | |
177 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) | |
178 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) | |
179 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) | |
180 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) | |
181 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) | |
182 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) | |
183 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | |
184 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | |
185 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) | |
186 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) | |
019c3e7c | 187 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
86975101 | 188 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
2e5d9c85 | 189 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
7b11fb51 | 190 | |
0b9c99b6 TG |
191 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) |
192 | # define cpu_has_invlpg 1 | |
193 | #else | |
194 | # define cpu_has_invlpg (boot_cpu_data.x86 > 3) | |
195 | #endif | |
196 | ||
7b11fb51 PA |
197 | #ifdef CONFIG_X86_64 |
198 | ||
199 | #undef cpu_has_vme | |
200 | #define cpu_has_vme 0 | |
201 | ||
202 | #undef cpu_has_pae | |
203 | #define cpu_has_pae ___BUG___ | |
204 | ||
205 | #undef cpu_has_mp | |
206 | #define cpu_has_mp 1 | |
207 | ||
208 | #undef cpu_has_k6_mtrr | |
209 | #define cpu_has_k6_mtrr 0 | |
210 | ||
211 | #undef cpu_has_cyrix_arr | |
212 | #define cpu_has_cyrix_arr 0 | |
213 | ||
214 | #undef cpu_has_centaur_mcr | |
215 | #define cpu_has_centaur_mcr 0 | |
216 | ||
217 | #endif /* CONFIG_X86_64 */ | |
218 | ||
fa1408e4 PA |
219 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
220 | ||
7b11fb51 | 221 | #endif /* _ASM_X86_CPUFEATURE_H */ |