projects / linux-2.6 / blame
| Commit | Line | Data |
|---|---|---|
| 9eb90a0c ZR |
1 | /* |
| 2 | * MPC85xx/86xx PCI Express structure define | |
| 3 | * | |
| 4 | * Copyright 2007 Freescale Semiconductor, Inc | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 9 | * option) any later version. | |
| 10 | * | |
| 11 | */ | |
| 12 | ||
| 13 | #ifdef __KERNEL__ | |
| 14 | #ifndef __POWERPC_FSL_PCIE_H | |
| 15 | #define __POWERPC_FSL_PCIE_H | |
| 16 | ||
| 17 | /* PCIE Express IO block registers in 85xx/86xx */ | |
| 18 | ||
| 19 | struct ccsr_pex { | |
| 20 | __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */ | |
| 21 | __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */ | |
| 22 | u8 __iomem res1[4]; | |
| 23 | __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */ | |
| 24 | __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */ | |
| 25 | u8 __iomem res2[12]; | |
| 26 | __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */ | |
| 27 | __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */ | |
| 28 | __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */ | |
| 29 | __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */ | |
| 30 | u8 __iomem res3[3024]; | |
| 31 | __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */ | |
| 32 | __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/ | |
| 33 | u8 __iomem res4[8]; | |
| 34 | __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/ | |
| 35 | u8 __iomem res5[12]; | |
| 36 | __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */ | |
| 37 | __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/ | |
| 38 | __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/ | |
| 39 | u8 __iomem res6[4]; | |
| 40 | __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/ | |
| 41 | u8 __iomem res7[12]; | |
| 42 | __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */ | |
| 43 | __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/ | |
| 44 | __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/ | |
| 45 | u8 __iomem res8[4]; | |
| 46 | __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/ | |
| 47 | u8 __iomem res9[12]; | |
| 48 | __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */ | |
| 49 | __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/ | |
| 50 | __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/ | |
| 51 | u8 __iomem res10[4]; | |
| 52 | __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/ | |
| 53 | u8 __iomem res11[12]; | |
| 54 | __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */ | |
| 55 | __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/ | |
| 56 | __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/ | |
| 57 | u8 __iomem res12[4]; | |
| 58 | __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/ | |
| 59 | u8 __iomem res13[12]; | |
| 60 | u8 __iomem res14[256]; | |
| 61 | __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */ | |
| 62 | u8 __iomem res15[4]; | |
| 63 | __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */ | |
| 64 | __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */ | |
| 65 | __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */ | |
| 66 | u8 __iomem res16[12]; | |
| 67 | __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */ | |
| 68 | u8 __iomem res17[4]; | |
| 69 | __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */ | |
| 70 | __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */ | |
| 71 | __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */ | |
| 72 | u8 __iomem res18[12]; | |
| 73 | __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */ | |
| 74 | u8 __iomem res19[4]; | |
| 75 | __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */ | |
| 76 | __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */ | |
| 77 | __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */ | |
| 78 | u8 __iomem res20[12]; | |
| 79 | __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */ | |
| 80 | u8 __iomem res21[4]; | |
| 81 | __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */ | |
| 82 | u8 __iomem res22[4]; | |
| 83 | __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */ | |
| 84 | u8 __iomem res23[12]; | |
| 85 | __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */ | |
| 86 | u8 __iomem res24[4]; | |
| 87 | __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */ | |
| 88 | __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */ | |
| 89 | __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */ | |
| 90 | __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */ | |
| 91 | }; | |
| 92 | ||
| 93 | #endif /* __POWERPC_FSL_PCIE_H */ | |
| 94 | #endif /* __KERNEL__ */ |