[linux-2.6] / drivers / mtd / chips / Kconfig

# drivers/mtd/chips/Kconfig

menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targetted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP

config MTD_CFI_NOSWAP
	bool "NO"
	---help---
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

	  If you have a LART, on which the data (and address) lines were
	  connected in a fashion which ensured that the nets were as short
	  as possible, resulting in a bit-shuffling which seems utterly
	  random to the untrained eye, you need the LART_ENDIAN_BYTE option.

	  Yes, there really exists something sicker than PDP-endian :)

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	select HAVE_MTD_OTP
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for Intel/Sharp flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on Intel
	  StrataFlash and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for AMD/Fujitsu/Spansion flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on chips
	  including the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for ST (Advanced Architecture) flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
1da177e4	1	# drivers/mtd/chips/Kconfig
1da177e4 LT	2
	3	menu "RAM/ROM/Flash chip drivers"
	4	depends on MTD!=n
	5
	6	config MTD_CFI
	7	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4	8	select MTD_GEN_PROBE
5e706469	9	select MTD_CFI_UTIL
1da177e4 LT	10	help
	11	The Common Flash Interface specification was developed by Intel,
	12	AMD and other flash manufactures that provides a universal method
	13	for probing the capabilities of flash devices. If you wish to
	14	support any device that is CFI-compliant, you need to enable this
	15	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	16	for more information on CFI.
	17
	18	config MTD_JEDECPROBE
	19	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4 LT	20	select MTD_GEN_PROBE
	21	help
	22	This option enables JEDEC-style probing of flash chips which are not
	23	compatible with the Common Flash Interface, but will use the common
	24	CFI-targetted flash drivers for any chips which are identified which
	25	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	26	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	27	Intel chips.
1da177e4 LT	28
	29	config MTD_GEN_PROBE
	30	tristate
	31
	32	config MTD_CFI_ADV_OPTIONS
	33	bool "Flash chip driver advanced configuration options"
	34	depends on MTD_GEN_PROBE
	35	help
	36	If you need to specify a specific endianness for access to flash
	37	chips, or if you wish to reduce the size of the kernel by including
	38	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	39	option does not directly affect the code, but will enable other
1da177e4 LT	40	configuration options which allow you to do so.
	41
	42	If unsure, say 'N'.
	43
	44	choice
	45	prompt "Flash cmd/query data swapping"
	46	depends on MTD_CFI_ADV_OPTIONS
	47	default MTD_CFI_NOSWAP
	48
	49	config MTD_CFI_NOSWAP
	50	bool "NO"
	51	---help---
	52	This option defines the way in which the CPU attempts to arrange
	53	data bits when writing the 'magic' commands to the chips. Saying
	54	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	55	enabled, means that the CPU will not do any swapping; the chips
1f948b43	56	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	57	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	58	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	59
	60	If you have a LART, on which the data (and address) lines were
	61	connected in a fashion which ensured that the nets were as short
	62	as possible, resulting in a bit-shuffling which seems utterly
	63	random to the untrained eye, you need the LART_ENDIAN_BYTE option.
	64
	65	Yes, there really exists something sicker than PDP-endian :)
	66
	67	config MTD_CFI_BE_BYTE_SWAP
	68	bool "BIG_ENDIAN_BYTE"
	69
	70	config MTD_CFI_LE_BYTE_SWAP
	71	bool "LITTLE_ENDIAN_BYTE"
	72
	73	endchoice
	74
	75	config MTD_CFI_GEOMETRY
	76	bool "Specific CFI Flash geometry selection"
	77	depends on MTD_CFI_ADV_OPTIONS
	78	help
1f948b43	79	This option does not affect the code directly, but will enable
1da177e4	80	some other configuration options which would allow you to reduce
1f948b43 TG	81	the size of the kernel by including support for only certain
1f948b43 TG	82	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	83	which are supported by the current code will be enabled.
	84
	85	config MTD_MAP_BANK_WIDTH_1
	86	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	87	default y
	88	help
	89	If you wish to support CFI devices on a physical bus which is
	90	8 bits wide, say 'Y'.
	91
	92	config MTD_MAP_BANK_WIDTH_2
	93	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	94	default y
	95	help
	96	If you wish to support CFI devices on a physical bus which is
	97	16 bits wide, say 'Y'.
	98
	99	config MTD_MAP_BANK_WIDTH_4
	100	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	101	default y
	102	help
	103	If you wish to support CFI devices on a physical bus which is
	104	32 bits wide, say 'Y'.
	105
	106	config MTD_MAP_BANK_WIDTH_8
	107	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	108	default n
	109	help
	110	If you wish to support CFI devices on a physical bus which is
	111	64 bits wide, say 'Y'.
	112
	113	config MTD_MAP_BANK_WIDTH_16
	114	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	115	default n
	116	help
	117	If you wish to support CFI devices on a physical bus which is
	118	128 bits wide, say 'Y'.
	119
	120	config MTD_MAP_BANK_WIDTH_32
	121	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	122	default n
	123	help
	124	If you wish to support CFI devices on a physical bus which is
	125	256 bits wide, say 'Y'.
	126
	127	config MTD_CFI_I1
	128	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	129	default y
	130	help
	131	If your flash chips are not interleaved - i.e. you only have one
	132	flash chip addressed by each bus cycle, then say 'Y'.
	133
	134	config MTD_CFI_I2
	135	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	136	default y
	137	help
	138	If your flash chips are interleaved in pairs - i.e. you have two
	139	flash chips addressed by each bus cycle, then say 'Y'.
	140
	141	config MTD_CFI_I4
	142	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	143	default n
	144	help
	145	If your flash chips are interleaved in fours - i.e. you have four
	146	flash chips addressed by each bus cycle, then say 'Y'.
147
148	config MTD_CFI_I8
149	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
150	default n
151	help
152	If your flash chips are interleaved in eights - i.e. you have eight
153	flash chips addressed by each bus cycle, then say 'Y'.
154
f77814dd NP	155	config MTD_OTP
	156	bool "Protection Registers aka one-time programmable (OTP) bits"
	157	depends on MTD_CFI_ADV_OPTIONS
34a82443	158	select HAVE_MTD_OTP
f77814dd NP	159	default n
	160	help
	161	This enables support for reading, writing and locking so called
	162	"Protection Registers" present on some flash chips.
	163	A subset of them are pre-programmed at the factory with a
	164	unique set of values. The rest is user-programmable.
	165
	166	The user-programmable Protection Registers contain one-time
	167	programmable (OTP) bits; when programmed, register bits cannot be
	168	erased. Each Protection Register can be accessed multiple times to
	169	program individual bits, as long as the register remains unlocked.
	170
	171	Each Protection Register has an associated Lock Register bit. When a
	172	Lock Register bit is programmed, the associated Protection Register
	173	can only be read; it can no longer be programmed. Additionally,
	174	because the Lock Register bits themselves are OTP, when programmed,
	175	Lock Register bits cannot be erased. Therefore, when a Protection
	176	Register is locked, it cannot be unlocked.
	177
	178	This feature should therefore be used with extreme care. Any mistake
	179	in the programming of OTP bits will waste them.
	180
1da177e4 LT	181	config MTD_CFI_INTELEXT
	182	tristate "Support for Intel/Sharp flash chips"
	183	depends on MTD_GEN_PROBE
	184	select MTD_CFI_UTIL
	185	help
	186	The Common Flash Interface defines a number of different command
	187	sets which a CFI-compliant chip may claim to implement. This code
	188	provides support for one of those command sets, used on Intel
	189	StrataFlash and other parts.
	190
	191	config MTD_CFI_AMDSTD
a0e7229e	192	tristate "Support for AMD/Fujitsu/Spansion flash chips"
1da177e4 LT	193	depends on MTD_GEN_PROBE
	194	select MTD_CFI_UTIL
	195	help
	196	The Common Flash Interface defines a number of different command
	197	sets which a CFI-compliant chip may claim to implement. This code
1f948b43	198	provides support for one of those command sets, used on chips
1da177e4 LT	199	including the AMD Am29LV320.
1da177e4 LT	200
1da177e4 LT	201	config MTD_CFI_STAA
	202	tristate "Support for ST (Advanced Architecture) flash chips"
	203	depends on MTD_GEN_PROBE
	204	select MTD_CFI_UTIL
	205	help
	206	The Common Flash Interface defines a number of different command
	207	sets which a CFI-compliant chip may claim to implement. This code
	208	provides support for one of those command sets.
	209
	210	config MTD_CFI_UTIL
	211	tristate
	212
	213	config MTD_RAM
	214	tristate "Support for RAM chips in bus mapping"
1da177e4	215	help
1f948b43	216	This option enables basic support for RAM chips accessed through
1da177e4 LT	217	a bus mapping driver.
	218
	219	config MTD_ROM
	220	tristate "Support for ROM chips in bus mapping"
1da177e4	221	help
1f948b43	222	This option enables basic support for ROM chips accessed through
1da177e4 LT	223	a bus mapping driver.
	224
	225	config MTD_ABSENT
	226	tristate "Support for absent chips in bus mapping"
1da177e4 LT	227	help
	228	This option enables support for a dummy probing driver used to
	229	allocated placeholder MTD devices on systems that have socketed
	230	or removable media. Use of this driver as a fallback chip probe
	231	preserves the expected registration order of MTD device nodes on
	232	the system regardless of media presence. Device nodes created
	233	with this driver will return -ENODEV upon access.
	234
1da177e4 LT	235	config MTD_XIP
1da177e4 LT	236	bool "XIP aware MTD support"
034d2f5a	237	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
1da177e4 LT	238	default y if XIP_KERNEL
	239	help
	240	This allows MTD support to work with flash memory which is also
	241	used for XIP purposes. If you're not sure what this is all about
	242	then say N.
	243
	244	endmenu
	245