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d61e0bf3 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #ifndef __HW_H__ | |
23 | #define __HW_H__ | |
24 | ||
25 | #include "global.h" | |
26 | ||
27 | /*************************************************** | |
28 | * Definition IGA1 Design Method of CRTC Registers * | |
29 | ****************************************************/ | |
30 | #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5) | |
31 | #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1) | |
32 | #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1) | |
33 | #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1) | |
34 | #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8) | |
35 | #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8) | |
36 | ||
37 | #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2) | |
38 | #define IGA1_VER_ADDR_FORMULA(x) ((x)-1) | |
39 | #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1) | |
40 | #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
41 | #define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1) | |
42 | #define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
43 | ||
44 | /*************************************************** | |
45 | ** Definition IGA2 Design Method of CRTC Registers * | |
46 | ****************************************************/ | |
47 | #define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1) | |
48 | #define IGA2_HOR_ADDR_FORMULA(x) ((x)-1) | |
49 | #define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1) | |
50 | #define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
51 | #define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1) | |
52 | #define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
53 | ||
54 | #define IGA2_VER_TOTAL_FORMULA(x) ((x)-1) | |
55 | #define IGA2_VER_ADDR_FORMULA(x) ((x)-1) | |
56 | #define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1) | |
57 | #define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1) | |
58 | #define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1) | |
59 | #define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1) | |
60 | ||
61 | /**********************************************************/ | |
62 | /* Definition IGA2 Design Method of CRTC Shadow Registers */ | |
63 | /**********************************************************/ | |
64 | #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5) | |
65 | #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1) | |
66 | #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2) | |
67 | #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1) | |
68 | #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1) | |
69 | #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1) | |
70 | #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x) | |
71 | #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y) | |
72 | ||
73 | /* Define Register Number for IGA1 CRTC Timing */ | |
74 | ||
75 | /* location: {CR00,0,7},{CR36,3,3} */ | |
76 | #define IGA1_HOR_TOTAL_REG_NUM 2 | |
77 | /* location: {CR01,0,7} */ | |
78 | #define IGA1_HOR_ADDR_REG_NUM 1 | |
79 | /* location: {CR02,0,7} */ | |
80 | #define IGA1_HOR_BLANK_START_REG_NUM 1 | |
81 | /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */ | |
82 | #define IGA1_HOR_BLANK_END_REG_NUM 3 | |
83 | /* location: {CR04,0,7},{CR33,4,4} */ | |
84 | #define IGA1_HOR_SYNC_START_REG_NUM 2 | |
85 | /* location: {CR05,0,4} */ | |
86 | #define IGA1_HOR_SYNC_END_REG_NUM 1 | |
87 | /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */ | |
88 | #define IGA1_VER_TOTAL_REG_NUM 4 | |
89 | /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */ | |
90 | #define IGA1_VER_ADDR_REG_NUM 4 | |
91 | /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */ | |
92 | #define IGA1_VER_BLANK_START_REG_NUM 4 | |
93 | /* location: {CR16,0,7} */ | |
94 | #define IGA1_VER_BLANK_END_REG_NUM 1 | |
95 | /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */ | |
96 | #define IGA1_VER_SYNC_START_REG_NUM 4 | |
97 | /* location: {CR11,0,3} */ | |
98 | #define IGA1_VER_SYNC_END_REG_NUM 1 | |
99 | ||
100 | /* Define Register Number for IGA2 Shadow CRTC Timing */ | |
101 | ||
102 | /* location: {CR6D,0,7},{CR71,3,3} */ | |
103 | #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2 | |
104 | /* location: {CR6E,0,7} */ | |
105 | #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1 | |
106 | /* location: {CR6F,0,7},{CR71,0,2} */ | |
107 | #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2 | |
108 | /* location: {CR70,0,7},{CR71,4,6} */ | |
109 | #define IGA2_SHADOW_VER_ADDR_REG_NUM 2 | |
110 | /* location: {CR72,0,7},{CR74,4,6} */ | |
111 | #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2 | |
112 | /* location: {CR73,0,7},{CR74,0,2} */ | |
113 | #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2 | |
114 | /* location: {CR75,0,7},{CR76,4,6} */ | |
115 | #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2 | |
116 | /* location: {CR76,0,3} */ | |
117 | #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1 | |
118 | ||
119 | /* Define Register Number for IGA2 CRTC Timing */ | |
120 | ||
121 | /* location: {CR50,0,7},{CR55,0,3} */ | |
122 | #define IGA2_HOR_TOTAL_REG_NUM 2 | |
123 | /* location: {CR51,0,7},{CR55,4,6} */ | |
124 | #define IGA2_HOR_ADDR_REG_NUM 2 | |
125 | /* location: {CR52,0,7},{CR54,0,2} */ | |
126 | #define IGA2_HOR_BLANK_START_REG_NUM 2 | |
127 | /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6] | |
128 | is reserved, so it may have problem to set 1600x1200 on IGA2. */ | |
129 | /* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */ | |
130 | #define IGA2_HOR_BLANK_END_REG_NUM 3 | |
131 | /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */ | |
132 | /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */ | |
133 | #define IGA2_HOR_SYNC_START_REG_NUM 4 | |
134 | ||
135 | /* location: {CR57,0,7},{CR5C,6,6} */ | |
136 | #define IGA2_HOR_SYNC_END_REG_NUM 2 | |
137 | /* location: {CR58,0,7},{CR5D,0,2} */ | |
138 | #define IGA2_VER_TOTAL_REG_NUM 2 | |
139 | /* location: {CR59,0,7},{CR5D,3,5} */ | |
140 | #define IGA2_VER_ADDR_REG_NUM 2 | |
141 | /* location: {CR5A,0,7},{CR5C,0,2} */ | |
142 | #define IGA2_VER_BLANK_START_REG_NUM 2 | |
143 | /* location: {CR5E,0,7},{CR5C,3,5} */ | |
144 | #define IGA2_VER_BLANK_END_REG_NUM 2 | |
145 | /* location: {CR5E,0,7},{CR5F,5,7} */ | |
146 | #define IGA2_VER_SYNC_START_REG_NUM 2 | |
147 | /* location: {CR5F,0,4} */ | |
148 | #define IGA2_VER_SYNC_END_REG_NUM 1 | |
149 | ||
150 | /* Define Offset and Fetch Count Register*/ | |
151 | ||
152 | /* location: {CR13,0,7},{CR35,5,7} */ | |
153 | #define IGA1_OFFSET_REG_NUM 2 | |
154 | /* 8 bytes alignment. */ | |
155 | #define IGA1_OFFSER_ALIGN_BYTE 8 | |
156 | /* x: H resolution, y: color depth */ | |
157 | #define IGA1_OFFSET_FORMULA(x, y) ((x*y)/IGA1_OFFSER_ALIGN_BYTE) | |
158 | /* location: {SR1C,0,7},{SR1D,0,1} */ | |
159 | #define IGA1_FETCH_COUNT_REG_NUM 2 | |
160 | /* 16 bytes alignment. */ | |
161 | #define IGA1_FETCH_COUNT_ALIGN_BYTE 16 | |
162 | /* x: H resolution, y: color depth */ | |
163 | #define IGA1_FETCH_COUNT_PATCH_VALUE 4 | |
164 | #define IGA1_FETCH_COUNT_FORMULA(x, y) \ | |
165 | (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE) | |
166 | ||
167 | /* location: {CR66,0,7},{CR67,0,1} */ | |
168 | #define IGA2_OFFSET_REG_NUM 2 | |
169 | #define IGA2_OFFSET_ALIGN_BYTE 8 | |
170 | /* x: H resolution, y: color depth */ | |
171 | #define IGA2_OFFSET_FORMULA(x, y) ((x*y)/IGA2_OFFSET_ALIGN_BYTE) | |
172 | /* location: {CR65,0,7},{CR67,2,3} */ | |
173 | #define IGA2_FETCH_COUNT_REG_NUM 2 | |
174 | #define IGA2_FETCH_COUNT_ALIGN_BYTE 16 | |
175 | #define IGA2_FETCH_COUNT_PATCH_VALUE 0 | |
176 | #define IGA2_FETCH_COUNT_FORMULA(x, y) \ | |
177 | (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE) | |
178 | ||
179 | /* Staring Address*/ | |
180 | ||
181 | /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */ | |
182 | #define IGA1_STARTING_ADDR_REG_NUM 4 | |
183 | /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */ | |
184 | #define IGA2_STARTING_ADDR_REG_NUM 3 | |
185 | ||
186 | /* Define Display OFFSET*/ | |
187 | /* These value are by HW suggested value*/ | |
188 | /* location: {SR17,0,7} */ | |
189 | #define K800_IGA1_FIFO_MAX_DEPTH 384 | |
190 | /* location: {SR16,0,5},{SR16,7,7} */ | |
191 | #define K800_IGA1_FIFO_THRESHOLD 328 | |
192 | /* location: {SR18,0,5},{SR18,7,7} */ | |
193 | #define K800_IGA1_FIFO_HIGH_THRESHOLD 296 | |
194 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
195 | /* because HW only 5 bits */ | |
196 | #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
197 | ||
198 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
199 | #define K800_IGA2_FIFO_MAX_DEPTH 384 | |
200 | /* location: {CR68,0,3},{CR95,4,6} */ | |
201 | #define K800_IGA2_FIFO_THRESHOLD 328 | |
202 | /* location: {CR92,0,3},{CR95,0,2} */ | |
203 | #define K800_IGA2_FIFO_HIGH_THRESHOLD 296 | |
204 | /* location: {CR94,0,6} */ | |
205 | #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
206 | ||
207 | /* location: {SR17,0,7} */ | |
208 | #define P880_IGA1_FIFO_MAX_DEPTH 192 | |
209 | /* location: {SR16,0,5},{SR16,7,7} */ | |
210 | #define P880_IGA1_FIFO_THRESHOLD 128 | |
211 | /* location: {SR18,0,5},{SR18,7,7} */ | |
212 | #define P880_IGA1_FIFO_HIGH_THRESHOLD 64 | |
213 | /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */ | |
214 | /* because HW only 5 bits */ | |
215 | #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
216 | ||
217 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
218 | #define P880_IGA2_FIFO_MAX_DEPTH 96 | |
219 | /* location: {CR68,0,3},{CR95,4,6} */ | |
220 | #define P880_IGA2_FIFO_THRESHOLD 64 | |
221 | /* location: {CR92,0,3},{CR95,0,2} */ | |
222 | #define P880_IGA2_FIFO_HIGH_THRESHOLD 32 | |
223 | /* location: {CR94,0,6} */ | |
224 | #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
225 | ||
226 | /* VT3314 chipset*/ | |
227 | ||
228 | /* location: {SR17,0,7} */ | |
229 | #define CN700_IGA1_FIFO_MAX_DEPTH 96 | |
230 | /* location: {SR16,0,5},{SR16,7,7} */ | |
231 | #define CN700_IGA1_FIFO_THRESHOLD 80 | |
232 | /* location: {SR18,0,5},{SR18,7,7} */ | |
233 | #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64 | |
234 | /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero, | |
235 | because HW only 5 bits */ | |
236 | #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 | |
237 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
238 | #define CN700_IGA2_FIFO_MAX_DEPTH 96 | |
239 | /* location: {CR68,0,3},{CR95,4,6} */ | |
240 | #define CN700_IGA2_FIFO_THRESHOLD 80 | |
241 | /* location: {CR92,0,3},{CR95,0,2} */ | |
242 | #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
243 | /* location: {CR94,0,6} */ | |
244 | #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
245 | ||
246 | /* For VT3324, these values are suggested by HW */ | |
247 | /* location: {SR17,0,7} */ | |
248 | #define CX700_IGA1_FIFO_MAX_DEPTH 192 | |
249 | /* location: {SR16,0,5},{SR16,7,7} */ | |
250 | #define CX700_IGA1_FIFO_THRESHOLD 128 | |
251 | /* location: {SR18,0,5},{SR18,7,7} */ | |
252 | #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 | |
253 | /* location: {SR22,0,4} */ | |
254 | #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
255 | ||
256 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
257 | #define CX700_IGA2_FIFO_MAX_DEPTH 96 | |
258 | /* location: {CR68,0,3},{CR95,4,6} */ | |
259 | #define CX700_IGA2_FIFO_THRESHOLD 64 | |
260 | /* location: {CR92,0,3},{CR95,0,2} */ | |
261 | #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 | |
262 | /* location: {CR94,0,6} */ | |
263 | #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
264 | ||
265 | /* VT3336 chipset*/ | |
266 | /* location: {SR17,0,7} */ | |
267 | #define K8M890_IGA1_FIFO_MAX_DEPTH 360 | |
268 | /* location: {SR16,0,5},{SR16,7,7} */ | |
269 | #define K8M890_IGA1_FIFO_THRESHOLD 328 | |
270 | /* location: {SR18,0,5},{SR18,7,7} */ | |
271 | #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296 | |
272 | /* location: {SR22,0,4}. */ | |
273 | #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
274 | ||
275 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
276 | #define K8M890_IGA2_FIFO_MAX_DEPTH 360 | |
277 | /* location: {CR68,0,3},{CR95,4,6} */ | |
278 | #define K8M890_IGA2_FIFO_THRESHOLD 328 | |
279 | /* location: {CR92,0,3},{CR95,0,2} */ | |
280 | #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296 | |
281 | /* location: {CR94,0,6} */ | |
282 | #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124 | |
283 | ||
284 | /* VT3327 chipset*/ | |
285 | /* location: {SR17,0,7} */ | |
286 | #define P4M890_IGA1_FIFO_MAX_DEPTH 96 | |
287 | /* location: {SR16,0,5},{SR16,7,7} */ | |
288 | #define P4M890_IGA1_FIFO_THRESHOLD 76 | |
289 | /* location: {SR18,0,5},{SR18,7,7} */ | |
290 | #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64 | |
291 | /* location: {SR22,0,4}. (32/4) =8 */ | |
292 | #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
293 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
294 | #define P4M890_IGA2_FIFO_MAX_DEPTH 96 | |
295 | /* location: {CR68,0,3},{CR95,4,6} */ | |
296 | #define P4M890_IGA2_FIFO_THRESHOLD 76 | |
297 | /* location: {CR92,0,3},{CR95,0,2} */ | |
298 | #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64 | |
299 | /* location: {CR94,0,6} */ | |
300 | #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
301 | ||
302 | /* VT3364 chipset*/ | |
303 | /* location: {SR17,0,7} */ | |
304 | #define P4M900_IGA1_FIFO_MAX_DEPTH 96 | |
305 | /* location: {SR16,0,5},{SR16,7,7} */ | |
306 | #define P4M900_IGA1_FIFO_THRESHOLD 76 | |
307 | /* location: {SR18,0,5},{SR18,7,7} */ | |
308 | #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76 | |
309 | /* location: {SR22,0,4}. */ | |
310 | #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
311 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
312 | #define P4M900_IGA2_FIFO_MAX_DEPTH 96 | |
313 | /* location: {CR68,0,3},{CR95,4,6} */ | |
314 | #define P4M900_IGA2_FIFO_THRESHOLD 76 | |
315 | /* location: {CR92,0,3},{CR95,0,2} */ | |
316 | #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76 | |
317 | /* location: {CR94,0,6} */ | |
318 | #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 | |
319 | ||
320 | /* For VT3353, these values are suggested by HW */ | |
321 | /* location: {SR17,0,7} */ | |
322 | #define VX800_IGA1_FIFO_MAX_DEPTH 192 | |
323 | /* location: {SR16,0,5},{SR16,7,7} */ | |
324 | #define VX800_IGA1_FIFO_THRESHOLD 152 | |
325 | /* location: {SR18,0,5},{SR18,7,7} */ | |
326 | #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152 | |
327 | /* location: {SR22,0,4} */ | |
328 | #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64 | |
329 | /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */ | |
330 | #define VX800_IGA2_FIFO_MAX_DEPTH 96 | |
331 | /* location: {CR68,0,3},{CR95,4,6} */ | |
332 | #define VX800_IGA2_FIFO_THRESHOLD 64 | |
333 | /* location: {CR92,0,3},{CR95,0,2} */ | |
334 | #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32 | |
335 | /* location: {CR94,0,6} */ | |
336 | #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 | |
337 | ||
338 | #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1 | |
339 | #define IGA1_FIFO_THRESHOLD_REG_NUM 2 | |
340 | #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
341 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
342 | ||
343 | #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3 | |
344 | #define IGA2_FIFO_THRESHOLD_REG_NUM 2 | |
345 | #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2 | |
346 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1 | |
347 | ||
348 | #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1) | |
349 | #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
350 | #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
351 | #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
352 | #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1) | |
353 | #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4) | |
354 | #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4) | |
355 | #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4) | |
356 | ||
357 | /************************************************************************/ | |
358 | /* LCD Timing */ | |
359 | /************************************************************************/ | |
360 | ||
361 | /* 500 ms = 500000 us */ | |
362 | #define LCD_POWER_SEQ_TD0 500000 | |
363 | /* 50 ms = 50000 us */ | |
364 | #define LCD_POWER_SEQ_TD1 50000 | |
365 | /* 0 us */ | |
366 | #define LCD_POWER_SEQ_TD2 0 | |
367 | /* 210 ms = 210000 us */ | |
368 | #define LCD_POWER_SEQ_TD3 210000 | |
369 | /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */ | |
370 | #define CLE266_POWER_SEQ_UNIT 71 | |
371 | /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */ | |
372 | #define K800_POWER_SEQ_UNIT 142 | |
373 | /* 2^13 * (1/14.31818M) = 572.1 us */ | |
374 | #define P880_POWER_SEQ_UNIT 572 | |
375 | ||
376 | #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT) | |
377 | #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT) | |
378 | #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT) | |
379 | ||
380 | /* location: {CR8B,0,7},{CR8F,0,3} */ | |
381 | #define LCD_POWER_SEQ_TD0_REG_NUM 2 | |
382 | /* location: {CR8C,0,7},{CR8F,4,7} */ | |
383 | #define LCD_POWER_SEQ_TD1_REG_NUM 2 | |
384 | /* location: {CR8D,0,7},{CR90,0,3} */ | |
385 | #define LCD_POWER_SEQ_TD2_REG_NUM 2 | |
386 | /* location: {CR8E,0,7},{CR90,4,7} */ | |
387 | #define LCD_POWER_SEQ_TD3_REG_NUM 2 | |
388 | ||
389 | /* LCD Scaling factor*/ | |
390 | /* x: indicate setting horizontal size*/ | |
391 | /* y: indicate panel horizontal size*/ | |
392 | ||
393 | /* Horizontal scaling factor 10 bits (2^10) */ | |
394 | #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
395 | /* Vertical scaling factor 10 bits (2^10) */ | |
396 | #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1)) | |
397 | /* Horizontal scaling factor 10 bits (2^12) */ | |
398 | #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1)) | |
399 | /* Vertical scaling factor 10 bits (2^11) */ | |
400 | #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1)) | |
401 | ||
402 | /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */ | |
403 | #define LCD_HOR_SCALING_FACTOR_REG_NUM 3 | |
404 | /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */ | |
405 | #define LCD_VER_SCALING_FACTOR_REG_NUM 3 | |
406 | /* location: {CR77,0,7},{CR79,4,5} */ | |
407 | #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2 | |
408 | /* location: {CR78,0,7},{CR79,6,7} */ | |
409 | #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2 | |
410 | ||
411 | /************************************************ | |
412 | ***** Define IGA1 Display Timing ***** | |
413 | ************************************************/ | |
414 | struct io_register { | |
415 | u8 io_addr; | |
416 | u8 start_bit; | |
417 | u8 end_bit; | |
418 | }; | |
419 | ||
420 | /* IGA1 Horizontal Total */ | |
421 | struct iga1_hor_total { | |
422 | int reg_num; | |
423 | struct io_register reg[IGA1_HOR_TOTAL_REG_NUM]; | |
424 | }; | |
425 | ||
426 | /* IGA1 Horizontal Addressable Video */ | |
427 | struct iga1_hor_addr { | |
428 | int reg_num; | |
429 | struct io_register reg[IGA1_HOR_ADDR_REG_NUM]; | |
430 | }; | |
431 | ||
432 | /* IGA1 Horizontal Blank Start */ | |
433 | struct iga1_hor_blank_start { | |
434 | int reg_num; | |
435 | struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM]; | |
436 | }; | |
437 | ||
438 | /* IGA1 Horizontal Blank End */ | |
439 | struct iga1_hor_blank_end { | |
440 | int reg_num; | |
441 | struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM]; | |
442 | }; | |
443 | ||
444 | /* IGA1 Horizontal Sync Start */ | |
445 | struct iga1_hor_sync_start { | |
446 | int reg_num; | |
447 | struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM]; | |
448 | }; | |
449 | ||
450 | /* IGA1 Horizontal Sync End */ | |
451 | struct iga1_hor_sync_end { | |
452 | int reg_num; | |
453 | struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM]; | |
454 | }; | |
455 | ||
456 | /* IGA1 Vertical Total */ | |
457 | struct iga1_ver_total { | |
458 | int reg_num; | |
459 | struct io_register reg[IGA1_VER_TOTAL_REG_NUM]; | |
460 | }; | |
461 | ||
462 | /* IGA1 Vertical Addressable Video */ | |
463 | struct iga1_ver_addr { | |
464 | int reg_num; | |
465 | struct io_register reg[IGA1_VER_ADDR_REG_NUM]; | |
466 | }; | |
467 | ||
468 | /* IGA1 Vertical Blank Start */ | |
469 | struct iga1_ver_blank_start { | |
470 | int reg_num; | |
471 | struct io_register reg[IGA1_VER_BLANK_START_REG_NUM]; | |
472 | }; | |
473 | ||
474 | /* IGA1 Vertical Blank End */ | |
475 | struct iga1_ver_blank_end { | |
476 | int reg_num; | |
477 | struct io_register reg[IGA1_VER_BLANK_END_REG_NUM]; | |
478 | }; | |
479 | ||
480 | /* IGA1 Vertical Sync Start */ | |
481 | struct iga1_ver_sync_start { | |
482 | int reg_num; | |
483 | struct io_register reg[IGA1_VER_SYNC_START_REG_NUM]; | |
484 | }; | |
485 | ||
486 | /* IGA1 Vertical Sync End */ | |
487 | struct iga1_ver_sync_end { | |
488 | int reg_num; | |
489 | struct io_register reg[IGA1_VER_SYNC_END_REG_NUM]; | |
490 | }; | |
491 | ||
492 | /***************************************************** | |
493 | ** Define IGA2 Shadow Display Timing **** | |
494 | *****************************************************/ | |
495 | ||
496 | /* IGA2 Shadow Horizontal Total */ | |
497 | struct iga2_shadow_hor_total { | |
498 | int reg_num; | |
499 | struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; | |
500 | }; | |
501 | ||
502 | /* IGA2 Shadow Horizontal Blank End */ | |
503 | struct iga2_shadow_hor_blank_end { | |
504 | int reg_num; | |
505 | struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM]; | |
506 | }; | |
507 | ||
508 | /* IGA2 Shadow Vertical Total */ | |
509 | struct iga2_shadow_ver_total { | |
510 | int reg_num; | |
511 | struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM]; | |
512 | }; | |
513 | ||
514 | /* IGA2 Shadow Vertical Addressable Video */ | |
515 | struct iga2_shadow_ver_addr { | |
516 | int reg_num; | |
517 | struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM]; | |
518 | }; | |
519 | ||
520 | /* IGA2 Shadow Vertical Blank Start */ | |
521 | struct iga2_shadow_ver_blank_start { | |
522 | int reg_num; | |
523 | struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM]; | |
524 | }; | |
525 | ||
526 | /* IGA2 Shadow Vertical Blank End */ | |
527 | struct iga2_shadow_ver_blank_end { | |
528 | int reg_num; | |
529 | struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM]; | |
530 | }; | |
531 | ||
532 | /* IGA2 Shadow Vertical Sync Start */ | |
533 | struct iga2_shadow_ver_sync_start { | |
534 | int reg_num; | |
535 | struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM]; | |
536 | }; | |
537 | ||
538 | /* IGA2 Shadow Vertical Sync End */ | |
539 | struct iga2_shadow_ver_sync_end { | |
540 | int reg_num; | |
541 | struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; | |
542 | }; | |
543 | ||
544 | /***************************************************** | |
545 | ** Define IGA2 Display Timing **** | |
546 | ******************************************************/ | |
547 | ||
548 | /* IGA2 Horizontal Total */ | |
549 | struct iga2_hor_total { | |
550 | int reg_num; | |
551 | struct io_register reg[IGA2_HOR_TOTAL_REG_NUM]; | |
552 | }; | |
553 | ||
554 | /* IGA2 Horizontal Addressable Video */ | |
555 | struct iga2_hor_addr { | |
556 | int reg_num; | |
557 | struct io_register reg[IGA2_HOR_ADDR_REG_NUM]; | |
558 | }; | |
559 | ||
560 | /* IGA2 Horizontal Blank Start */ | |
561 | struct iga2_hor_blank_start { | |
562 | int reg_num; | |
563 | struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM]; | |
564 | }; | |
565 | ||
566 | /* IGA2 Horizontal Blank End */ | |
567 | struct iga2_hor_blank_end { | |
568 | int reg_num; | |
569 | struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM]; | |
570 | }; | |
571 | ||
572 | /* IGA2 Horizontal Sync Start */ | |
573 | struct iga2_hor_sync_start { | |
574 | int reg_num; | |
575 | struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM]; | |
576 | }; | |
577 | ||
578 | /* IGA2 Horizontal Sync End */ | |
579 | struct iga2_hor_sync_end { | |
580 | int reg_num; | |
581 | struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM]; | |
582 | }; | |
583 | ||
584 | /* IGA2 Vertical Total */ | |
585 | struct iga2_ver_total { | |
586 | int reg_num; | |
587 | struct io_register reg[IGA2_VER_TOTAL_REG_NUM]; | |
588 | }; | |
589 | ||
590 | /* IGA2 Vertical Addressable Video */ | |
591 | struct iga2_ver_addr { | |
592 | int reg_num; | |
593 | struct io_register reg[IGA2_VER_ADDR_REG_NUM]; | |
594 | }; | |
595 | ||
596 | /* IGA2 Vertical Blank Start */ | |
597 | struct iga2_ver_blank_start { | |
598 | int reg_num; | |
599 | struct io_register reg[IGA2_VER_BLANK_START_REG_NUM]; | |
600 | }; | |
601 | ||
602 | /* IGA2 Vertical Blank End */ | |
603 | struct iga2_ver_blank_end { | |
604 | int reg_num; | |
605 | struct io_register reg[IGA2_VER_BLANK_END_REG_NUM]; | |
606 | }; | |
607 | ||
608 | /* IGA2 Vertical Sync Start */ | |
609 | struct iga2_ver_sync_start { | |
610 | int reg_num; | |
611 | struct io_register reg[IGA2_VER_SYNC_START_REG_NUM]; | |
612 | }; | |
613 | ||
614 | /* IGA2 Vertical Sync End */ | |
615 | struct iga2_ver_sync_end { | |
616 | int reg_num; | |
617 | struct io_register reg[IGA2_VER_SYNC_END_REG_NUM]; | |
618 | }; | |
619 | ||
620 | /* IGA1 Offset Register */ | |
621 | struct iga1_offset { | |
622 | int reg_num; | |
623 | struct io_register reg[IGA1_OFFSET_REG_NUM]; | |
624 | }; | |
625 | ||
626 | /* IGA2 Offset Register */ | |
627 | struct iga2_offset { | |
628 | int reg_num; | |
629 | struct io_register reg[IGA2_OFFSET_REG_NUM]; | |
630 | }; | |
631 | ||
632 | struct offset { | |
633 | struct iga1_offset iga1_offset_reg; | |
634 | struct iga2_offset iga2_offset_reg; | |
635 | }; | |
636 | ||
637 | /* IGA1 Fetch Count Register */ | |
638 | struct iga1_fetch_count { | |
639 | int reg_num; | |
640 | struct io_register reg[IGA1_FETCH_COUNT_REG_NUM]; | |
641 | }; | |
642 | ||
643 | /* IGA2 Fetch Count Register */ | |
644 | struct iga2_fetch_count { | |
645 | int reg_num; | |
646 | struct io_register reg[IGA2_FETCH_COUNT_REG_NUM]; | |
647 | }; | |
648 | ||
649 | struct fetch_count { | |
650 | struct iga1_fetch_count iga1_fetch_count_reg; | |
651 | struct iga2_fetch_count iga2_fetch_count_reg; | |
652 | }; | |
653 | ||
654 | /* Starting Address Register */ | |
655 | struct iga1_starting_addr { | |
656 | int reg_num; | |
657 | struct io_register reg[IGA1_STARTING_ADDR_REG_NUM]; | |
658 | }; | |
659 | ||
660 | struct iga2_starting_addr { | |
661 | int reg_num; | |
662 | struct io_register reg[IGA2_STARTING_ADDR_REG_NUM]; | |
663 | }; | |
664 | ||
665 | struct starting_addr { | |
666 | struct iga1_starting_addr iga1_starting_addr_reg; | |
667 | struct iga2_starting_addr iga2_starting_addr_reg; | |
668 | }; | |
669 | ||
670 | /* LCD Power Sequence Timer */ | |
671 | struct lcd_pwd_seq_td0 { | |
672 | int reg_num; | |
673 | struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM]; | |
674 | }; | |
675 | ||
676 | struct lcd_pwd_seq_td1 { | |
677 | int reg_num; | |
678 | struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM]; | |
679 | }; | |
680 | ||
681 | struct lcd_pwd_seq_td2 { | |
682 | int reg_num; | |
683 | struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM]; | |
684 | }; | |
685 | ||
686 | struct lcd_pwd_seq_td3 { | |
687 | int reg_num; | |
688 | struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM]; | |
689 | }; | |
690 | ||
691 | struct _lcd_pwd_seq_timer { | |
692 | struct lcd_pwd_seq_td0 td0; | |
693 | struct lcd_pwd_seq_td1 td1; | |
694 | struct lcd_pwd_seq_td2 td2; | |
695 | struct lcd_pwd_seq_td3 td3; | |
696 | }; | |
697 | ||
698 | /* LCD Scaling Factor */ | |
699 | struct _lcd_hor_scaling_factor { | |
700 | int reg_num; | |
701 | struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM]; | |
702 | }; | |
703 | ||
704 | struct _lcd_ver_scaling_factor { | |
705 | int reg_num; | |
706 | struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM]; | |
707 | }; | |
708 | ||
709 | struct _lcd_scaling_factor { | |
710 | struct _lcd_hor_scaling_factor lcd_hor_scaling_factor; | |
711 | struct _lcd_ver_scaling_factor lcd_ver_scaling_factor; | |
712 | }; | |
713 | ||
714 | struct pll_map { | |
715 | u32 clk; | |
716 | u32 cle266_pll; | |
717 | u32 k800_pll; | |
718 | u32 cx700_pll; | |
719 | }; | |
720 | ||
721 | struct rgbLUT { | |
722 | u8 red; | |
723 | u8 green; | |
724 | u8 blue; | |
725 | }; | |
726 | ||
727 | struct lcd_pwd_seq_timer { | |
728 | u16 td0; | |
729 | u16 td1; | |
730 | u16 td2; | |
731 | u16 td3; | |
732 | }; | |
733 | ||
734 | /* Display FIFO Relation Registers*/ | |
735 | struct iga1_fifo_depth_select { | |
736 | int reg_num; | |
737 | struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM]; | |
738 | }; | |
739 | ||
740 | struct iga1_fifo_threshold_select { | |
741 | int reg_num; | |
742 | struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM]; | |
743 | }; | |
744 | ||
745 | struct iga1_fifo_high_threshold_select { | |
746 | int reg_num; | |
747 | struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
748 | }; | |
749 | ||
750 | struct iga1_display_queue_expire_num { | |
751 | int reg_num; | |
752 | struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
753 | }; | |
754 | ||
755 | struct iga2_fifo_depth_select { | |
756 | int reg_num; | |
757 | struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM]; | |
758 | }; | |
759 | ||
760 | struct iga2_fifo_threshold_select { | |
761 | int reg_num; | |
762 | struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM]; | |
763 | }; | |
764 | ||
765 | struct iga2_fifo_high_threshold_select { | |
766 | int reg_num; | |
767 | struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM]; | |
768 | }; | |
769 | ||
770 | struct iga2_display_queue_expire_num { | |
771 | int reg_num; | |
772 | struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; | |
773 | }; | |
774 | ||
775 | struct fifo_depth_select { | |
776 | struct iga1_fifo_depth_select iga1_fifo_depth_select_reg; | |
777 | struct iga2_fifo_depth_select iga2_fifo_depth_select_reg; | |
778 | }; | |
779 | ||
780 | struct fifo_threshold_select { | |
781 | struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg; | |
782 | struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg; | |
783 | }; | |
784 | ||
785 | struct fifo_high_threshold_select { | |
786 | struct iga1_fifo_high_threshold_select | |
787 | iga1_fifo_high_threshold_select_reg; | |
788 | struct iga2_fifo_high_threshold_select | |
789 | iga2_fifo_high_threshold_select_reg; | |
790 | }; | |
791 | ||
792 | struct display_queue_expire_num { | |
793 | struct iga1_display_queue_expire_num | |
794 | iga1_display_queue_expire_num_reg; | |
795 | struct iga2_display_queue_expire_num | |
796 | iga2_display_queue_expire_num_reg; | |
797 | }; | |
798 | ||
799 | struct iga1_crtc_timing { | |
800 | struct iga1_hor_total hor_total; | |
801 | struct iga1_hor_addr hor_addr; | |
802 | struct iga1_hor_blank_start hor_blank_start; | |
803 | struct iga1_hor_blank_end hor_blank_end; | |
804 | struct iga1_hor_sync_start hor_sync_start; | |
805 | struct iga1_hor_sync_end hor_sync_end; | |
806 | struct iga1_ver_total ver_total; | |
807 | struct iga1_ver_addr ver_addr; | |
808 | struct iga1_ver_blank_start ver_blank_start; | |
809 | struct iga1_ver_blank_end ver_blank_end; | |
810 | struct iga1_ver_sync_start ver_sync_start; | |
811 | struct iga1_ver_sync_end ver_sync_end; | |
812 | }; | |
813 | ||
814 | struct iga2_shadow_crtc_timing { | |
815 | struct iga2_shadow_hor_total hor_total_shadow; | |
816 | struct iga2_shadow_hor_blank_end hor_blank_end_shadow; | |
817 | struct iga2_shadow_ver_total ver_total_shadow; | |
818 | struct iga2_shadow_ver_addr ver_addr_shadow; | |
819 | struct iga2_shadow_ver_blank_start ver_blank_start_shadow; | |
820 | struct iga2_shadow_ver_blank_end ver_blank_end_shadow; | |
821 | struct iga2_shadow_ver_sync_start ver_sync_start_shadow; | |
822 | struct iga2_shadow_ver_sync_end ver_sync_end_shadow; | |
823 | }; | |
824 | ||
825 | struct iga2_crtc_timing { | |
826 | struct iga2_hor_total hor_total; | |
827 | struct iga2_hor_addr hor_addr; | |
828 | struct iga2_hor_blank_start hor_blank_start; | |
829 | struct iga2_hor_blank_end hor_blank_end; | |
830 | struct iga2_hor_sync_start hor_sync_start; | |
831 | struct iga2_hor_sync_end hor_sync_end; | |
832 | struct iga2_ver_total ver_total; | |
833 | struct iga2_ver_addr ver_addr; | |
834 | struct iga2_ver_blank_start ver_blank_start; | |
835 | struct iga2_ver_blank_end ver_blank_end; | |
836 | struct iga2_ver_sync_start ver_sync_start; | |
837 | struct iga2_ver_sync_end ver_sync_end; | |
838 | }; | |
839 | ||
840 | /* device ID */ | |
841 | #define CLE266 0x3123 | |
842 | #define KM400 0x3205 | |
843 | #define CN400_FUNCTION2 0x2259 | |
844 | #define CN400_FUNCTION3 0x3259 | |
845 | /* support VT3314 chipset */ | |
846 | #define CN700_FUNCTION2 0x2314 | |
847 | #define CN700_FUNCTION3 0x3208 | |
848 | /* VT3324 chipset */ | |
849 | #define CX700_FUNCTION2 0x2324 | |
850 | #define CX700_FUNCTION3 0x3324 | |
851 | /* VT3204 chipset*/ | |
852 | #define KM800_FUNCTION3 0x3204 | |
853 | /* VT3336 chipset*/ | |
854 | #define KM890_FUNCTION3 0x3336 | |
855 | /* VT3327 chipset*/ | |
856 | #define P4M890_FUNCTION3 0x3327 | |
857 | /* VT3293 chipset*/ | |
858 | #define CN750_FUNCTION3 0x3208 | |
859 | /* VT3364 chipset*/ | |
860 | #define P4M900_FUNCTION3 0x3364 | |
861 | /* VT3353 chipset*/ | |
862 | #define VX800_FUNCTION3 0x3353 | |
863 | ||
864 | #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value) | |
865 | ||
866 | struct IODATA { | |
867 | u8 Index; | |
868 | u8 Mask; | |
869 | u8 Data; | |
870 | }; | |
871 | ||
872 | struct pci_device_id_info { | |
873 | u32 vendor; | |
874 | u32 device; | |
875 | u32 chip_index; | |
876 | }; | |
877 | ||
878 | extern unsigned int viafb_second_virtual_xres; | |
879 | extern unsigned int viafb_second_offset; | |
880 | extern int viafb_second_size; | |
881 | extern int viafb_SAMM_ON; | |
882 | extern int viafb_dual_fb; | |
883 | extern int viafb_LCD2_ON; | |
884 | extern int viafb_LCD_ON; | |
885 | extern int viafb_DVI_ON; | |
886 | extern int viafb_accel; | |
887 | extern int viafb_hotplug; | |
888 | ||
889 | void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask); | |
890 | void viafb_set_output_path(int device, int set_iga, | |
891 | int output_interface); | |
892 | void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, | |
893 | int mode_index, int bpp_byte, int set_iga); | |
894 | ||
895 | void viafb_set_vclock(u32 CLK, int set_iga); | |
896 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, | |
897 | struct io_register *reg, | |
898 | int io_type); | |
899 | void viafb_crt_disable(void); | |
900 | void viafb_crt_enable(void); | |
901 | void init_ad9389(void); | |
902 | /* Access I/O Function */ | |
903 | void viafb_write_reg(u8 index, u16 io_port, u8 data); | |
904 | u8 viafb_read_reg(int io_port, u8 index); | |
905 | void viafb_lock_crt(void); | |
906 | void viafb_unlock_crt(void); | |
907 | void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga); | |
908 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); | |
909 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum); | |
910 | struct VideoModeTable *viafb_get_modetbl_pointer(int Index); | |
911 | u32 viafb_get_clk_value(int clk); | |
912 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); | |
913 | void viafb_set_color_depth(int bpp_byte, int set_iga); | |
914 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ | |
915 | *p_gfx_dpa_setting); | |
916 | ||
917 | int viafb_setmode(int vmode_index, int hor_res, int ver_res, | |
918 | int video_bpp, int vmode_index1, int hor_res1, | |
919 | int ver_res1, int video_bpp1); | |
920 | void viafb_init_chip_info(void); | |
921 | void viafb_init_dac(int set_iga); | |
922 | int viafb_get_pixclock(int hres, int vres, int vmode_refresh); | |
923 | int viafb_get_refresh(int hres, int vres, u32 float_refresh); | |
924 | void viafb_update_device_setting(int hres, int vres, int bpp, | |
925 | int vmode_refresh, int flag); | |
926 | void viafb_get_mmio_info(unsigned long *mmio_base, | |
927 | unsigned long *mmio_len); | |
928 | ||
929 | void viafb_set_iga_path(void); | |
930 | void viafb_set_start_addr(void); | |
931 | void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); | |
932 | ||
933 | #endif /* __HW_H__ */ |