Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
f3294a33 | 28 | #include <linux/bootmem.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
1d16b53e | 39 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 40 | |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/smp.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/timer.h> | |
306e440d | 45 | #include <asm/i8259.h> |
3e4ff115 | 46 | #include <asm/nmi.h> |
2d3fcc1c | 47 | #include <asm/msidef.h> |
8b955b0d | 48 | #include <asm/hypertransport.h> |
1da177e4 LT |
49 | |
50 | #include <mach_apic.h> | |
874c4fe3 | 51 | #include <mach_apicdef.h> |
1da177e4 | 52 | |
1da177e4 LT |
53 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
54 | atomic_t irq_mis_count; | |
55 | ||
fcfd636a EB |
56 | /* Where if anywhere is the i8259 connect in external int mode */ |
57 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
58 | ||
1da177e4 | 59 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 60 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 61 | |
35542c5e | 62 | int timer_through_8259 __initdata; |
f9262c12 | 63 | |
1da177e4 LT |
64 | /* |
65 | * Is the SiS APIC rmw bug present ? | |
66 | * -1 = don't know, 0 = no, 1 = yes | |
67 | */ | |
68 | int sis_apic_bug = -1; | |
69 | ||
70 | /* | |
71 | * # of IRQ routing registers | |
72 | */ | |
73 | int nr_ioapic_registers[MAX_IO_APICS]; | |
74 | ||
9f640ccb | 75 | /* I/O APIC entries */ |
ec2cd0a2 | 76 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
77 | int nr_ioapics; |
78 | ||
584f734d | 79 | /* MP IRQ source entries */ |
2fddb6e2 | 80 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
81 | |
82 | /* # of MP IRQ source entries */ | |
83 | int mp_irq_entries; | |
84 | ||
8732fc4b AS |
85 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
86 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
87 | #endif | |
88 | ||
89 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
90 | ||
1a3f239d | 91 | static int disable_timer_pin_1 __initdata; |
66759a01 | 92 | |
1da177e4 LT |
93 | /* |
94 | * Rough estimation of how many shared IRQs there are, can | |
95 | * be changed anytime. | |
96 | */ | |
97 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
98 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
99 | ||
100 | /* | |
101 | * This is performance-critical, we want to do it O(1) | |
102 | * | |
103 | * the indexing order of this array favors 1:1 mappings | |
104 | * between pins and IRQs. | |
105 | */ | |
106 | ||
107 | static struct irq_pin_list { | |
108 | int apic, pin, next; | |
109 | } irq_2_pin[PIN_MAP_SIZE]; | |
110 | ||
130fe05d LT |
111 | struct io_apic { |
112 | unsigned int index; | |
113 | unsigned int unused[3]; | |
114 | unsigned int data; | |
115 | }; | |
116 | ||
117 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
118 | { | |
119 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 120 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
121 | } |
122 | ||
123 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
124 | { | |
125 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
126 | writel(reg, &io_apic->index); | |
127 | return readl(&io_apic->data); | |
128 | } | |
129 | ||
130 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
131 | { | |
132 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
133 | writel(reg, &io_apic->index); | |
134 | writel(value, &io_apic->data); | |
135 | } | |
136 | ||
137 | /* | |
138 | * Re-write a value: to be used for read-modify-write | |
139 | * cycles where the read already set up the index register. | |
140 | * | |
141 | * Older SiS APIC requires we rewrite the index register | |
142 | */ | |
143 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
144 | { | |
cb468984 | 145 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
146 | if (sis_apic_bug) |
147 | writel(reg, &io_apic->index); | |
148 | writel(value, &io_apic->data); | |
149 | } | |
150 | ||
cf4c6a2f AK |
151 | union entry_union { |
152 | struct { u32 w1, w2; }; | |
153 | struct IO_APIC_route_entry entry; | |
154 | }; | |
155 | ||
156 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
157 | { | |
158 | union entry_union eu; | |
159 | unsigned long flags; | |
160 | spin_lock_irqsave(&ioapic_lock, flags); | |
161 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
162 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
163 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
164 | return eu.entry; | |
165 | } | |
166 | ||
f9dadfa7 LT |
167 | /* |
168 | * When we write a new IO APIC routing entry, we need to write the high | |
169 | * word first! If the mask bit in the low word is clear, we will enable | |
170 | * the interrupt, and we need to make sure the entry is fully populated | |
171 | * before that happens. | |
172 | */ | |
d15512f4 AK |
173 | static void |
174 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 175 | { |
cf4c6a2f AK |
176 | union entry_union eu; |
177 | eu.entry = e; | |
f9dadfa7 LT |
178 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
179 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
180 | } |
181 | ||
182 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
183 | { | |
184 | unsigned long flags; | |
185 | spin_lock_irqsave(&ioapic_lock, flags); | |
186 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
187 | spin_unlock_irqrestore(&ioapic_lock, flags); |
188 | } | |
189 | ||
190 | /* | |
191 | * When we mask an IO APIC routing entry, we need to write the low | |
192 | * word first, in order to set the mask bit before we change the | |
193 | * high bits! | |
194 | */ | |
195 | static void ioapic_mask_entry(int apic, int pin) | |
196 | { | |
197 | unsigned long flags; | |
198 | union entry_union eu = { .entry.mask = 1 }; | |
199 | ||
cf4c6a2f AK |
200 | spin_lock_irqsave(&ioapic_lock, flags); |
201 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
202 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
203 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
204 | } | |
205 | ||
1da177e4 LT |
206 | /* |
207 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
208 | * shared ISA-space IRQs, so we have to support them. We are super | |
209 | * fast in the common case, and fast for shared ISA-space IRQs. | |
210 | */ | |
211 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
212 | { | |
213 | static int first_free_entry = NR_IRQS; | |
214 | struct irq_pin_list *entry = irq_2_pin + irq; | |
215 | ||
216 | while (entry->next) | |
217 | entry = irq_2_pin + entry->next; | |
218 | ||
219 | if (entry->pin != -1) { | |
220 | entry->next = first_free_entry; | |
221 | entry = irq_2_pin + entry->next; | |
222 | if (++first_free_entry >= PIN_MAP_SIZE) | |
223 | panic("io_apic.c: whoops"); | |
224 | } | |
225 | entry->apic = apic; | |
226 | entry->pin = pin; | |
227 | } | |
228 | ||
229 | /* | |
230 | * Reroute an IRQ to a different pin. | |
231 | */ | |
232 | static void __init replace_pin_at_irq(unsigned int irq, | |
233 | int oldapic, int oldpin, | |
234 | int newapic, int newpin) | |
235 | { | |
236 | struct irq_pin_list *entry = irq_2_pin + irq; | |
237 | ||
238 | while (1) { | |
239 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
240 | entry->apic = newapic; | |
241 | entry->pin = newpin; | |
242 | } | |
243 | if (!entry->next) | |
244 | break; | |
245 | entry = irq_2_pin + entry->next; | |
246 | } | |
247 | } | |
248 | ||
36062448 | 249 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 LT |
250 | { |
251 | struct irq_pin_list *entry = irq_2_pin + irq; | |
252 | unsigned int pin, reg; | |
253 | ||
254 | for (;;) { | |
255 | pin = entry->pin; | |
256 | if (pin == -1) | |
257 | break; | |
258 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
259 | reg &= ~disable; | |
260 | reg |= enable; | |
261 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
262 | if (!entry->next) | |
263 | break; | |
264 | entry = irq_2_pin + entry->next; | |
265 | } | |
266 | } | |
267 | ||
268 | /* mask = 1 */ | |
36062448 | 269 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 270 | { |
46b3b4ef | 271 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
272 | } |
273 | ||
274 | /* mask = 0 */ | |
36062448 | 275 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 276 | { |
46b3b4ef | 277 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
278 | } |
279 | ||
280 | /* mask = 1, trigger = 0 */ | |
36062448 | 281 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 282 | { |
46b3b4ef CG |
283 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
284 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
285 | } |
286 | ||
287 | /* mask = 0, trigger = 1 */ | |
36062448 | 288 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 289 | { |
46b3b4ef CG |
290 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
291 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
292 | } |
293 | ||
36062448 | 294 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
295 | { |
296 | unsigned long flags; | |
297 | ||
298 | spin_lock_irqsave(&ioapic_lock, flags); | |
299 | __mask_IO_APIC_irq(irq); | |
300 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
301 | } | |
302 | ||
36062448 | 303 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
304 | { |
305 | unsigned long flags; | |
306 | ||
307 | spin_lock_irqsave(&ioapic_lock, flags); | |
308 | __unmask_IO_APIC_irq(irq); | |
309 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
310 | } | |
311 | ||
312 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
313 | { | |
314 | struct IO_APIC_route_entry entry; | |
36062448 | 315 | |
1da177e4 | 316 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 317 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
318 | if (entry.delivery_mode == dest_SMI) |
319 | return; | |
320 | ||
321 | /* | |
322 | * Disable it in the IO-APIC irq-routing table: | |
323 | */ | |
f9dadfa7 | 324 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
325 | } |
326 | ||
36062448 | 327 | static void clear_IO_APIC(void) |
1da177e4 LT |
328 | { |
329 | int apic, pin; | |
330 | ||
331 | for (apic = 0; apic < nr_ioapics; apic++) | |
332 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
333 | clear_IO_APIC_pin(apic, pin); | |
334 | } | |
335 | ||
54d5d424 | 336 | #ifdef CONFIG_SMP |
1da177e4 LT |
337 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
338 | { | |
339 | unsigned long flags; | |
340 | int pin; | |
341 | struct irq_pin_list *entry = irq_2_pin + irq; | |
342 | unsigned int apicid_value; | |
54d5d424 | 343 | cpumask_t tmp; |
36062448 | 344 | |
54d5d424 AR |
345 | cpus_and(tmp, cpumask, cpu_online_map); |
346 | if (cpus_empty(tmp)) | |
347 | tmp = TARGET_CPUS; | |
348 | ||
349 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
350 | ||
1da177e4 LT |
351 | apicid_value = cpu_mask_to_apicid(cpumask); |
352 | /* Prepare to do the io_apic_write */ | |
353 | apicid_value = apicid_value << 24; | |
354 | spin_lock_irqsave(&ioapic_lock, flags); | |
355 | for (;;) { | |
356 | pin = entry->pin; | |
357 | if (pin == -1) | |
358 | break; | |
359 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
360 | if (!entry->next) | |
361 | break; | |
362 | entry = irq_2_pin + entry->next; | |
363 | } | |
9f0a5ba5 | 364 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
365 | spin_unlock_irqrestore(&ioapic_lock, flags); |
366 | } | |
367 | ||
368 | #if defined(CONFIG_IRQBALANCE) | |
369 | # include <asm/processor.h> /* kernel_thread() */ | |
370 | # include <linux/kernel_stat.h> /* kstat */ | |
371 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 372 | # include <linux/timer.h> |
36062448 | 373 | |
1da177e4 | 374 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
375 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
376 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
377 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
378 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
379 | ||
380 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
381 | static int physical_balance __read_mostly; | |
382 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
383 | |
384 | static struct irq_cpu_info { | |
36062448 PC |
385 | unsigned long *last_irq; |
386 | unsigned long *irq_delta; | |
1da177e4 LT |
387 | unsigned long irq; |
388 | } irq_cpu_data[NR_CPUS]; | |
389 | ||
390 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
36062448 PC |
391 | #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq]) |
392 | #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
1da177e4 LT |
393 | |
394 | #define IDLE_ENOUGH(cpu,now) \ | |
395 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
396 | ||
397 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
398 | ||
d5a7430d | 399 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 400 | |
1b61b910 ZY |
401 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
402 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
403 | }; | |
1da177e4 | 404 | |
1b61b910 ZY |
405 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
406 | { | |
407 | balance_irq_affinity[irq] = mask; | |
408 | } | |
1da177e4 LT |
409 | |
410 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
411 | unsigned long now, int direction) | |
412 | { | |
413 | int search_idle = 1; | |
414 | int cpu = curr_cpu; | |
415 | ||
416 | goto inside; | |
417 | ||
418 | do { | |
419 | if (unlikely(cpu == curr_cpu)) | |
420 | search_idle = 0; | |
421 | inside: | |
422 | if (direction == 1) { | |
423 | cpu++; | |
424 | if (cpu >= NR_CPUS) | |
425 | cpu = 0; | |
426 | } else { | |
427 | cpu--; | |
428 | if (cpu == -1) | |
429 | cpu = NR_CPUS-1; | |
430 | } | |
36062448 PC |
431 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) || |
432 | (search_idle && !IDLE_ENOUGH(cpu, now))); | |
1da177e4 LT |
433 | |
434 | return cpu; | |
435 | } | |
436 | ||
437 | static inline void balance_irq(int cpu, int irq) | |
438 | { | |
439 | unsigned long now = jiffies; | |
440 | cpumask_t allowed_mask; | |
441 | unsigned int new_cpu; | |
36062448 | 442 | |
1da177e4 | 443 | if (irqbalance_disabled) |
36062448 | 444 | return; |
1da177e4 | 445 | |
1b61b910 | 446 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 | 447 | new_cpu = move(cpu, allowed_mask, now, 1); |
36062448 | 448 | if (cpu != new_cpu) |
54d5d424 | 449 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
450 | } |
451 | ||
452 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
453 | { | |
454 | int i, j; | |
edc2cbf4 | 455 | |
394e3902 AM |
456 | for_each_online_cpu(i) { |
457 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
458 | if (!irq_desc[j].action) |
459 | continue; | |
460 | /* Is it a significant load ? */ | |
36062448 | 461 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) < |
1da177e4 LT |
462 | useful_load_threshold) |
463 | continue; | |
464 | balance_irq(i, j); | |
465 | } | |
466 | } | |
467 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 468 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
469 | return; |
470 | } | |
471 | ||
472 | static void do_irq_balance(void) | |
473 | { | |
474 | int i, j; | |
475 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
476 | unsigned long move_this_load = 0; | |
477 | int max_loaded = 0, min_loaded = 0; | |
478 | int load; | |
479 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
480 | int selected_irq; | |
481 | int tmp_loaded, first_attempt = 1; | |
482 | unsigned long tmp_cpu_irq; | |
483 | unsigned long imbalance = 0; | |
484 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
485 | ||
c8912599 | 486 | for_each_possible_cpu(i) { |
1da177e4 LT |
487 | int package_index; |
488 | CPU_IRQ(i) = 0; | |
489 | if (!cpu_online(i)) | |
490 | continue; | |
491 | package_index = CPU_TO_PACKAGEINDEX(i); | |
492 | for (j = 0; j < NR_IRQS; j++) { | |
493 | unsigned long value_now, delta; | |
950f4427 TG |
494 | /* Is this an active IRQ or balancing disabled ? */ |
495 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 | 496 | continue; |
36062448 PC |
497 | if (package_index == i) |
498 | IRQ_DELTA(package_index, j) = 0; | |
1da177e4 LT |
499 | /* Determine the total count per processor per IRQ */ |
500 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
501 | ||
502 | /* Determine the activity per processor per IRQ */ | |
36062448 | 503 | delta = value_now - LAST_CPU_IRQ(i, j); |
1da177e4 LT |
504 | |
505 | /* Update last_cpu_irq[][] for the next time */ | |
36062448 | 506 | LAST_CPU_IRQ(i, j) = value_now; |
1da177e4 LT |
507 | |
508 | /* Ignore IRQs whose rate is less than the clock */ | |
509 | if (delta < useful_load_threshold) | |
510 | continue; | |
511 | /* update the load for the processor or package total */ | |
36062448 | 512 | IRQ_DELTA(package_index, j) += delta; |
1da177e4 LT |
513 | |
514 | /* Keep track of the higher numbered sibling as well */ | |
515 | if (i != package_index) | |
516 | CPU_IRQ(i) += delta; | |
517 | /* | |
518 | * We have sibling A and sibling B in the package | |
519 | * | |
520 | * cpu_irq[A] = load for cpu A + load for cpu B | |
521 | * cpu_irq[B] = load for cpu B | |
522 | */ | |
523 | CPU_IRQ(package_index) += delta; | |
524 | } | |
525 | } | |
526 | /* Find the least loaded processor package */ | |
394e3902 | 527 | for_each_online_cpu(i) { |
1da177e4 LT |
528 | if (i != CPU_TO_PACKAGEINDEX(i)) |
529 | continue; | |
530 | if (min_cpu_irq > CPU_IRQ(i)) { | |
531 | min_cpu_irq = CPU_IRQ(i); | |
532 | min_loaded = i; | |
533 | } | |
534 | } | |
535 | max_cpu_irq = ULONG_MAX; | |
536 | ||
537 | tryanothercpu: | |
36062448 PC |
538 | /* |
539 | * Look for heaviest loaded processor. | |
1da177e4 LT |
540 | * We may come back to get the next heaviest loaded processor. |
541 | * Skip processors with trivial loads. | |
542 | */ | |
543 | tmp_cpu_irq = 0; | |
544 | tmp_loaded = -1; | |
394e3902 | 545 | for_each_online_cpu(i) { |
1da177e4 LT |
546 | if (i != CPU_TO_PACKAGEINDEX(i)) |
547 | continue; | |
36062448 | 548 | if (max_cpu_irq <= CPU_IRQ(i)) |
1da177e4 LT |
549 | continue; |
550 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
551 | tmp_cpu_irq = CPU_IRQ(i); | |
552 | tmp_loaded = i; | |
553 | } | |
554 | } | |
555 | ||
556 | if (tmp_loaded == -1) { | |
36062448 PC |
557 | /* |
558 | * In the case of small number of heavy interrupt sources, | |
559 | * loading some of the cpus too much. We use Ingo's original | |
1da177e4 LT |
560 | * approach to rotate them around. |
561 | */ | |
562 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
563 | rotate_irqs_among_cpus(useful_load_threshold); | |
564 | return; | |
565 | } | |
566 | goto not_worth_the_effort; | |
567 | } | |
36062448 | 568 | |
1da177e4 LT |
569 | first_attempt = 0; /* heaviest search */ |
570 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
571 | max_loaded = tmp_loaded; /* processor */ | |
572 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
36062448 PC |
573 | |
574 | /* | |
575 | * if imbalance is less than approx 10% of max load, then | |
1da177e4 LT |
576 | * observe diminishing returns action. - quit |
577 | */ | |
edc2cbf4 | 578 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 579 | goto not_worth_the_effort; |
1da177e4 LT |
580 | |
581 | tryanotherirq: | |
582 | /* if we select an IRQ to move that can't go where we want, then | |
583 | * see if there is another one to try. | |
584 | */ | |
585 | move_this_load = 0; | |
586 | selected_irq = -1; | |
587 | for (j = 0; j < NR_IRQS; j++) { | |
588 | /* Is this an active IRQ? */ | |
589 | if (!irq_desc[j].action) | |
590 | continue; | |
36062448 | 591 | if (imbalance <= IRQ_DELTA(max_loaded, j)) |
1da177e4 LT |
592 | continue; |
593 | /* Try to find the IRQ that is closest to the imbalance | |
594 | * without going over. | |
595 | */ | |
36062448 PC |
596 | if (move_this_load < IRQ_DELTA(max_loaded, j)) { |
597 | move_this_load = IRQ_DELTA(max_loaded, j); | |
1da177e4 LT |
598 | selected_irq = j; |
599 | } | |
600 | } | |
36062448 | 601 | if (selected_irq == -1) |
1da177e4 | 602 | goto tryanothercpu; |
1da177e4 LT |
603 | |
604 | imbalance = move_this_load; | |
36062448 | 605 | |
27b46d76 | 606 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
607 | * values in the one of the siblings cpu_irq[], |
608 | * to use the same code for physical and logical processors | |
36062448 | 609 | * as much as possible. |
1da177e4 LT |
610 | * |
611 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
612 | * sibling A and sibling B in the slot for the lowest numbered | |
613 | * sibling (A), _AND_ the load for sibling B in the slot for | |
614 | * the higher numbered sibling. | |
615 | * | |
616 | * We seek the least loaded sibling by making the comparison | |
617 | * (A+B)/2 vs B | |
618 | */ | |
619 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 620 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
621 | if (load > CPU_IRQ(j)) { |
622 | /* This won't change cpu_sibling_map[min_loaded] */ | |
623 | load = CPU_IRQ(j); | |
624 | min_loaded = j; | |
625 | } | |
626 | } | |
627 | ||
1b61b910 ZY |
628 | cpus_and(allowed_mask, |
629 | cpu_online_map, | |
630 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
631 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
632 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
633 | ||
634 | if (!cpus_empty(tmp)) { | |
1da177e4 | 635 | /* mark for change destination */ |
54d5d424 AR |
636 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
637 | ||
36062448 | 638 | /* Since we made a change, come back sooner to |
1da177e4 LT |
639 | * check for more variation. |
640 | */ | |
641 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 642 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
643 | return; |
644 | } | |
645 | goto tryanotherirq; | |
646 | ||
647 | not_worth_the_effort: | |
648 | /* | |
649 | * if we did not find an IRQ to move, then adjust the time interval | |
650 | * upward | |
651 | */ | |
652 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
36062448 | 653 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); |
1da177e4 LT |
654 | return; |
655 | } | |
656 | ||
657 | static int balanced_irq(void *unused) | |
658 | { | |
659 | int i; | |
660 | unsigned long prev_balance_time = jiffies; | |
661 | long time_remaining = balanced_irq_interval; | |
662 | ||
1da177e4 LT |
663 | /* push everything to CPU 0 to give us a starting point. */ |
664 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 665 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 666 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
667 | } |
668 | ||
83144186 | 669 | set_freezable(); |
1da177e4 | 670 | for ( ; ; ) { |
52e6e630 | 671 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 672 | try_to_freeze(); |
1da177e4 LT |
673 | if (time_after(jiffies, |
674 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 675 | preempt_disable(); |
1da177e4 LT |
676 | do_irq_balance(); |
677 | prev_balance_time = jiffies; | |
678 | time_remaining = balanced_irq_interval; | |
f3705136 | 679 | preempt_enable(); |
1da177e4 LT |
680 | } |
681 | } | |
682 | return 0; | |
683 | } | |
684 | ||
685 | static int __init balanced_irq_init(void) | |
686 | { | |
687 | int i; | |
688 | struct cpuinfo_x86 *c; | |
689 | cpumask_t tmp; | |
690 | ||
691 | cpus_shift_right(tmp, cpu_online_map, 2); | |
36062448 | 692 | c = &boot_cpu_data; |
1da177e4 LT |
693 | /* When not overwritten by the command line ask subarchitecture. */ |
694 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
695 | irqbalance_disabled = NO_BALANCE_IRQ; | |
696 | if (irqbalance_disabled) | |
697 | return 0; | |
36062448 | 698 | |
1da177e4 LT |
699 | /* disable irqbalance completely if there is only one processor online */ |
700 | if (num_online_cpus() < 2) { | |
701 | irqbalance_disabled = 1; | |
702 | return 0; | |
703 | } | |
704 | /* | |
705 | * Enable physical balance only if more than 1 physical processor | |
706 | * is present | |
707 | */ | |
708 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
709 | physical_balance = 1; | |
710 | ||
394e3902 | 711 | for_each_online_cpu(i) { |
25556c16 CJ |
712 | irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
713 | irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
1da177e4 LT |
714 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { |
715 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
716 | goto failed; | |
717 | } | |
1da177e4 | 718 | } |
36062448 | 719 | |
1da177e4 | 720 | printk(KERN_INFO "Starting balanced_irq\n"); |
f26d6a2b | 721 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 722 | return 0; |
f26d6a2b | 723 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 724 | failed: |
c8912599 | 725 | for_each_possible_cpu(i) { |
4ae6673e | 726 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 727 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 728 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 729 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
730 | } |
731 | return 0; | |
732 | } | |
733 | ||
c2481cc4 | 734 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
735 | { |
736 | irqbalance_disabled = 1; | |
9b41046c | 737 | return 1; |
1da177e4 LT |
738 | } |
739 | ||
740 | __setup("noirqbalance", irqbalance_disable); | |
741 | ||
1da177e4 | 742 | late_initcall(balanced_irq_init); |
1da177e4 | 743 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 744 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
745 | |
746 | #ifndef CONFIG_SMP | |
75604d7f | 747 | void send_IPI_self(int vector) |
1da177e4 LT |
748 | { |
749 | unsigned int cfg; | |
750 | ||
751 | /* | |
752 | * Wait for idle. | |
753 | */ | |
754 | apic_wait_icr_idle(); | |
755 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
756 | /* | |
757 | * Send the IPI. The write to APIC_ICR fires this off. | |
758 | */ | |
593f4a78 | 759 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
760 | } |
761 | #endif /* !CONFIG_SMP */ | |
762 | ||
763 | ||
764 | /* | |
765 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
766 | * specific CPU-side IRQs. | |
767 | */ | |
768 | ||
769 | #define MAX_PIRQS 8 | |
770 | static int pirq_entries [MAX_PIRQS]; | |
771 | static int pirqs_enabled; | |
772 | int skip_ioapic_setup; | |
773 | ||
1da177e4 LT |
774 | static int __init ioapic_pirq_setup(char *str) |
775 | { | |
776 | int i, max; | |
777 | int ints[MAX_PIRQS+1]; | |
778 | ||
779 | get_options(str, ARRAY_SIZE(ints), ints); | |
780 | ||
781 | for (i = 0; i < MAX_PIRQS; i++) | |
782 | pirq_entries[i] = -1; | |
783 | ||
784 | pirqs_enabled = 1; | |
785 | apic_printk(APIC_VERBOSE, KERN_INFO | |
786 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
787 | max = MAX_PIRQS; | |
788 | if (ints[0] < MAX_PIRQS) | |
789 | max = ints[0]; | |
790 | ||
791 | for (i = 0; i < max; i++) { | |
792 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
793 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
794 | /* | |
795 | * PIRQs are mapped upside down, usually. | |
796 | */ | |
797 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
798 | } | |
799 | return 1; | |
800 | } | |
801 | ||
802 | __setup("pirq=", ioapic_pirq_setup); | |
803 | ||
804 | /* | |
805 | * Find the IRQ entry number of a certain pin. | |
806 | */ | |
807 | static int find_irq_entry(int apic, int pin, int type) | |
808 | { | |
809 | int i; | |
810 | ||
811 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
812 | if (mp_irqs[i].mp_irqtype == type && |
813 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
814 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
815 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
816 | return i; |
817 | ||
818 | return -1; | |
819 | } | |
820 | ||
821 | /* | |
822 | * Find the pin to which IRQ[irq] (ISA) is connected | |
823 | */ | |
fcfd636a | 824 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
825 | { |
826 | int i; | |
827 | ||
828 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 829 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 830 | |
d27e2b8e | 831 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
832 | (mp_irqs[i].mp_irqtype == type) && |
833 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 834 | |
2fddb6e2 | 835 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
836 | } |
837 | return -1; | |
838 | } | |
839 | ||
fcfd636a EB |
840 | static int __init find_isa_irq_apic(int irq, int type) |
841 | { | |
842 | int i; | |
843 | ||
844 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 845 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 846 | |
73b2961b | 847 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
848 | (mp_irqs[i].mp_irqtype == type) && |
849 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
850 | break; |
851 | } | |
852 | if (i < mp_irq_entries) { | |
853 | int apic; | |
36062448 | 854 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 855 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
856 | return apic; |
857 | } | |
858 | } | |
859 | ||
860 | return -1; | |
861 | } | |
862 | ||
1da177e4 LT |
863 | /* |
864 | * Find a specific PCI IRQ entry. | |
865 | * Not an __init, possibly needed by modules | |
866 | */ | |
867 | static int pin_2_irq(int idx, int apic, int pin); | |
868 | ||
869 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
870 | { | |
871 | int apic, i, best_guess = -1; | |
872 | ||
873 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
874 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 875 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
876 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
877 | return -1; | |
878 | } | |
879 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 880 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
881 | |
882 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
883 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
884 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
885 | break; |
886 | ||
47cab822 | 887 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 888 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 889 | (bus == lbus) && |
2fddb6e2 | 890 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 891 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
892 | |
893 | if (!(apic || IO_APIC_IRQ(irq))) | |
894 | continue; | |
895 | ||
2fddb6e2 | 896 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
897 | return irq; |
898 | /* | |
899 | * Use the first all-but-pin matching entry as a | |
900 | * best-guess fuzzy result for broken mptables. | |
901 | */ | |
902 | if (best_guess < 0) | |
903 | best_guess = irq; | |
904 | } | |
905 | } | |
906 | return best_guess; | |
907 | } | |
129f6946 | 908 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
909 | |
910 | /* | |
36062448 | 911 | * This function currently is only a helper for the i386 smp boot process where |
1da177e4 LT |
912 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
913 | * so mask in all cases should simply be TARGET_CPUS | |
914 | */ | |
54d5d424 | 915 | #ifdef CONFIG_SMP |
1da177e4 LT |
916 | void __init setup_ioapic_dest(void) |
917 | { | |
918 | int pin, ioapic, irq, irq_entry; | |
919 | ||
920 | if (skip_ioapic_setup == 1) | |
921 | return; | |
922 | ||
923 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
924 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
925 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
926 | if (irq_entry == -1) | |
927 | continue; | |
928 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
929 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
930 | } | |
931 | ||
932 | } | |
933 | } | |
54d5d424 | 934 | #endif |
1da177e4 | 935 | |
c0a282c2 | 936 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
937 | /* |
938 | * EISA Edge/Level control register, ELCR | |
939 | */ | |
940 | static int EISA_ELCR(unsigned int irq) | |
941 | { | |
942 | if (irq < 16) { | |
943 | unsigned int port = 0x4d0 + (irq >> 3); | |
944 | return (inb(port) >> (irq & 7)) & 1; | |
945 | } | |
946 | apic_printk(APIC_VERBOSE, KERN_INFO | |
947 | "Broken MPtable reports ISA irq %d\n", irq); | |
948 | return 0; | |
949 | } | |
c0a282c2 | 950 | #endif |
1da177e4 | 951 | |
6728801d AS |
952 | /* ISA interrupts are always polarity zero edge triggered, |
953 | * when listed as conforming in the MP table. */ | |
954 | ||
955 | #define default_ISA_trigger(idx) (0) | |
956 | #define default_ISA_polarity(idx) (0) | |
957 | ||
1da177e4 LT |
958 | /* EISA interrupts are always polarity zero and can be edge or level |
959 | * trigger depending on the ELCR value. If an interrupt is listed as | |
960 | * EISA conforming in the MP table, that means its trigger type must | |
961 | * be read in from the ELCR */ | |
962 | ||
2fddb6e2 | 963 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 964 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
965 | |
966 | /* PCI interrupts are always polarity one level triggered, | |
967 | * when listed as conforming in the MP table. */ | |
968 | ||
969 | #define default_PCI_trigger(idx) (1) | |
970 | #define default_PCI_polarity(idx) (1) | |
971 | ||
972 | /* MCA interrupts are always polarity zero level triggered, | |
973 | * when listed as conforming in the MP table. */ | |
974 | ||
975 | #define default_MCA_trigger(idx) (1) | |
6728801d | 976 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 977 | |
61fd47e0 | 978 | static int MPBIOS_polarity(int idx) |
1da177e4 | 979 | { |
2fddb6e2 | 980 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
981 | int polarity; |
982 | ||
983 | /* | |
984 | * Determine IRQ line polarity (high active or low active): | |
985 | */ | |
3de352bb | 986 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 987 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 988 | { |
36062448 PC |
989 | polarity = test_bit(bus, mp_bus_not_pci)? |
990 | default_ISA_polarity(idx): | |
991 | default_PCI_polarity(idx); | |
992 | break; | |
993 | } | |
994 | case 1: /* high active */ | |
995 | { | |
996 | polarity = 0; | |
997 | break; | |
998 | } | |
999 | case 2: /* reserved */ | |
1000 | { | |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1002 | polarity = 1; | |
1003 | break; | |
1004 | } | |
1005 | case 3: /* low active */ | |
1006 | { | |
1007 | polarity = 1; | |
1008 | break; | |
1009 | } | |
1010 | default: /* invalid */ | |
1011 | { | |
1012 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1013 | polarity = 1; | |
1014 | break; | |
1015 | } | |
1da177e4 LT |
1016 | } |
1017 | return polarity; | |
1018 | } | |
1019 | ||
1020 | static int MPBIOS_trigger(int idx) | |
1021 | { | |
2fddb6e2 | 1022 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1023 | int trigger; |
1024 | ||
1025 | /* | |
1026 | * Determine IRQ trigger mode (edge or level sensitive): | |
1027 | */ | |
3de352bb | 1028 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 1029 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 1030 | { |
36062448 PC |
1031 | trigger = test_bit(bus, mp_bus_not_pci)? |
1032 | default_ISA_trigger(idx): | |
1033 | default_PCI_trigger(idx); | |
c0a282c2 | 1034 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
1035 | switch (mp_bus_id_to_type[bus]) { |
1036 | case MP_BUS_ISA: /* ISA pin */ | |
1037 | { | |
1038 | /* set before the switch */ | |
1da177e4 LT |
1039 | break; |
1040 | } | |
36062448 | 1041 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 1042 | { |
36062448 | 1043 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
1044 | break; |
1045 | } | |
36062448 | 1046 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 1047 | { |
36062448 | 1048 | /* set before the switch */ |
1da177e4 LT |
1049 | break; |
1050 | } | |
36062448 | 1051 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 1052 | { |
36062448 | 1053 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
1054 | break; |
1055 | } | |
36062448 | 1056 | default: |
1da177e4 LT |
1057 | { |
1058 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 1059 | trigger = 1; |
1da177e4 LT |
1060 | break; |
1061 | } | |
1062 | } | |
36062448 PC |
1063 | #endif |
1064 | break; | |
1065 | } | |
1066 | case 1: /* edge */ | |
1067 | { | |
1068 | trigger = 0; | |
1069 | break; | |
1070 | } | |
1071 | case 2: /* reserved */ | |
1072 | { | |
1073 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1074 | trigger = 1; | |
1075 | break; | |
1076 | } | |
1077 | case 3: /* level */ | |
1078 | { | |
1079 | trigger = 1; | |
1080 | break; | |
1081 | } | |
1082 | default: /* invalid */ | |
1083 | { | |
1084 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1085 | trigger = 0; | |
1086 | break; | |
1087 | } | |
1088 | } | |
1da177e4 LT |
1089 | return trigger; |
1090 | } | |
1091 | ||
1092 | static inline int irq_polarity(int idx) | |
1093 | { | |
1094 | return MPBIOS_polarity(idx); | |
1095 | } | |
1096 | ||
1097 | static inline int irq_trigger(int idx) | |
1098 | { | |
1099 | return MPBIOS_trigger(idx); | |
1100 | } | |
1101 | ||
1102 | static int pin_2_irq(int idx, int apic, int pin) | |
1103 | { | |
1104 | int irq, i; | |
2fddb6e2 | 1105 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1106 | |
1107 | /* | |
1108 | * Debugging check, we are in big trouble if this message pops up! | |
1109 | */ | |
2fddb6e2 | 1110 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1111 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1112 | ||
643befed | 1113 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 1114 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
1115 | else { |
1116 | /* | |
1117 | * PCI IRQs are mapped in order | |
1118 | */ | |
1119 | i = irq = 0; | |
1120 | while (i < apic) | |
1121 | irq += nr_ioapic_registers[i++]; | |
1122 | irq += pin; | |
1da177e4 | 1123 | |
643befed AS |
1124 | /* |
1125 | * For MPS mode, so far only needed by ES7000 platform | |
1126 | */ | |
1127 | if (ioapic_renumber_irq) | |
1128 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1129 | } |
1130 | ||
1131 | /* | |
1132 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1133 | */ | |
1134 | if ((pin >= 16) && (pin <= 23)) { | |
1135 | if (pirq_entries[pin-16] != -1) { | |
1136 | if (!pirq_entries[pin-16]) { | |
1137 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1138 | "disabling PIRQ%d\n", pin-16); | |
1139 | } else { | |
1140 | irq = pirq_entries[pin-16]; | |
1141 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1142 | "using PIRQ%d -> IRQ %d\n", | |
1143 | pin-16, irq); | |
1144 | } | |
1145 | } | |
1146 | } | |
1147 | return irq; | |
1148 | } | |
1149 | ||
1150 | static inline int IO_APIC_irq_trigger(int irq) | |
1151 | { | |
1152 | int apic, idx, pin; | |
1153 | ||
1154 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1155 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
1156 | idx = find_irq_entry(apic, pin, mp_INT); |
1157 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
1158 | return irq_trigger(idx); |
1159 | } | |
1160 | } | |
1161 | /* | |
1162 | * nonexistent IRQs are edge default | |
1163 | */ | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
7e95b593 | 1168 | static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1169 | |
ace80ab7 | 1170 | static int __assign_irq_vector(int irq) |
1da177e4 | 1171 | { |
36062448 | 1172 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset; |
dbeb2be2 | 1173 | int vector, offset; |
1da177e4 | 1174 | |
ace80ab7 | 1175 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1176 | |
b940d22d EB |
1177 | if (irq_vector[irq] > 0) |
1178 | return irq_vector[irq]; | |
ace80ab7 | 1179 | |
0a1ad60d | 1180 | vector = current_vector; |
8339f000 EB |
1181 | offset = current_offset; |
1182 | next: | |
1183 | vector += 8; | |
305b92a2 | 1184 | if (vector >= first_system_vector) { |
8339f000 EB |
1185 | offset = (offset + 1) % 8; |
1186 | vector = FIRST_DEVICE_VECTOR + offset; | |
1187 | } | |
1188 | if (vector == current_vector) | |
1189 | return -ENOSPC; | |
dbeb2be2 | 1190 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1191 | goto next; |
8339f000 EB |
1192 | |
1193 | current_vector = vector; | |
1194 | current_offset = offset; | |
b940d22d | 1195 | irq_vector[irq] = vector; |
ace80ab7 EB |
1196 | |
1197 | return vector; | |
1198 | } | |
0a1ad60d | 1199 | |
ace80ab7 EB |
1200 | static int assign_irq_vector(int irq) |
1201 | { | |
1202 | unsigned long flags; | |
1203 | int vector; | |
1204 | ||
1205 | spin_lock_irqsave(&vector_lock, flags); | |
1206 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1207 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1208 | |
0a1ad60d | 1209 | return vector; |
1da177e4 | 1210 | } |
3fde6900 GC |
1211 | |
1212 | void setup_vector_irq(int cpu) | |
1213 | { | |
1214 | } | |
1215 | ||
f5b9ed7a | 1216 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1217 | |
1218 | #define IOAPIC_AUTO -1 | |
1219 | #define IOAPIC_EDGE 0 | |
1220 | #define IOAPIC_LEVEL 1 | |
1221 | ||
d1bef4ed | 1222 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1223 | { |
6ebcc00e | 1224 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1225 | trigger == IOAPIC_LEVEL) { |
1226 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1227 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1228 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1229 | } else { |
1230 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1231 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1232 | handle_edge_irq, "edge"); | |
cc75b92d | 1233 | } |
ace80ab7 | 1234 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1235 | } |
1236 | ||
1237 | static void __init setup_IO_APIC_irqs(void) | |
1238 | { | |
1239 | struct IO_APIC_route_entry entry; | |
1240 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1241 | |
1242 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1243 | ||
1244 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1245 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1246 | ||
1247 | /* | |
1248 | * add it to the IO-APIC irq-routing table: | |
1249 | */ | |
36062448 | 1250 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1251 | |
1252 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1253 | entry.dest_mode = INT_DEST_MODE; | |
1254 | entry.mask = 0; /* enable IRQ */ | |
36062448 | 1255 | entry.dest.logical.logical_dest = |
1da177e4 LT |
1256 | cpu_mask_to_apicid(TARGET_CPUS); |
1257 | ||
36062448 | 1258 | idx = find_irq_entry(apic, pin, mp_INT); |
1da177e4 LT |
1259 | if (idx == -1) { |
1260 | if (first_notcon) { | |
1261 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1262 | " IO-APIC (apicid-pin) %d-%d", | |
ec2cd0a2 | 1263 | mp_ioapics[apic].mp_apicid, |
1da177e4 LT |
1264 | pin); |
1265 | first_notcon = 0; | |
1266 | } else | |
1267 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
ec2cd0a2 | 1268 | mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1269 | continue; |
1270 | } | |
1271 | ||
20d225b9 YL |
1272 | if (!first_notcon) { |
1273 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1274 | first_notcon = 1; | |
1275 | } | |
1276 | ||
1da177e4 LT |
1277 | entry.trigger = irq_trigger(idx); |
1278 | entry.polarity = irq_polarity(idx); | |
1279 | ||
1280 | if (irq_trigger(idx)) { | |
1281 | entry.trigger = 1; | |
1282 | entry.mask = 1; | |
1283 | } | |
1284 | ||
1285 | irq = pin_2_irq(idx, apic, pin); | |
1286 | /* | |
1287 | * skip adding the timer int on secondary nodes, which causes | |
1288 | * a small but painful rift in the time-space continuum | |
1289 | */ | |
1290 | if (multi_timer_check(apic, irq)) | |
1291 | continue; | |
1292 | else | |
1293 | add_pin_to_irq(irq, apic, pin); | |
1294 | ||
1295 | if (!apic && !IO_APIC_IRQ(irq)) | |
1296 | continue; | |
1297 | ||
1298 | if (IO_APIC_IRQ(irq)) { | |
1299 | vector = assign_irq_vector(irq); | |
1300 | entry.vector = vector; | |
1301 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
36062448 | 1302 | |
1da177e4 LT |
1303 | if (!apic && (irq < 16)) |
1304 | disable_8259A_irq(irq); | |
1305 | } | |
a2249cba | 1306 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1307 | } |
1308 | } | |
1309 | ||
1310 | if (!first_notcon) | |
1311 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1312 | } | |
1313 | ||
1314 | /* | |
f7633ce5 | 1315 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1316 | */ |
f7633ce5 MR |
1317 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1318 | int vector) | |
1da177e4 LT |
1319 | { |
1320 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1321 | |
36062448 | 1322 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1323 | |
1324 | /* | |
1325 | * We use logical delivery to get the timer IRQ | |
1326 | * to the first CPU. | |
1327 | */ | |
1328 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1329 | entry.mask = 1; /* mask IRQ now */ |
1da177e4 LT |
1330 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
1331 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1332 | entry.polarity = 0; | |
1333 | entry.trigger = 0; | |
1334 | entry.vector = vector; | |
1335 | ||
1336 | /* | |
1337 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1338 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1339 | */ |
f0825262 | 1340 | ioapic_register_intr(0, vector, IOAPIC_EDGE); |
1da177e4 LT |
1341 | |
1342 | /* | |
1343 | * Add it to the IO-APIC irq-routing table: | |
1344 | */ | |
cf4c6a2f | 1345 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1346 | } |
1347 | ||
1da177e4 LT |
1348 | void __init print_IO_APIC(void) |
1349 | { | |
1350 | int apic, i; | |
1351 | union IO_APIC_reg_00 reg_00; | |
1352 | union IO_APIC_reg_01 reg_01; | |
1353 | union IO_APIC_reg_02 reg_02; | |
1354 | union IO_APIC_reg_03 reg_03; | |
1355 | unsigned long flags; | |
1356 | ||
1357 | if (apic_verbosity == APIC_QUIET) | |
1358 | return; | |
1359 | ||
36062448 | 1360 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1361 | for (i = 0; i < nr_ioapics; i++) |
1362 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1363 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1364 | |
1365 | /* | |
1366 | * We are a bit conservative about what we expect. We have to | |
1367 | * know about every hardware change ASAP. | |
1368 | */ | |
1369 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1370 | ||
1371 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1372 | ||
1373 | spin_lock_irqsave(&ioapic_lock, flags); | |
1374 | reg_00.raw = io_apic_read(apic, 0); | |
1375 | reg_01.raw = io_apic_read(apic, 1); | |
1376 | if (reg_01.bits.version >= 0x10) | |
1377 | reg_02.raw = io_apic_read(apic, 2); | |
1378 | if (reg_01.bits.version >= 0x20) | |
1379 | reg_03.raw = io_apic_read(apic, 3); | |
1380 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1381 | ||
ec2cd0a2 | 1382 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1383 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1384 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1385 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1386 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1387 | |
1388 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1389 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1390 | |
1391 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1392 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1393 | |
1394 | /* | |
1395 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1396 | * but the value of reg_02 is read as the previous read register | |
1397 | * value, so ignore it if reg_02 == reg_01. | |
1398 | */ | |
1399 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1400 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1401 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1402 | } |
1403 | ||
1404 | /* | |
1405 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1406 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1407 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1408 | */ | |
1409 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1410 | reg_03.raw != reg_01.raw) { | |
1411 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1412 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1413 | } |
1414 | ||
1415 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1416 | ||
1417 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1418 | " Stat Dest Deli Vect: \n"); | |
1419 | ||
1420 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1421 | struct IO_APIC_route_entry entry; | |
1422 | ||
cf4c6a2f | 1423 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1424 | |
1425 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1426 | i, | |
1427 | entry.dest.logical.logical_dest, | |
1428 | entry.dest.physical.physical_dest | |
1429 | ); | |
1430 | ||
1431 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1432 | entry.mask, | |
1433 | entry.trigger, | |
1434 | entry.irr, | |
1435 | entry.polarity, | |
1436 | entry.delivery_status, | |
1437 | entry.dest_mode, | |
1438 | entry.delivery_mode, | |
1439 | entry.vector | |
1440 | ); | |
1441 | } | |
1442 | } | |
1da177e4 LT |
1443 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1444 | for (i = 0; i < NR_IRQS; i++) { | |
1445 | struct irq_pin_list *entry = irq_2_pin + i; | |
1446 | if (entry->pin < 0) | |
1447 | continue; | |
ace80ab7 | 1448 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1449 | for (;;) { |
1450 | printk("-> %d:%d", entry->apic, entry->pin); | |
1451 | if (!entry->next) | |
1452 | break; | |
1453 | entry = irq_2_pin + entry->next; | |
1454 | } | |
1455 | printk("\n"); | |
1456 | } | |
1457 | ||
1458 | printk(KERN_INFO ".................................... done.\n"); | |
1459 | ||
1460 | return; | |
1461 | } | |
1462 | ||
1463 | #if 0 | |
1464 | ||
36062448 | 1465 | static void print_APIC_bitfield(int base) |
1da177e4 LT |
1466 | { |
1467 | unsigned int v; | |
1468 | int i, j; | |
1469 | ||
1470 | if (apic_verbosity == APIC_QUIET) | |
1471 | return; | |
1472 | ||
1473 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1474 | for (i = 0; i < 8; i++) { | |
1475 | v = apic_read(base + i*0x10); | |
1476 | for (j = 0; j < 32; j++) { | |
1477 | if (v & (1<<j)) | |
1478 | printk("1"); | |
1479 | else | |
1480 | printk("0"); | |
1481 | } | |
1482 | printk("\n"); | |
1483 | } | |
1484 | } | |
1485 | ||
36062448 | 1486 | void /*__init*/ print_local_APIC(void *dummy) |
1da177e4 LT |
1487 | { |
1488 | unsigned int v, ver, maxlvt; | |
1489 | ||
1490 | if (apic_verbosity == APIC_QUIET) | |
1491 | return; | |
1492 | ||
1493 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1494 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1495 | v = apic_read(APIC_ID); |
05f2d12c JS |
1496 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
1497 | GET_APIC_ID(read_apic_id())); | |
1da177e4 LT |
1498 | v = apic_read(APIC_LVR); |
1499 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1500 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1501 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1502 | |
1503 | v = apic_read(APIC_TASKPRI); | |
1504 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1505 | ||
1506 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1507 | v = apic_read(APIC_ARBPRI); | |
1508 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1509 | v & APIC_ARBPRI_MASK); | |
1510 | v = apic_read(APIC_PROCPRI); | |
1511 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1512 | } | |
1513 | ||
1514 | v = apic_read(APIC_EOI); | |
1515 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1516 | v = apic_read(APIC_RRR); | |
1517 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1518 | v = apic_read(APIC_LDR); | |
1519 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1520 | v = apic_read(APIC_DFR); | |
1521 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1522 | v = apic_read(APIC_SPIV); | |
1523 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1524 | ||
1525 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1526 | print_APIC_bitfield(APIC_ISR); | |
1527 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1528 | print_APIC_bitfield(APIC_TMR); | |
1529 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1530 | print_APIC_bitfield(APIC_IRR); | |
1531 | ||
1532 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1533 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1534 | apic_write(APIC_ESR, 0); | |
1535 | v = apic_read(APIC_ESR); | |
1536 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1537 | } | |
1538 | ||
1539 | v = apic_read(APIC_ICR); | |
1540 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1541 | v = apic_read(APIC_ICR2); | |
1542 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1543 | ||
1544 | v = apic_read(APIC_LVTT); | |
1545 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1546 | ||
1547 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1548 | v = apic_read(APIC_LVTPC); | |
1549 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1550 | } | |
1551 | v = apic_read(APIC_LVT0); | |
1552 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1553 | v = apic_read(APIC_LVT1); | |
1554 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1555 | ||
1556 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1557 | v = apic_read(APIC_LVTERR); | |
1558 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1559 | } | |
1560 | ||
1561 | v = apic_read(APIC_TMICT); | |
1562 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1563 | v = apic_read(APIC_TMCCT); | |
1564 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1565 | v = apic_read(APIC_TDCR); | |
1566 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1567 | printk("\n"); | |
1568 | } | |
1569 | ||
36062448 | 1570 | void print_all_local_APICs(void) |
1da177e4 | 1571 | { |
15c8b6c1 | 1572 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1573 | } |
1574 | ||
1575 | void /*__init*/ print_PIC(void) | |
1576 | { | |
1da177e4 LT |
1577 | unsigned int v; |
1578 | unsigned long flags; | |
1579 | ||
1580 | if (apic_verbosity == APIC_QUIET) | |
1581 | return; | |
1582 | ||
1583 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1584 | ||
1585 | spin_lock_irqsave(&i8259A_lock, flags); | |
1586 | ||
1587 | v = inb(0xa1) << 8 | inb(0x21); | |
1588 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1589 | ||
1590 | v = inb(0xa0) << 8 | inb(0x20); | |
1591 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1592 | ||
36062448 PC |
1593 | outb(0x0b, 0xa0); |
1594 | outb(0x0b, 0x20); | |
1da177e4 | 1595 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1596 | outb(0x0a, 0xa0); |
1597 | outb(0x0a, 0x20); | |
1da177e4 LT |
1598 | |
1599 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1600 | ||
1601 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1602 | ||
1603 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1604 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1605 | } | |
1606 | ||
1607 | #endif /* 0 */ | |
1608 | ||
1609 | static void __init enable_IO_APIC(void) | |
1610 | { | |
1611 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1612 | int i8259_apic, i8259_pin; |
1613 | int i, apic; | |
1da177e4 LT |
1614 | unsigned long flags; |
1615 | ||
1616 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1617 | irq_2_pin[i].pin = -1; | |
1618 | irq_2_pin[i].next = 0; | |
1619 | } | |
1620 | if (!pirqs_enabled) | |
1621 | for (i = 0; i < MAX_PIRQS; i++) | |
1622 | pirq_entries[i] = -1; | |
1623 | ||
1624 | /* | |
1625 | * The number of IO-APIC IRQ registers (== #pins): | |
1626 | */ | |
fcfd636a | 1627 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1628 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1629 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1630 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1631 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1632 | } | |
36062448 | 1633 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1634 | int pin; |
1635 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1636 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1637 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1638 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1639 | |
1640 | ||
1641 | /* If the interrupt line is enabled and in ExtInt mode | |
1642 | * I have found the pin where the i8259 is connected. | |
1643 | */ | |
1644 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1645 | ioapic_i8259.apic = apic; | |
1646 | ioapic_i8259.pin = pin; | |
1647 | goto found_i8259; | |
1648 | } | |
1649 | } | |
1650 | } | |
1651 | found_i8259: | |
1652 | /* Look to see what if the MP table has reported the ExtINT */ | |
1653 | /* If we could not find the appropriate pin by looking at the ioapic | |
1654 | * the i8259 probably is not connected the ioapic but give the | |
1655 | * mptable a chance anyway. | |
1656 | */ | |
1657 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1658 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1659 | /* Trust the MP table if nothing is setup in the hardware */ | |
1660 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1661 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1662 | ioapic_i8259.pin = i8259_pin; | |
1663 | ioapic_i8259.apic = i8259_apic; | |
1664 | } | |
1665 | /* Complain if the MP table and the hardware disagree */ | |
1666 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1667 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1668 | { | |
1669 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1670 | } |
1671 | ||
1672 | /* | |
1673 | * Do not trust the IO-APIC being empty at bootup | |
1674 | */ | |
1675 | clear_IO_APIC(); | |
1676 | } | |
1677 | ||
1678 | /* | |
1679 | * Not an __init, needed by the reboot code | |
1680 | */ | |
1681 | void disable_IO_APIC(void) | |
1682 | { | |
1683 | /* | |
1684 | * Clear the IO-APIC before rebooting: | |
1685 | */ | |
1686 | clear_IO_APIC(); | |
1687 | ||
650927ef | 1688 | /* |
0b968d23 | 1689 | * If the i8259 is routed through an IOAPIC |
650927ef | 1690 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1691 | * so legacy interrupts can be delivered. |
650927ef | 1692 | */ |
fcfd636a | 1693 | if (ioapic_i8259.pin != -1) { |
650927ef | 1694 | struct IO_APIC_route_entry entry; |
650927ef EB |
1695 | |
1696 | memset(&entry, 0, sizeof(entry)); | |
1697 | entry.mask = 0; /* Enabled */ | |
1698 | entry.trigger = 0; /* Edge */ | |
1699 | entry.irr = 0; | |
1700 | entry.polarity = 0; /* High */ | |
1701 | entry.delivery_status = 0; | |
1702 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1703 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1704 | entry.vector = 0; |
76865c3f | 1705 | entry.dest.physical.physical_dest = |
05f2d12c | 1706 | GET_APIC_ID(read_apic_id()); |
650927ef EB |
1707 | |
1708 | /* | |
1709 | * Add it to the IO-APIC irq-routing table: | |
1710 | */ | |
cf4c6a2f | 1711 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1712 | } |
fcfd636a | 1713 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1714 | } |
1715 | ||
1716 | /* | |
1717 | * function to set the IO-APIC physical IDs based on the | |
1718 | * values stored in the MPC table. | |
1719 | * | |
1720 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1721 | */ | |
1722 | ||
1da177e4 LT |
1723 | static void __init setup_ioapic_ids_from_mpc(void) |
1724 | { | |
1725 | union IO_APIC_reg_00 reg_00; | |
1726 | physid_mask_t phys_id_present_map; | |
1727 | int apic; | |
1728 | int i; | |
1729 | unsigned char old_id; | |
1730 | unsigned long flags; | |
1731 | ||
d49c4288 YL |
1732 | #ifdef CONFIG_X86_NUMAQ |
1733 | if (found_numaq) | |
1734 | return; | |
1735 | #endif | |
1736 | ||
ca05fea6 NP |
1737 | /* |
1738 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1739 | * no meaning without the serial APIC bus. | |
1740 | */ | |
7c5c1e42 SL |
1741 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1742 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1743 | return; |
1da177e4 LT |
1744 | /* |
1745 | * This is broken; anything with a real cpu count has to | |
1746 | * circumvent this idiocy regardless. | |
1747 | */ | |
1748 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1749 | ||
1750 | /* | |
1751 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1752 | */ | |
1753 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1754 | ||
1755 | /* Read the register 0 value */ | |
1756 | spin_lock_irqsave(&ioapic_lock, flags); | |
1757 | reg_00.raw = io_apic_read(apic, 0); | |
1758 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1759 | |
ec2cd0a2 | 1760 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1761 | |
ec2cd0a2 | 1762 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1763 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1764 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1765 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1766 | reg_00.bits.ID); | |
ec2cd0a2 | 1767 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1768 | } |
1769 | ||
1da177e4 LT |
1770 | /* |
1771 | * Sanity check, is the ID really free? Every APIC in a | |
1772 | * system must have a unique ID or we get lots of nice | |
1773 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1774 | */ | |
1775 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1776 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1777 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1778 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1779 | for (i = 0; i < get_physical_broadcast(); i++) |
1780 | if (!physid_isset(i, phys_id_present_map)) | |
1781 | break; | |
1782 | if (i >= get_physical_broadcast()) | |
1783 | panic("Max APIC ID exceeded!\n"); | |
1784 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1785 | i); | |
1786 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1787 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1788 | } else { |
1789 | physid_mask_t tmp; | |
ec2cd0a2 | 1790 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1791 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1792 | "phys_id_present_map\n", | |
ec2cd0a2 | 1793 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1794 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1795 | } | |
1796 | ||
1797 | ||
1798 | /* | |
1799 | * We need to adjust the IRQ routing table | |
1800 | * if the ID changed. | |
1801 | */ | |
ec2cd0a2 | 1802 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1803 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1804 | if (mp_irqs[i].mp_dstapic == old_id) |
1805 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1806 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1807 | |
1808 | /* | |
1809 | * Read the right value from the MPC table and | |
1810 | * write it into the ID register. | |
36062448 | 1811 | */ |
1da177e4 LT |
1812 | apic_printk(APIC_VERBOSE, KERN_INFO |
1813 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1814 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1815 | |
ec2cd0a2 | 1816 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1817 | spin_lock_irqsave(&ioapic_lock, flags); |
1818 | io_apic_write(apic, 0, reg_00.raw); | |
1819 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1820 | ||
1821 | /* | |
1822 | * Sanity check | |
1823 | */ | |
1824 | spin_lock_irqsave(&ioapic_lock, flags); | |
1825 | reg_00.raw = io_apic_read(apic, 0); | |
1826 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1827 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1828 | printk("could not set ID!\n"); |
1829 | else | |
1830 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1831 | } | |
1832 | } | |
1da177e4 | 1833 | |
7ce0bcfd | 1834 | int no_timer_check __initdata; |
8542b200 ZA |
1835 | |
1836 | static int __init notimercheck(char *s) | |
1837 | { | |
1838 | no_timer_check = 1; | |
1839 | return 1; | |
1840 | } | |
1841 | __setup("no_timer_check", notimercheck); | |
1842 | ||
1da177e4 LT |
1843 | /* |
1844 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1845 | * about the timer IRQ. We do the following to work around the situation: | |
1846 | * | |
1847 | * - timer IRQ defaults to IO-APIC IRQ | |
1848 | * - if this function detects that timer IRQs are defunct, then we fall | |
1849 | * back to ISA timer IRQs | |
1850 | */ | |
f0a7a5c9 | 1851 | static int __init timer_irq_works(void) |
1da177e4 LT |
1852 | { |
1853 | unsigned long t1 = jiffies; | |
4aae0702 | 1854 | unsigned long flags; |
1da177e4 | 1855 | |
8542b200 ZA |
1856 | if (no_timer_check) |
1857 | return 1; | |
1858 | ||
4aae0702 | 1859 | local_save_flags(flags); |
1da177e4 LT |
1860 | local_irq_enable(); |
1861 | /* Let ten ticks pass... */ | |
1862 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1863 | local_irq_restore(flags); |
1da177e4 LT |
1864 | |
1865 | /* | |
1866 | * Expect a few ticks at least, to be sure some possible | |
1867 | * glue logic does not lock up after one or two first | |
1868 | * ticks in a non-ExtINT mode. Also the local APIC | |
1869 | * might have cached one ExtINT interrupt. Finally, at | |
1870 | * least one tick may be lost due to delays. | |
1871 | */ | |
1d16b53e | 1872 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1873 | return 1; |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | /* | |
1879 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1880 | * number of pending IRQ events unhandled. These cases are very rare, | |
1881 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1882 | * better to do it this way as thus we do not have to be aware of | |
1883 | * 'pending' interrupts in the IRQ path, except at this point. | |
1884 | */ | |
1885 | /* | |
1886 | * Edge triggered needs to resend any interrupt | |
1887 | * that was delayed but this is now handled in the device | |
1888 | * independent code. | |
1889 | */ | |
1890 | ||
1891 | /* | |
f5b9ed7a IM |
1892 | * Startup quirk: |
1893 | * | |
1da177e4 LT |
1894 | * Starting up a edge-triggered IO-APIC interrupt is |
1895 | * nasty - we need to make sure that we get the edge. | |
1896 | * If it is already asserted for some reason, we need | |
1897 | * return 1 to indicate that is was pending. | |
1898 | * | |
1899 | * This is not complete - we should be able to fake | |
1900 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1901 | * |
1902 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1903 | */ |
f5b9ed7a | 1904 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1905 | { |
1906 | int was_pending = 0; | |
1907 | unsigned long flags; | |
1908 | ||
1909 | spin_lock_irqsave(&ioapic_lock, flags); | |
1910 | if (irq < 16) { | |
1911 | disable_8259A_irq(irq); | |
1912 | if (i8259A_irq_pending(irq)) | |
1913 | was_pending = 1; | |
1914 | } | |
1915 | __unmask_IO_APIC_irq(irq); | |
1916 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1917 | ||
1918 | return was_pending; | |
1919 | } | |
1920 | ||
f5b9ed7a | 1921 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1922 | { |
ace80ab7 | 1923 | move_native_irq(irq); |
1da177e4 LT |
1924 | ack_APIC_irq(); |
1925 | } | |
1926 | ||
f5b9ed7a | 1927 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1928 | { |
1929 | unsigned long v; | |
1930 | int i; | |
1931 | ||
ace80ab7 | 1932 | move_native_irq(irq); |
1da177e4 LT |
1933 | /* |
1934 | * It appears there is an erratum which affects at least version 0x11 | |
1935 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1936 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1937 | * erroneously delivered as edge-triggered one but the respective IRR | |
1938 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1939 | * message but it will never arrive and further interrupts are blocked | |
1940 | * from the source. The exact reason is so far unknown, but the | |
1941 | * phenomenon was observed when two consecutive interrupt requests | |
1942 | * from a given source get delivered to the same CPU and the source is | |
1943 | * temporarily disabled in between. | |
1944 | * | |
1945 | * A workaround is to simulate an EOI message manually. We achieve it | |
1946 | * by setting the trigger mode to edge and then to level when the edge | |
1947 | * trigger mode gets detected in the TMR of a local APIC for a | |
1948 | * level-triggered interrupt. We mask the source for the time of the | |
1949 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1950 | * The idea is from Manfred Spraul. --macro | |
1951 | */ | |
b940d22d | 1952 | i = irq_vector[irq]; |
1da177e4 LT |
1953 | |
1954 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1955 | ||
1956 | ack_APIC_irq(); | |
1957 | ||
1958 | if (!(v & (1 << (i & 0x1f)))) { | |
1959 | atomic_inc(&irq_mis_count); | |
1960 | spin_lock(&ioapic_lock); | |
1961 | __mask_and_edge_IO_APIC_irq(irq); | |
1962 | __unmask_and_level_IO_APIC_irq(irq); | |
1963 | spin_unlock(&ioapic_lock); | |
1964 | } | |
1965 | } | |
1966 | ||
ace80ab7 | 1967 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1968 | { |
b940d22d | 1969 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1970 | |
1971 | return 1; | |
1972 | } | |
1973 | ||
f5b9ed7a IM |
1974 | static struct irq_chip ioapic_chip __read_mostly = { |
1975 | .name = "IO-APIC", | |
ace80ab7 EB |
1976 | .startup = startup_ioapic_irq, |
1977 | .mask = mask_IO_APIC_irq, | |
1978 | .unmask = unmask_IO_APIC_irq, | |
1979 | .ack = ack_ioapic_irq, | |
1980 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 1981 | #ifdef CONFIG_SMP |
ace80ab7 | 1982 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1983 | #endif |
ace80ab7 | 1984 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1985 | }; |
1986 | ||
1da177e4 LT |
1987 | |
1988 | static inline void init_IO_APIC_traps(void) | |
1989 | { | |
1990 | int irq; | |
1991 | ||
1992 | /* | |
1993 | * NOTE! The local APIC isn't very good at handling | |
1994 | * multiple interrupts at the same interrupt level. | |
1995 | * As the interrupt level is determined by taking the | |
1996 | * vector number and shifting that right by 4, we | |
1997 | * want to spread these out a bit so that they don't | |
1998 | * all fall in the same interrupt level. | |
1999 | * | |
2000 | * Also, we've got to be careful not to trash gate | |
2001 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2002 | */ | |
2003 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
addfc66b | 2004 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
2005 | /* |
2006 | * Hmm.. We don't have an entry for this, | |
2007 | * so default to an old-fashioned 8259 | |
2008 | * interrupt if we can.. | |
2009 | */ | |
2010 | if (irq < 16) | |
2011 | make_8259A_irq(irq); | |
2012 | else | |
2013 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2014 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2015 | } |
2016 | } | |
2017 | } | |
2018 | ||
f5b9ed7a IM |
2019 | /* |
2020 | * The local APIC irq-chip implementation: | |
2021 | */ | |
1da177e4 | 2022 | |
c88ac1df | 2023 | static void ack_lapic_irq(unsigned int irq) |
f5b9ed7a IM |
2024 | { |
2025 | ack_APIC_irq(); | |
1da177e4 LT |
2026 | } |
2027 | ||
36062448 | 2028 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2029 | { |
2030 | unsigned long v; | |
2031 | ||
2032 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2033 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2034 | } |
2035 | ||
36062448 | 2036 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2037 | { |
f5b9ed7a | 2038 | unsigned long v; |
1da177e4 | 2039 | |
f5b9ed7a | 2040 | v = apic_read(APIC_LVT0); |
593f4a78 | 2041 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2042 | } |
1da177e4 | 2043 | |
f5b9ed7a | 2044 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2045 | .name = "local-APIC", |
f5b9ed7a IM |
2046 | .mask = mask_lapic_irq, |
2047 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2048 | .ack = ack_lapic_irq, |
1da177e4 LT |
2049 | }; |
2050 | ||
c88ac1df MR |
2051 | static void lapic_register_intr(int irq, int vector) |
2052 | { | |
2053 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
2054 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, | |
2055 | "edge"); | |
2056 | set_intr_gate(vector, interrupt[irq]); | |
2057 | } | |
2058 | ||
e9427101 | 2059 | static void __init setup_nmi(void) |
1da177e4 LT |
2060 | { |
2061 | /* | |
36062448 | 2062 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2063 | * We put the 8259A master into AEOI mode and |
2064 | * unmask on all local APICs LVT0 as NMI. | |
2065 | * | |
2066 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2067 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2068 | * the NMI handler or the timer interrupt. | |
36062448 | 2069 | */ |
1da177e4 LT |
2070 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2071 | ||
e9427101 | 2072 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2073 | |
2074 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2075 | } | |
2076 | ||
2077 | /* | |
2078 | * This looks a bit hackish but it's about the only one way of sending | |
2079 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2080 | * not support the ExtINT mode, unfortunately. We need to send these | |
2081 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2082 | * 8259A interrupt line asserted until INTA. --macro | |
2083 | */ | |
28acf285 | 2084 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2085 | { |
fcfd636a | 2086 | int apic, pin, i; |
1da177e4 LT |
2087 | struct IO_APIC_route_entry entry0, entry1; |
2088 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2089 | |
fcfd636a | 2090 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2091 | if (pin == -1) { |
2092 | WARN_ON_ONCE(1); | |
2093 | return; | |
2094 | } | |
fcfd636a | 2095 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2096 | if (apic == -1) { |
2097 | WARN_ON_ONCE(1); | |
1da177e4 | 2098 | return; |
956fb531 | 2099 | } |
1da177e4 | 2100 | |
cf4c6a2f | 2101 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2102 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2103 | |
2104 | memset(&entry1, 0, sizeof(entry1)); | |
2105 | ||
2106 | entry1.dest_mode = 0; /* physical delivery */ | |
2107 | entry1.mask = 0; /* unmask IRQ now */ | |
2108 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2109 | entry1.delivery_mode = dest_ExtINT; | |
2110 | entry1.polarity = entry0.polarity; | |
2111 | entry1.trigger = 0; | |
2112 | entry1.vector = 0; | |
2113 | ||
cf4c6a2f | 2114 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2115 | |
2116 | save_control = CMOS_READ(RTC_CONTROL); | |
2117 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2118 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2119 | RTC_FREQ_SELECT); | |
2120 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2121 | ||
2122 | i = 100; | |
2123 | while (i-- > 0) { | |
2124 | mdelay(10); | |
2125 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2126 | i -= 10; | |
2127 | } | |
2128 | ||
2129 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2130 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2131 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2132 | |
cf4c6a2f | 2133 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2134 | } |
2135 | ||
2136 | /* | |
2137 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2138 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2139 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2140 | * fanatically on his truly buggy board. | |
2141 | */ | |
8542b200 | 2142 | static inline void __init check_timer(void) |
1da177e4 | 2143 | { |
fcfd636a | 2144 | int apic1, pin1, apic2, pin2; |
691874fa | 2145 | int no_pin1 = 0; |
1da177e4 | 2146 | int vector; |
6e908947 | 2147 | unsigned int ver; |
4aae0702 IM |
2148 | unsigned long flags; |
2149 | ||
2150 | local_irq_save(flags); | |
d4d25dec | 2151 | |
6e908947 IM |
2152 | ver = apic_read(APIC_LVR); |
2153 | ver = GET_APIC_VERSION(ver); | |
2154 | ||
1da177e4 LT |
2155 | /* |
2156 | * get/set the timer IRQ vector: | |
2157 | */ | |
2158 | disable_8259A_irq(0); | |
2159 | vector = assign_irq_vector(0); | |
2160 | set_intr_gate(vector, interrupt[0]); | |
2161 | ||
2162 | /* | |
d11d5794 MR |
2163 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2164 | * wire has to be disabled in the local APIC. Also | |
2165 | * timer interrupts need to be acknowledged manually in | |
2166 | * the 8259A for the i82489DX when using the NMI | |
2167 | * watchdog as that APIC treats NMIs as level-triggered. | |
2168 | * The AEOI mode will finish them in the 8259A | |
2169 | * automatically. | |
1da177e4 | 2170 | */ |
593f4a78 | 2171 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2172 | init_8259A(1); |
d11d5794 | 2173 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2174 | |
fcfd636a EB |
2175 | pin1 = find_isa_irq_pin(0, mp_INT); |
2176 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2177 | pin2 = ioapic_i8259.pin; | |
2178 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2179 | |
fcfd636a EB |
2180 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2181 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 | 2182 | |
691874fa MR |
2183 | /* |
2184 | * Some BIOS writers are clueless and report the ExtINTA | |
2185 | * I/O APIC input from the cascaded 8259A as the timer | |
2186 | * interrupt input. So just in case, if only one pin | |
2187 | * was found above, try it both directly and through the | |
2188 | * 8259A. | |
2189 | */ | |
2190 | if (pin1 == -1) { | |
2191 | pin1 = pin2; | |
2192 | apic1 = apic2; | |
2193 | no_pin1 = 1; | |
2194 | } else if (pin2 == -1) { | |
2195 | pin2 = pin1; | |
2196 | apic2 = apic1; | |
2197 | } | |
2198 | ||
1da177e4 LT |
2199 | if (pin1 != -1) { |
2200 | /* | |
2201 | * Ok, does IRQ0 through the IOAPIC work? | |
2202 | */ | |
691874fa MR |
2203 | if (no_pin1) { |
2204 | add_pin_to_irq(0, apic1, pin1); | |
2205 | setup_timer_IRQ0_pin(apic1, pin1, vector); | |
2206 | } | |
1da177e4 LT |
2207 | unmask_IO_APIC_irq(0); |
2208 | if (timer_irq_works()) { | |
2209 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2210 | setup_nmi(); |
2211 | enable_8259A_irq(0); | |
1da177e4 | 2212 | } |
66759a01 CE |
2213 | if (disable_timer_pin_1 > 0) |
2214 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2215 | goto out; |
1da177e4 | 2216 | } |
fcfd636a | 2217 | clear_IO_APIC_pin(apic1, pin1); |
691874fa MR |
2218 | if (!no_pin1) |
2219 | printk(KERN_ERR "..MP-BIOS bug: " | |
2220 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2221 | |
691874fa MR |
2222 | printk(KERN_INFO "...trying to set up timer (IRQ0) " |
2223 | "through the 8259A ... "); | |
1da177e4 LT |
2224 | printk("\n..... (found pin %d) ...", pin2); |
2225 | /* | |
2226 | * legacy devices should be connected to IO APIC #0 | |
2227 | */ | |
691874fa | 2228 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 2229 | setup_timer_IRQ0_pin(apic2, pin2, vector); |
24742ece | 2230 | unmask_IO_APIC_irq(0); |
ecd29476 | 2231 | enable_8259A_irq(0); |
1da177e4 LT |
2232 | if (timer_irq_works()) { |
2233 | printk("works.\n"); | |
35542c5e | 2234 | timer_through_8259 = 1; |
1da177e4 | 2235 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2236 | disable_8259A_irq(0); |
1da177e4 | 2237 | setup_nmi(); |
60134ebe | 2238 | enable_8259A_irq(0); |
1da177e4 | 2239 | } |
4aae0702 | 2240 | goto out; |
1da177e4 LT |
2241 | } |
2242 | /* | |
2243 | * Cleanup, just in case ... | |
2244 | */ | |
ecd29476 | 2245 | disable_8259A_irq(0); |
fcfd636a | 2246 | clear_IO_APIC_pin(apic2, pin2); |
691874fa | 2247 | printk(" failed.\n"); |
1da177e4 | 2248 | } |
1da177e4 LT |
2249 | |
2250 | if (nmi_watchdog == NMI_IO_APIC) { | |
2251 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2252 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2253 | } |
d11d5794 | 2254 | timer_ack = 0; |
1da177e4 LT |
2255 | |
2256 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2257 | ||
c88ac1df | 2258 | lapic_register_intr(0, vector); |
593f4a78 | 2259 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1da177e4 LT |
2260 | enable_8259A_irq(0); |
2261 | ||
2262 | if (timer_irq_works()) { | |
2263 | printk(" works.\n"); | |
4aae0702 | 2264 | goto out; |
1da177e4 | 2265 | } |
e67465f1 | 2266 | disable_8259A_irq(0); |
593f4a78 | 2267 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
1da177e4 LT |
2268 | printk(" failed.\n"); |
2269 | ||
2270 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2271 | ||
1da177e4 LT |
2272 | init_8259A(0); |
2273 | make_8259A_irq(0); | |
593f4a78 | 2274 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2275 | |
2276 | unlock_ExtINT_logic(); | |
2277 | ||
2278 | if (timer_irq_works()) { | |
2279 | printk(" works.\n"); | |
4aae0702 | 2280 | goto out; |
1da177e4 LT |
2281 | } |
2282 | printk(" failed :(.\n"); | |
2283 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2284 | "report. Then try booting with the 'noapic' option"); | |
4aae0702 IM |
2285 | out: |
2286 | local_irq_restore(flags); | |
1da177e4 LT |
2287 | } |
2288 | ||
2289 | /* | |
af174783 MR |
2290 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2291 | * to devices. However there may be an I/O APIC pin available for | |
2292 | * this interrupt regardless. The pin may be left unconnected, but | |
2293 | * typically it will be reused as an ExtINT cascade interrupt for | |
2294 | * the master 8259A. In the MPS case such a pin will normally be | |
2295 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2296 | * there is no provision for ExtINT interrupts, and in the absence | |
2297 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2298 | * interrupt, that is edge-triggered and unmasked by default. We | |
2299 | * used to do this, but it caused problems on some systems because | |
2300 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2301 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2302 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2303 | * the I/O APIC in all cases now. No actual device should request | |
2304 | * it anyway. --macro | |
1da177e4 LT |
2305 | */ |
2306 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2307 | ||
2308 | void __init setup_IO_APIC(void) | |
2309 | { | |
dbeb2be2 RR |
2310 | int i; |
2311 | ||
2312 | /* Reserve all the system vectors. */ | |
305b92a2 | 2313 | for (i = first_system_vector; i < NR_VECTORS; i++) |
dbeb2be2 RR |
2314 | set_bit(i, used_vectors); |
2315 | ||
1da177e4 LT |
2316 | enable_IO_APIC(); |
2317 | ||
af174783 | 2318 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
2319 | |
2320 | printk("ENABLING IO-APIC IRQs\n"); | |
2321 | ||
2322 | /* | |
2323 | * Set up IO-APIC IRQ routing. | |
2324 | */ | |
2325 | if (!acpi_ioapic) | |
2326 | setup_ioapic_ids_from_mpc(); | |
2327 | sync_Arb_IDs(); | |
2328 | setup_IO_APIC_irqs(); | |
2329 | init_IO_APIC_traps(); | |
1e4c85f9 | 2330 | check_timer(); |
1da177e4 LT |
2331 | if (!acpi_ioapic) |
2332 | print_IO_APIC(); | |
2333 | } | |
2334 | ||
2335 | /* | |
2336 | * Called after all the initialization is done. If we didnt find any | |
2337 | * APIC bugs then we can allow the modify fast path | |
2338 | */ | |
36062448 | 2339 | |
1da177e4 LT |
2340 | static int __init io_apic_bug_finalize(void) |
2341 | { | |
36062448 | 2342 | if (sis_apic_bug == -1) |
1da177e4 LT |
2343 | sis_apic_bug = 0; |
2344 | return 0; | |
2345 | } | |
2346 | ||
2347 | late_initcall(io_apic_bug_finalize); | |
2348 | ||
2349 | struct sysfs_ioapic_data { | |
2350 | struct sys_device dev; | |
2351 | struct IO_APIC_route_entry entry[0]; | |
2352 | }; | |
36062448 | 2353 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2354 | |
438510f6 | 2355 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2356 | { |
2357 | struct IO_APIC_route_entry *entry; | |
2358 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2359 | int i; |
36062448 | 2360 | |
1da177e4 LT |
2361 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2362 | entry = data->entry; | |
36062448 | 2363 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2364 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2365 | |
2366 | return 0; | |
2367 | } | |
2368 | ||
2369 | static int ioapic_resume(struct sys_device *dev) | |
2370 | { | |
2371 | struct IO_APIC_route_entry *entry; | |
2372 | struct sysfs_ioapic_data *data; | |
2373 | unsigned long flags; | |
2374 | union IO_APIC_reg_00 reg_00; | |
2375 | int i; | |
36062448 | 2376 | |
1da177e4 LT |
2377 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2378 | entry = data->entry; | |
2379 | ||
2380 | spin_lock_irqsave(&ioapic_lock, flags); | |
2381 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2382 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2383 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2384 | io_apic_write(dev->id, 0, reg_00.raw); |
2385 | } | |
1da177e4 | 2386 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2387 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2388 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2389 | |
2390 | return 0; | |
2391 | } | |
2392 | ||
2393 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2394 | .name = "ioapic", |
1da177e4 LT |
2395 | .suspend = ioapic_suspend, |
2396 | .resume = ioapic_resume, | |
2397 | }; | |
2398 | ||
2399 | static int __init ioapic_init_sysfs(void) | |
2400 | { | |
36062448 | 2401 | struct sys_device *dev; |
1da177e4 LT |
2402 | int i, size, error = 0; |
2403 | ||
2404 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2405 | if (error) | |
2406 | return error; | |
2407 | ||
36062448 PC |
2408 | for (i = 0; i < nr_ioapics; i++) { |
2409 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2410 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2411 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2412 | if (!mp_ioapic_data[i]) { |
2413 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2414 | continue; | |
2415 | } | |
1da177e4 | 2416 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2417 | dev->id = i; |
1da177e4 LT |
2418 | dev->cls = &ioapic_sysdev_class; |
2419 | error = sysdev_register(dev); | |
2420 | if (error) { | |
2421 | kfree(mp_ioapic_data[i]); | |
2422 | mp_ioapic_data[i] = NULL; | |
2423 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2424 | continue; | |
2425 | } | |
2426 | } | |
2427 | ||
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | device_initcall(ioapic_init_sysfs); | |
2432 | ||
3fc471ed | 2433 | /* |
95d77884 | 2434 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2435 | */ |
2436 | int create_irq(void) | |
2437 | { | |
ace80ab7 | 2438 | /* Allocate an unused irq */ |
306a22c2 | 2439 | int irq, new, vector = 0; |
3fc471ed | 2440 | unsigned long flags; |
3fc471ed | 2441 | |
ace80ab7 EB |
2442 | irq = -ENOSPC; |
2443 | spin_lock_irqsave(&vector_lock, flags); | |
2444 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2445 | if (platform_legacy_irq(new)) | |
2446 | continue; | |
2447 | if (irq_vector[new] != 0) | |
2448 | continue; | |
2449 | vector = __assign_irq_vector(new); | |
2450 | if (likely(vector > 0)) | |
2451 | irq = new; | |
2452 | break; | |
2453 | } | |
2454 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2455 | |
ace80ab7 | 2456 | if (irq >= 0) { |
3fc471ed | 2457 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2458 | dynamic_irq_init(irq); |
2459 | } | |
2460 | return irq; | |
2461 | } | |
2462 | ||
2463 | void destroy_irq(unsigned int irq) | |
2464 | { | |
2465 | unsigned long flags; | |
3fc471ed EB |
2466 | |
2467 | dynamic_irq_cleanup(irq); | |
2468 | ||
2469 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2470 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2471 | irq_vector[irq] = 0; |
2472 | spin_unlock_irqrestore(&vector_lock, flags); | |
2473 | } | |
3fc471ed | 2474 | |
2d3fcc1c | 2475 | /* |
27b46d76 | 2476 | * MSI message composition |
2d3fcc1c EB |
2477 | */ |
2478 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2479 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2480 | { |
2d3fcc1c EB |
2481 | int vector; |
2482 | unsigned dest; | |
2483 | ||
2484 | vector = assign_irq_vector(irq); | |
2485 | if (vector >= 0) { | |
2486 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2487 | ||
2488 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2489 | msg->address_lo = | |
2490 | MSI_ADDR_BASE_LO | | |
2491 | ((INT_DEST_MODE == 0) ? | |
36062448 | 2492 | MSI_ADDR_DEST_MODE_PHYSICAL: |
2d3fcc1c EB |
2493 | MSI_ADDR_DEST_MODE_LOGICAL) | |
2494 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2495 | MSI_ADDR_REDIRECTION_CPU: | |
2496 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2497 | MSI_ADDR_DEST_ID(dest); | |
2498 | ||
2499 | msg->data = | |
2500 | MSI_DATA_TRIGGER_EDGE | | |
2501 | MSI_DATA_LEVEL_ASSERT | | |
2502 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
36062448 | 2503 | MSI_DATA_DELIVERY_FIXED: |
2d3fcc1c EB |
2504 | MSI_DATA_DELIVERY_LOWPRI) | |
2505 | MSI_DATA_VECTOR(vector); | |
2506 | } | |
2507 | return vector; | |
2508 | } | |
2509 | ||
3b7d1921 EB |
2510 | #ifdef CONFIG_SMP |
2511 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2512 | { |
3b7d1921 EB |
2513 | struct msi_msg msg; |
2514 | unsigned int dest; | |
2515 | cpumask_t tmp; | |
2d3fcc1c | 2516 | int vector; |
3b7d1921 EB |
2517 | |
2518 | cpus_and(tmp, mask, cpu_online_map); | |
2519 | if (cpus_empty(tmp)) | |
2520 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2521 | |
2522 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2523 | if (vector < 0) |
2524 | return; | |
2d3fcc1c | 2525 | |
3b7d1921 EB |
2526 | dest = cpu_mask_to_apicid(mask); |
2527 | ||
2528 | read_msi_msg(irq, &msg); | |
2529 | ||
2530 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2531 | msg.data |= MSI_DATA_VECTOR(vector); | |
2532 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2533 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2534 | ||
2535 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2536 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2537 | } |
3b7d1921 | 2538 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2539 | |
3b7d1921 EB |
2540 | /* |
2541 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2542 | * which implement the MSI or MSI-X Capability Structure. | |
2543 | */ | |
2544 | static struct irq_chip msi_chip = { | |
2545 | .name = "PCI-MSI", | |
2546 | .unmask = unmask_msi_irq, | |
2547 | .mask = mask_msi_irq, | |
2548 | .ack = ack_ioapic_irq, | |
2549 | #ifdef CONFIG_SMP | |
2550 | .set_affinity = set_msi_irq_affinity, | |
2551 | #endif | |
2552 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2553 | }; |
2554 | ||
f7feaca7 | 2555 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2556 | { |
2557 | struct msi_msg msg; | |
f7feaca7 EB |
2558 | int irq, ret; |
2559 | irq = create_irq(); | |
2560 | if (irq < 0) | |
2561 | return irq; | |
2562 | ||
3b7d1921 | 2563 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2564 | if (ret < 0) { |
2565 | destroy_irq(irq); | |
3b7d1921 | 2566 | return ret; |
f7feaca7 | 2567 | } |
3b7d1921 | 2568 | |
7fe3730d | 2569 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2570 | write_msi_msg(irq, &msg); |
2571 | ||
a460e745 IM |
2572 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2573 | "edge"); | |
3b7d1921 | 2574 | |
7fe3730d | 2575 | return 0; |
3b7d1921 EB |
2576 | } |
2577 | ||
2578 | void arch_teardown_msi_irq(unsigned int irq) | |
2579 | { | |
f7feaca7 | 2580 | destroy_irq(irq); |
3b7d1921 EB |
2581 | } |
2582 | ||
2d3fcc1c EB |
2583 | #endif /* CONFIG_PCI_MSI */ |
2584 | ||
8b955b0d EB |
2585 | /* |
2586 | * Hypertransport interrupt support | |
2587 | */ | |
2588 | #ifdef CONFIG_HT_IRQ | |
2589 | ||
2590 | #ifdef CONFIG_SMP | |
2591 | ||
2592 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2593 | { | |
ec68307c EB |
2594 | struct ht_irq_msg msg; |
2595 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2596 | |
ec68307c EB |
2597 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2598 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2599 | |
ec68307c EB |
2600 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2601 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2602 | |
ec68307c | 2603 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2604 | } |
2605 | ||
2606 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2607 | { | |
2608 | unsigned int dest; | |
2609 | cpumask_t tmp; | |
2610 | ||
2611 | cpus_and(tmp, mask, cpu_online_map); | |
2612 | if (cpus_empty(tmp)) | |
2613 | tmp = TARGET_CPUS; | |
2614 | ||
2615 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2616 | ||
2617 | dest = cpu_mask_to_apicid(mask); | |
2618 | ||
2619 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2620 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2621 | } |
2622 | #endif | |
2623 | ||
c37e108d | 2624 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2625 | .name = "PCI-HT", |
2626 | .mask = mask_ht_irq, | |
2627 | .unmask = unmask_ht_irq, | |
2628 | .ack = ack_ioapic_irq, | |
2629 | #ifdef CONFIG_SMP | |
2630 | .set_affinity = set_ht_irq_affinity, | |
2631 | #endif | |
2632 | .retrigger = ioapic_retrigger_irq, | |
2633 | }; | |
2634 | ||
2635 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2636 | { | |
2637 | int vector; | |
2638 | ||
2639 | vector = assign_irq_vector(irq); | |
2640 | if (vector >= 0) { | |
ec68307c | 2641 | struct ht_irq_msg msg; |
8b955b0d EB |
2642 | unsigned dest; |
2643 | cpumask_t tmp; | |
2644 | ||
2645 | cpus_clear(tmp); | |
2646 | cpu_set(vector >> 8, tmp); | |
2647 | dest = cpu_mask_to_apicid(tmp); | |
2648 | ||
ec68307c | 2649 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2650 | |
ec68307c EB |
2651 | msg.address_lo = |
2652 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2653 | HT_IRQ_LOW_DEST_ID(dest) | |
2654 | HT_IRQ_LOW_VECTOR(vector) | | |
2655 | ((INT_DEST_MODE == 0) ? | |
2656 | HT_IRQ_LOW_DM_PHYSICAL : | |
2657 | HT_IRQ_LOW_DM_LOGICAL) | | |
2658 | HT_IRQ_LOW_RQEOI_EDGE | | |
2659 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2660 | HT_IRQ_LOW_MT_FIXED : | |
2661 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2662 | HT_IRQ_LOW_IRQ_MASKED; | |
2663 | ||
ec68307c | 2664 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2665 | |
a460e745 IM |
2666 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2667 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2668 | } |
2669 | return vector; | |
2670 | } | |
2671 | #endif /* CONFIG_HT_IRQ */ | |
2672 | ||
1da177e4 | 2673 | /* -------------------------------------------------------------------------- |
36062448 | 2674 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2675 | -------------------------------------------------------------------------- */ |
2676 | ||
888ba6c6 | 2677 | #ifdef CONFIG_ACPI |
1da177e4 | 2678 | |
36062448 | 2679 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2680 | { |
2681 | union IO_APIC_reg_00 reg_00; | |
2682 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2683 | physid_mask_t tmp; | |
2684 | unsigned long flags; | |
2685 | int i = 0; | |
2686 | ||
2687 | /* | |
36062448 PC |
2688 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2689 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2690 | * supports up to 16 on one shared APIC bus. |
36062448 | 2691 | * |
1da177e4 LT |
2692 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2693 | * advantage of new APIC bus architecture. | |
2694 | */ | |
2695 | ||
2696 | if (physids_empty(apic_id_map)) | |
2697 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2698 | ||
2699 | spin_lock_irqsave(&ioapic_lock, flags); | |
2700 | reg_00.raw = io_apic_read(ioapic, 0); | |
2701 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2702 | ||
2703 | if (apic_id >= get_physical_broadcast()) { | |
2704 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2705 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2706 | apic_id = reg_00.bits.ID; | |
2707 | } | |
2708 | ||
2709 | /* | |
36062448 | 2710 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2711 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2712 | */ | |
2713 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2714 | ||
2715 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2716 | if (!check_apicid_used(apic_id_map, i)) | |
2717 | break; | |
2718 | } | |
2719 | ||
2720 | if (i == get_physical_broadcast()) | |
2721 | panic("Max apic_id exceeded!\n"); | |
2722 | ||
2723 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2724 | "trying %d\n", ioapic, apic_id, i); | |
2725 | ||
2726 | apic_id = i; | |
36062448 | 2727 | } |
1da177e4 LT |
2728 | |
2729 | tmp = apicid_to_cpu_present(apic_id); | |
2730 | physids_or(apic_id_map, apic_id_map, tmp); | |
2731 | ||
2732 | if (reg_00.bits.ID != apic_id) { | |
2733 | reg_00.bits.ID = apic_id; | |
2734 | ||
2735 | spin_lock_irqsave(&ioapic_lock, flags); | |
2736 | io_apic_write(ioapic, 0, reg_00.raw); | |
2737 | reg_00.raw = io_apic_read(ioapic, 0); | |
2738 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2739 | ||
2740 | /* Sanity check */ | |
6070f9ec AD |
2741 | if (reg_00.bits.ID != apic_id) { |
2742 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2743 | return -1; | |
2744 | } | |
1da177e4 LT |
2745 | } |
2746 | ||
2747 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2748 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2749 | ||
2750 | return apic_id; | |
2751 | } | |
2752 | ||
2753 | ||
36062448 | 2754 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2755 | { |
2756 | union IO_APIC_reg_01 reg_01; | |
2757 | unsigned long flags; | |
2758 | ||
2759 | spin_lock_irqsave(&ioapic_lock, flags); | |
2760 | reg_01.raw = io_apic_read(ioapic, 1); | |
2761 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2762 | ||
2763 | return reg_01.bits.version; | |
2764 | } | |
2765 | ||
2766 | ||
36062448 | 2767 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2768 | { |
2769 | union IO_APIC_reg_01 reg_01; | |
2770 | unsigned long flags; | |
2771 | ||
2772 | spin_lock_irqsave(&ioapic_lock, flags); | |
2773 | reg_01.raw = io_apic_read(ioapic, 1); | |
2774 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2775 | ||
2776 | return reg_01.bits.entries; | |
2777 | } | |
2778 | ||
2779 | ||
36062448 | 2780 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low) |
1da177e4 LT |
2781 | { |
2782 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2783 | |
2784 | if (!IO_APIC_IRQ(irq)) { | |
2785 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2786 | ioapic); | |
2787 | return -EINVAL; | |
2788 | } | |
2789 | ||
2790 | /* | |
2791 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2792 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2793 | * corresponding device driver registers for this IRQ. | |
2794 | */ | |
2795 | ||
36062448 | 2796 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
2797 | |
2798 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2799 | entry.dest_mode = INT_DEST_MODE; | |
2800 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2801 | entry.trigger = edge_level; | |
2802 | entry.polarity = active_high_low; | |
2803 | entry.mask = 1; | |
2804 | ||
2805 | /* | |
2806 | * IRQs < 16 are already in the irq_2_pin[] map | |
2807 | */ | |
2808 | if (irq >= 16) | |
2809 | add_pin_to_irq(irq, ioapic, pin); | |
2810 | ||
2811 | entry.vector = assign_irq_vector(irq); | |
2812 | ||
2813 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2814 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
ec2cd0a2 | 2815 | mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq, |
1da177e4 LT |
2816 | edge_level, active_high_low); |
2817 | ||
2818 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2819 | ||
2820 | if (!ioapic && (irq < 16)) | |
2821 | disable_8259A_irq(irq); | |
2822 | ||
a2249cba | 2823 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2824 | |
2825 | return 0; | |
2826 | } | |
2827 | ||
61fd47e0 SL |
2828 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2829 | { | |
2830 | int i; | |
2831 | ||
2832 | if (skip_ioapic_setup) | |
2833 | return -1; | |
2834 | ||
2835 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2836 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2837 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2838 | break; |
2839 | if (i >= mp_irq_entries) | |
2840 | return -1; | |
2841 | ||
2842 | *trigger = irq_trigger(i); | |
2843 | *polarity = irq_polarity(i); | |
2844 | return 0; | |
2845 | } | |
2846 | ||
888ba6c6 | 2847 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2848 | |
2849 | static int __init parse_disable_timer_pin_1(char *arg) | |
2850 | { | |
2851 | disable_timer_pin_1 = 1; | |
2852 | return 0; | |
2853 | } | |
2854 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2855 | ||
2856 | static int __init parse_enable_timer_pin_1(char *arg) | |
2857 | { | |
2858 | disable_timer_pin_1 = -1; | |
2859 | return 0; | |
2860 | } | |
2861 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2862 | ||
2863 | static int __init parse_noapic(char *arg) | |
2864 | { | |
2865 | /* disable IO-APIC */ | |
2866 | disable_ioapic_setup(); | |
2867 | return 0; | |
2868 | } | |
2869 | early_param("noapic", parse_noapic); | |
f3294a33 YL |
2870 | |
2871 | void __init ioapic_init_mappings(void) | |
2872 | { | |
2873 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2874 | int i; | |
2875 | ||
2876 | for (i = 0; i < nr_ioapics; i++) { | |
2877 | if (smp_found_config) { | |
2878 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
2879 | if (!ioapic_phys) { | |
2880 | printk(KERN_ERR | |
2881 | "WARNING: bogus zero IO-APIC " | |
2882 | "address found in MPTABLE, " | |
2883 | "disabling IO/APIC support!\n"); | |
2884 | smp_found_config = 0; | |
2885 | skip_ioapic_setup = 1; | |
2886 | goto fake_ioapic_page; | |
2887 | } | |
2888 | } else { | |
2889 | fake_ioapic_page: | |
2890 | ioapic_phys = (unsigned long) | |
2891 | alloc_bootmem_pages(PAGE_SIZE); | |
2892 | ioapic_phys = __pa(ioapic_phys); | |
2893 | } | |
2894 | set_fixmap_nocache(idx, ioapic_phys); | |
2895 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
2896 | __fix_to_virt(idx), ioapic_phys); | |
2897 | idx++; | |
2898 | } | |
2899 | } | |
2900 |