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1da177e4 LT |
1 | /* |
2 | * hp100.h: Hewlett Packard HP10/100VG ANY LAN ethernet driver for Linux. | |
3 | * | |
4 | * $Id: hp100.h,v 1.51 1997/04/08 14:26:42 floeff Exp floeff $ | |
5 | * | |
6 | * Authors: Jaroslav Kysela, <perex@pf.jcu.cz> | |
7 | * Siegfried Loeffler <floeff@tunix.mathematik.uni-stuttgart.de> | |
8 | * | |
9 | * This driver is based on the 'hpfepkt' crynwr packet driver. | |
10 | * | |
6aa20a22 | 11 | * This source/code is public free; you can distribute it and/or modify |
1da177e4 | 12 | * it under terms of the GNU General Public License (published by the |
6aa20a22 | 13 | * Free Software Foundation) either version two of this License, or any |
1da177e4 LT |
14 | * later version. |
15 | */ | |
16 | ||
17 | /**************************************************************************** | |
18 | * Hardware Constants | |
19 | ****************************************************************************/ | |
20 | ||
6aa20a22 | 21 | /* |
1da177e4 LT |
22 | * Page Identifiers |
23 | * (Swap Paging Register, PAGING, bits 3:0, Offset 0x02) | |
24 | */ | |
25 | ||
26 | #define HP100_PAGE_PERFORMANCE 0x0 /* Page 0 */ | |
27 | #define HP100_PAGE_MAC_ADDRESS 0x1 /* Page 1 */ | |
28 | #define HP100_PAGE_HW_MAP 0x2 /* Page 2 */ | |
29 | #define HP100_PAGE_EEPROM_CTRL 0x3 /* Page 3 */ | |
30 | #define HP100_PAGE_MAC_CTRL 0x4 /* Page 4 */ | |
31 | #define HP100_PAGE_MMU_CFG 0x5 /* Page 5 */ | |
32 | #define HP100_PAGE_ID_MAC_ADDR 0x6 /* Page 6 */ | |
33 | #define HP100_PAGE_MMU_POINTER 0x7 /* Page 7 */ | |
34 | ||
35 | ||
36 | /* Registers that are present on all pages */ | |
37 | ||
38 | #define HP100_REG_HW_ID 0x00 /* R: (16) Unique card ID */ | |
39 | #define HP100_REG_TRACE 0x00 /* W: (16) Used for debug output */ | |
40 | #define HP100_REG_PAGING 0x02 /* R: (16),15:4 Card ID */ | |
41 | /* W: (16),3:0 Switch pages */ | |
42 | #define HP100_REG_OPTION_LSW 0x04 /* RW: (16) Select card functions */ | |
43 | #define HP100_REG_OPTION_MSW 0x06 /* RW: (16) Select card functions */ | |
44 | ||
45 | /* Page 0 - Performance */ | |
46 | ||
47 | #define HP100_REG_IRQ_STATUS 0x08 /* RW: (16) Which ints are pending */ | |
48 | #define HP100_REG_IRQ_MASK 0x0a /* RW: (16) Select ints to allow */ | |
49 | #define HP100_REG_FRAGMENT_LEN 0x0c /* W: (16)12:0 Current fragment len */ | |
50 | /* Note: For 32 bit systems, fragment len and offset registers are available */ | |
51 | /* at offset 0x28 and 0x2c, where they can be written as 32bit values. */ | |
52 | #define HP100_REG_OFFSET 0x0e /* RW: (16)12:0 Offset to start read */ | |
53 | #define HP100_REG_DATA32 0x10 /* RW: (32) I/O mode data port */ | |
54 | #define HP100_REG_DATA16 0x12 /* RW: WORDs must be read from here */ | |
55 | #define HP100_REG_TX_MEM_FREE 0x14 /* RD: (32) Amount of free Tx mem */ | |
56 | #define HP100_REG_TX_PDA_L 0x14 /* W: (32) BM: Ptr to PDL, Low Pri */ | |
57 | #define HP100_REG_TX_PDA_H 0x1c /* W: (32) BM: Ptr to PDL, High Pri */ | |
58 | #define HP100_REG_RX_PKT_CNT 0x18 /* RD: (8) Rx count of pkts on card */ | |
59 | #define HP100_REG_TX_PKT_CNT 0x19 /* RD: (8) Tx count of pkts on card */ | |
60 | #define HP100_REG_RX_PDL 0x1a /* R: (8) BM: # rx pdl not executed */ | |
61 | #define HP100_REG_TX_PDL 0x1b /* R: (8) BM: # tx pdl not executed */ | |
62 | #define HP100_REG_RX_PDA 0x18 /* W: (32) BM: Up to 31 addresses */ | |
63 | /* which point to a PDL */ | |
64 | #define HP100_REG_SL_EARLY 0x1c /* (32) Enhanced Slave Early Rx */ | |
65 | #define HP100_REG_STAT_DROPPED 0x20 /* R (12) Dropped Packet Counter */ | |
66 | #define HP100_REG_STAT_ERRORED 0x22 /* R (8) Errored Packet Counter */ | |
67 | #define HP100_REG_STAT_ABORT 0x23 /* R (8) Abort Counter/OW Coll. Flag */ | |
68 | #define HP100_REG_RX_RING 0x24 /* W (32) Slave: RX Ring Pointers */ | |
69 | #define HP100_REG_32_FRAGMENT_LEN 0x28 /* W (13) Slave: Fragment Length Reg */ | |
70 | #define HP100_REG_32_OFFSET 0x2c /* W (16) Slave: Offset Register */ | |
71 | ||
72 | /* Page 1 - MAC Address/Hash Table */ | |
73 | ||
74 | #define HP100_REG_MAC_ADDR 0x08 /* RW: (8) Cards MAC address */ | |
75 | #define HP100_REG_HASH_BYTE0 0x10 /* RW: (8) Cards multicast filter */ | |
76 | ||
77 | /* Page 2 - Hardware Mapping */ | |
78 | ||
79 | #define HP100_REG_MEM_MAP_LSW 0x08 /* RW: (16) LSW of cards mem addr */ | |
80 | #define HP100_REG_MEM_MAP_MSW 0x0a /* RW: (16) MSW of cards mem addr */ | |
81 | #define HP100_REG_IO_MAP 0x0c /* RW: (8) Cards I/O address */ | |
82 | #define HP100_REG_IRQ_CHANNEL 0x0d /* RW: (8) IRQ and edge/level int */ | |
83 | #define HP100_REG_SRAM 0x0e /* RW: (8) How much RAM on card */ | |
84 | #define HP100_REG_BM 0x0f /* RW: (8) Controls BM functions */ | |
85 | ||
86 | /* New on Page 2 for ETR chips: */ | |
87 | #define HP100_REG_MODECTRL1 0x10 /* RW: (8) Mode Control 1 */ | |
88 | #define HP100_REG_MODECTRL2 0x11 /* RW: (8) Mode Control 2 */ | |
89 | #define HP100_REG_PCICTRL1 0x12 /* RW: (8) PCI Cfg 1 */ | |
90 | #define HP100_REG_PCICTRL2 0x13 /* RW: (8) PCI Cfg 2 */ | |
91 | #define HP100_REG_PCIBUSMLAT 0x15 /* RW: (8) PCI Bus Master Latency */ | |
92 | #define HP100_REG_EARLYTXCFG 0x16 /* RW: (16) Early TX Cfg/Cntrl Reg */ | |
93 | #define HP100_REG_EARLYRXCFG 0x18 /* RW: (8) Early RX Cfg/Cntrl Reg */ | |
94 | #define HP100_REG_ISAPNPCFG1 0x1a /* RW: (8) ISA PnP Cfg/Cntrl Reg 1 */ | |
95 | #define HP100_REG_ISAPNPCFG2 0x1b /* RW: (8) ISA PnP Cfg/Cntrl Reg 2 */ | |
96 | ||
97 | /* Page 3 - EEPROM/Boot ROM */ | |
98 | ||
99 | #define HP100_REG_EEPROM_CTRL 0x08 /* RW: (16) Used to load EEPROM */ | |
100 | #define HP100_REG_BOOTROM_CTRL 0x0a | |
101 | ||
102 | /* Page 4 - LAN Configuration (MAC_CTRL) */ | |
103 | ||
104 | #define HP100_REG_10_LAN_CFG_1 0x08 /* RW: (8) Set 10M XCVR functions */ | |
105 | #define HP100_REG_10_LAN_CFG_2 0x09 /* RW: (8) 10M XCVR functions */ | |
106 | #define HP100_REG_VG_LAN_CFG_1 0x0a /* RW: (8) Set 100M XCVR functions */ | |
107 | #define HP100_REG_VG_LAN_CFG_2 0x0b /* RW: (8) 100M LAN Training cfgregs */ | |
108 | #define HP100_REG_MAC_CFG_1 0x0c /* RW: (8) Types of pkts to accept */ | |
109 | #define HP100_REG_MAC_CFG_2 0x0d /* RW: (8) Misc MAC functions */ | |
110 | #define HP100_REG_MAC_CFG_3 0x0e /* RW: (8) Misc MAC functions */ | |
111 | #define HP100_REG_MAC_CFG_4 0x0f /* R: (8) Misc MAC states */ | |
112 | #define HP100_REG_DROPPED 0x10 /* R: (16),11:0 Pkts cant fit in mem */ | |
113 | #define HP100_REG_CRC 0x12 /* R: (8) Pkts with CRC */ | |
114 | #define HP100_REG_ABORT 0x13 /* R: (8) Aborted Tx pkts */ | |
115 | #define HP100_REG_TRAIN_REQUEST 0x14 /* RW: (16) Endnode MAC register. */ | |
116 | #define HP100_REG_TRAIN_ALLOW 0x16 /* R: (16) Hub allowed register */ | |
117 | ||
118 | /* Page 5 - MMU */ | |
119 | ||
120 | #define HP100_REG_RX_MEM_STOP 0x0c /* RW: (16) End of Rx ring addr */ | |
121 | #define HP100_REG_TX_MEM_STOP 0x0e /* RW: (16) End of Tx ring addr */ | |
122 | #define HP100_REG_PDL_MEM_STOP 0x10 /* Not used by 802.12 devices */ | |
123 | #define HP100_REG_ECB_MEM_STOP 0x14 /* I've no idea what this is */ | |
124 | ||
125 | /* Page 6 - Card ID/Physical LAN Address */ | |
126 | ||
127 | #define HP100_REG_BOARD_ID 0x08 /* R: (8) EISA/ISA card ID */ | |
128 | #define HP100_REG_BOARD_IO_CHCK 0x0c /* R: (8) Added to ID to get FFh */ | |
129 | #define HP100_REG_SOFT_MODEL 0x0d /* R: (8) Config program defined */ | |
130 | #define HP100_REG_LAN_ADDR 0x10 /* R: (8) MAC addr of card */ | |
131 | #define HP100_REG_LAN_ADDR_CHCK 0x16 /* R: (8) Added to addr to get FFh */ | |
132 | ||
133 | /* Page 7 - MMU Current Pointers */ | |
134 | ||
135 | #define HP100_REG_PTR_RXSTART 0x08 /* R: (16) Current begin of Rx ring */ | |
136 | #define HP100_REG_PTR_RXEND 0x0a /* R: (16) Current end of Rx ring */ | |
137 | #define HP100_REG_PTR_TXSTART 0x0c /* R: (16) Current begin of Tx ring */ | |
138 | #define HP100_REG_PTR_TXEND 0x0e /* R: (16) Current end of Rx ring */ | |
139 | #define HP100_REG_PTR_RPDLSTART 0x10 | |
140 | #define HP100_REG_PTR_RPDLEND 0x12 | |
141 | #define HP100_REG_PTR_RINGPTRS 0x14 | |
142 | #define HP100_REG_PTR_MEMDEBUG 0x1a | |
143 | /* ------------------------------------------------------------------------ */ | |
144 | ||
145 | ||
6aa20a22 | 146 | /* |
1da177e4 LT |
147 | * Hardware ID Register I (Always available, HW_ID, Offset 0x00) |
148 | */ | |
149 | #define HP100_HW_ID_CASCADE 0x4850 /* Identifies Cascade Chip */ | |
150 | ||
6aa20a22 | 151 | /* |
1da177e4 LT |
152 | * Hardware ID Register 2 & Paging Register |
153 | * (Always available, PAGING, Offset 0x02) | |
6aa20a22 | 154 | * Bits 15:4 are for the Chip ID |
1da177e4 LT |
155 | */ |
156 | #define HP100_CHIPID_MASK 0xFFF0 | |
157 | #define HP100_CHIPID_SHASTA 0x5350 /* Not 802.12 compliant */ | |
158 | /* EISA BM/SL, MCA16/32 SL, ISA SL */ | |
159 | #define HP100_CHIPID_RAINIER 0x5360 /* Not 802.12 compliant EISA BM, */ | |
160 | /* PCI SL, MCA16/32 SL, ISA SL */ | |
161 | #define HP100_CHIPID_LASSEN 0x5370 /* 802.12 compliant PCI BM, PCI SL */ | |
162 | /* LRF supported */ | |
163 | ||
164 | /* | |
6aa20a22 | 165 | * Option Registers I and II |
1da177e4 LT |
166 | * (Always available, OPTION_LSW, Offset 0x04-0x05) |
167 | */ | |
168 | #define HP100_DEBUG_EN 0x8000 /* 0:Dis., 1:Enable Debug Dump Ptr. */ | |
169 | #define HP100_RX_HDR 0x4000 /* 0:Dis., 1:Enable putting pkt into */ | |
170 | /* system mem. before Rx interrupt */ | |
171 | #define HP100_MMAP_DIS 0x2000 /* 0:Enable, 1:Disable mem.mapping. */ | |
172 | /* MMAP_DIS must be 0 and MEM_EN */ | |
173 | /* must be 1 for memory-mapped */ | |
174 | /* mode to be enabled */ | |
175 | #define HP100_EE_EN 0x1000 /* 0:Disable,1:Enable EEPROM writing */ | |
176 | #define HP100_BM_WRITE 0x0800 /* 0:Slave, 1:Bus Master for Tx data */ | |
177 | #define HP100_BM_READ 0x0400 /* 0:Slave, 1:Bus Master for Rx data */ | |
178 | #define HP100_TRI_INT 0x0200 /* 0:Don't, 1:Do tri-state the int */ | |
179 | #define HP100_MEM_EN 0x0040 /* Config program set this to */ | |
180 | /* 0:Disable, 1:Enable mem map. */ | |
181 | /* See MMAP_DIS. */ | |
182 | #define HP100_IO_EN 0x0020 /* 1:Enable I/O transfers */ | |
183 | #define HP100_BOOT_EN 0x0010 /* 1:Enable boot ROM access */ | |
184 | #define HP100_FAKE_INT 0x0008 /* 1:int */ | |
185 | #define HP100_INT_EN 0x0004 /* 1:Enable ints from card */ | |
186 | #define HP100_HW_RST 0x0002 /* 0:Reset, 1:Out of reset */ | |
187 | /* NIC reset on 0 to 1 transition */ | |
188 | ||
189 | /* | |
6aa20a22 | 190 | * Option Register III |
1da177e4 LT |
191 | * (Always available, OPTION_MSW, Offset 0x06) |
192 | */ | |
193 | #define HP100_PRIORITY_TX 0x0080 /* 1:Do all Tx pkts as priority */ | |
194 | #define HP100_EE_LOAD 0x0040 /* 1:EEPROM loading, 0 when done */ | |
195 | #define HP100_ADV_NXT_PKT 0x0004 /* 1:Advance to next pkt in Rx queue */ | |
196 | /* h/w will set to 0 when done */ | |
197 | #define HP100_TX_CMD 0x0002 /* 1:Tell h/w download done, h/w */ | |
198 | /* will set to 0 when done */ | |
199 | ||
200 | /* | |
201 | * Interrupt Status Registers I and II | |
202 | * (Page PERFORMANCE, IRQ_STATUS, Offset 0x08-0x09) | |
203 | * Note: With old chips, these Registers will clear when 1 is written to them | |
204 | * with new chips this depends on setting of CLR_ISMODE | |
205 | */ | |
206 | #define HP100_RX_EARLY_INT 0x2000 | |
207 | #define HP100_RX_PDA_ZERO 0x1000 | |
208 | #define HP100_RX_PDL_FILL_COMPL 0x0800 | |
209 | #define HP100_RX_PACKET 0x0400 /* 0:No, 1:Yes pkt has been Rx */ | |
210 | #define HP100_RX_ERROR 0x0200 /* 0:No, 1:Yes Rx pkt had error */ | |
211 | #define HP100_TX_PDA_ZERO 0x0020 /* 1 when PDA count goes to zero */ | |
212 | #define HP100_TX_SPACE_AVAIL 0x0010 /* 0:<8192, 1:>=8192 Tx free bytes */ | |
213 | #define HP100_TX_COMPLETE 0x0008 /* 0:No, 1:Yes a Tx has completed */ | |
214 | #define HP100_MISC_ERROR 0x0004 /* 0:No, 1:Lan Link down or bus error */ | |
215 | #define HP100_TX_ERROR 0x0002 /* 0:No, 1:Yes Tx pkt had error */ | |
216 | ||
217 | /* | |
218 | * Xmit Memory Free Count | |
219 | * (Page PERFORMANCE, TX_MEM_FREE, Offset 0x14) (Read only, 32bit) | |
220 | */ | |
221 | #define HP100_AUTO_COMPARE 0x80000000 /* Tx Space avail & pkts<255 */ | |
222 | #define HP100_FREE_SPACE 0x7fffffe0 /* Tx free memory */ | |
223 | ||
224 | /* | |
225 | * IRQ Channel | |
226 | * (Page HW_MAP, IRQ_CHANNEL, Offset 0x0d) | |
227 | */ | |
228 | #define HP100_ZERO_WAIT_EN 0x80 /* 0:No, 1:Yes asserts NOWS signal */ | |
229 | #define HP100_IRQ_SCRAMBLE 0x40 | |
230 | #define HP100_BOND_HP 0x20 | |
231 | #define HP100_LEVEL_IRQ 0x10 /* 0:Edge, 1:Level type interrupts. */ | |
232 | /* (Only valid on EISA cards) */ | |
233 | #define HP100_IRQMASK 0x0F /* Isolate the IRQ bits */ | |
234 | ||
235 | /* | |
236 | * SRAM Parameters | |
237 | * (Page HW_MAP, SRAM, Offset 0x0e) | |
238 | */ | |
239 | #define HP100_RAM_SIZE_MASK 0xe0 /* AND to get SRAM size index */ | |
240 | #define HP100_RAM_SIZE_SHIFT 0x05 /* Shift count(put index in lwr bits) */ | |
241 | ||
242 | /* | |
243 | * Bus Master Register | |
244 | * (Page HW_MAP, BM, Offset 0x0f) | |
245 | */ | |
246 | #define HP100_BM_BURST_RD 0x01 /* EISA only: 1=Use burst trans. fm system */ | |
247 | /* memory to chip (tx) */ | |
248 | #define HP100_BM_BURST_WR 0x02 /* EISA only: 1=Use burst trans. fm system */ | |
249 | /* memory to chip (rx) */ | |
250 | #define HP100_BM_MASTER 0x04 /* 0:Slave, 1:BM mode */ | |
251 | #define HP100_BM_PAGE_CK 0x08 /* This bit should be set whenever in */ | |
252 | /* an EISA system */ | |
253 | #define HP100_BM_PCI_8CLK 0x40 /* ... cycles 8 clocks apart */ | |
254 | ||
255 | ||
6aa20a22 | 256 | /* |
1da177e4 LT |
257 | * Mode Control Register I |
258 | * (Page HW_MAP, MODECTRL1, Offset0x10) | |
259 | */ | |
260 | #define HP100_TX_DUALQ 0x10 | |
261 | /* If set and BM -> dual tx pda queues */ | |
262 | #define HP100_ISR_CLRMODE 0x02 /* If set ISR will clear all pending */ | |
263 | /* interrupts on read (etr only?) */ | |
264 | #define HP100_EE_NOLOAD 0x04 /* Status whether res will be loaded */ | |
265 | /* from the eeprom */ | |
266 | #define HP100_TX_CNT_FLG 0x08 /* Controls Early TX Reg Cnt Field */ | |
267 | #define HP100_PDL_USE3 0x10 /* If set BM engine will read only */ | |
268 | /* first three data elements of a PDL */ | |
269 | /* on the first access. */ | |
270 | #define HP100_BUSTYPE_MASK 0xe0 /* Three bit bus type info */ | |
271 | ||
272 | /* | |
273 | * Mode Control Register II | |
274 | * (Page HW_MAP, MODECTRL2, Offset0x11) | |
275 | */ | |
276 | #define HP100_EE_MASK 0x0f /* Tell EEPROM circuit not to load */ | |
277 | /* certain resources */ | |
278 | #define HP100_DIS_CANCEL 0x20 /* For tx dualq mode operation */ | |
279 | #define HP100_EN_PDL_WB 0x40 /* 1: Status of PDL completion may be */ | |
280 | /* written back to system mem */ | |
281 | #define HP100_EN_BUS_FAIL 0x80 /* Enables bus-fail portion of misc */ | |
282 | /* interrupt */ | |
283 | ||
6aa20a22 | 284 | /* |
1da177e4 LT |
285 | * PCI Configuration and Control Register I |
286 | * (Page HW_MAP, PCICTRL1, Offset 0x12) | |
287 | */ | |
288 | #define HP100_LO_MEM 0x01 /* 1: Mapped Mem requested below 1MB */ | |
289 | #define HP100_NO_MEM 0x02 /* 1: Disables Req for sysmem to PCI */ | |
290 | /* bios */ | |
291 | #define HP100_USE_ISA 0x04 /* 1: isa type decodes will occur */ | |
292 | /* simultaneously with PCI decodes */ | |
293 | #define HP100_IRQ_HI_MASK 0xf0 /* pgmed by pci bios */ | |
294 | #define HP100_PCI_IRQ_HI_MASK 0x78 /* Isolate 4 bits for PCI IRQ */ | |
295 | ||
296 | /* | |
297 | * PCI Configuration and Control Register II | |
298 | * (Page HW_MAP, PCICTRL2, Offset 0x13) | |
299 | */ | |
300 | #define HP100_RD_LINE_PDL 0x01 /* 1: PCI command Memory Read Line en */ | |
301 | #define HP100_RD_TX_DATA_MASK 0x06 /* choose PCI memread cmds for TX */ | |
302 | #define HP100_MWI 0x08 /* 1: en. PCI memory write invalidate */ | |
303 | #define HP100_ARB_MODE 0x10 /* Select PCI arbitor type */ | |
304 | #define HP100_STOP_EN 0x20 /* Enables PCI state machine to issue */ | |
305 | /* pci stop if cascade not ready */ | |
306 | #define HP100_IGNORE_PAR 0x40 /* 1: PCI state machine ignores parity */ | |
307 | #define HP100_PCI_RESET 0x80 /* 0->1: Reset PCI block */ | |
308 | ||
309 | /* | |
310 | * Early TX Configuration and Control Register | |
311 | * (Page HW_MAP, EARLYTXCFG, Offset 0x16) | |
312 | */ | |
313 | #define HP100_EN_EARLY_TX 0x8000 /* 1=Enable Early TX */ | |
314 | #define HP100_EN_ADAPTIVE 0x4000 /* 1=Enable adaptive mode */ | |
315 | #define HP100_EN_TX_UR_IRQ 0x2000 /* reserved, must be 0 */ | |
316 | #define HP100_EN_LOW_TX 0x1000 /* reserved, must be 0 */ | |
317 | #define HP100_ET_CNT_MASK 0x0fff /* bits 11..0: ET counters */ | |
318 | ||
319 | /* | |
320 | * Early RX Configuration and Control Register | |
321 | * (Page HW_MAP, EARLYRXCFG, Offset 0x18) | |
322 | */ | |
323 | #define HP100_EN_EARLY_RX 0x80 /* 1=Enable Early RX */ | |
324 | #define HP100_EN_LOW_RX 0x40 /* reserved, must be 0 */ | |
325 | #define HP100_RX_TRIP_MASK 0x1f /* bits 4..0: threshold at which the | |
326 | * early rx circuit will start the | |
327 | * dma of received packet into system | |
328 | * memory for BM */ | |
329 | ||
330 | /* | |
331 | * Serial Devices Control Register | |
332 | * (Page EEPROM_CTRL, EEPROM_CTRL, Offset 0x08) | |
333 | */ | |
334 | #define HP100_EEPROM_LOAD 0x0001 /* 0->1 loads EEPROM into registers. */ | |
335 | /* When it goes back to 0, load is */ | |
336 | /* complete. This should take ~600us. */ | |
337 | ||
338 | /* | |
339 | * 10MB LAN Control and Configuration Register I | |
340 | * (Page MAC_CTRL, 10_LAN_CFG_1, Offset 0x08) | |
341 | */ | |
342 | #define HP100_MAC10_SEL 0xc0 /* Get bits to indicate MAC */ | |
343 | #define HP100_AUI_SEL 0x20 /* Status of AUI selection */ | |
344 | #define HP100_LOW_TH 0x10 /* 0:No, 1:Yes allow better cabling */ | |
345 | #define HP100_LINK_BEAT_DIS 0x08 /* 0:Enable, 1:Disable link beat */ | |
346 | #define HP100_LINK_BEAT_ST 0x04 /* 0:No, 1:Yes link beat being Rx */ | |
347 | #define HP100_R_ROL_ST 0x02 /* 0:No, 1:Yes Rx twisted pair has */ | |
348 | /* been reversed */ | |
349 | #define HP100_AUI_ST 0x01 /* 0:No, 1:Yes use AUI on TP card */ | |
350 | ||
351 | /* | |
352 | * 10 MB LAN Control and Configuration Register II | |
353 | * (Page MAC_CTRL, 10_LAN_CFG_2, Offset 0x09) | |
354 | */ | |
355 | #define HP100_SQU_ST 0x01 /* 0:No, 1:Yes collision signal sent */ | |
356 | /* after Tx.Only used for AUI. */ | |
357 | #define HP100_FULLDUP 0x02 /* 1: LXT901 XCVR fullduplx enabled */ | |
358 | #define HP100_DOT3_MAC 0x04 /* 1: DOT 3 Mac sel. unless Autosel */ | |
359 | ||
360 | /* | |
361 | * MAC Selection, use with MAC10_SEL bits | |
362 | */ | |
363 | #define HP100_AUTO_SEL_10 0x0 /* Auto select */ | |
364 | #define HP100_XCVR_LXT901_10 0x1 /* LXT901 10BaseT transceiver */ | |
365 | #define HP100_XCVR_7213 0x2 /* 7213 transceiver */ | |
366 | #define HP100_XCVR_82503 0x3 /* 82503 transceiver */ | |
367 | ||
368 | /* | |
369 | * 100MB LAN Training Register | |
370 | * (Page MAC_CTRL, VG_LAN_CFG_2, Offset 0x0b) (old, pre 802.12) | |
371 | */ | |
372 | #define HP100_FRAME_FORMAT 0x08 /* 0:802.3, 1:802.5 frames */ | |
373 | #define HP100_BRIDGE 0x04 /* 0:No, 1:Yes tell hub i am a bridge */ | |
374 | #define HP100_PROM_MODE 0x02 /* 0:No, 1:Yes tell hub card is */ | |
375 | /* promiscuous */ | |
376 | #define HP100_REPEATER 0x01 /* 0:No, 1:Yes tell hub MAC wants to */ | |
377 | /* be a cascaded repeater */ | |
378 | ||
379 | /* | |
380 | * 100MB LAN Control and Configuration Register | |
6aa20a22 | 381 | * (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a) |
1da177e4 LT |
382 | */ |
383 | #define HP100_VG_SEL 0x80 /* 0:No, 1:Yes use 100 Mbit MAC */ | |
384 | #define HP100_LINK_UP_ST 0x40 /* 0:No, 1:Yes endnode logged in */ | |
385 | #define HP100_LINK_CABLE_ST 0x20 /* 0:No, 1:Yes cable can hear tones */ | |
386 | /* from hub */ | |
387 | #define HP100_LOAD_ADDR 0x10 /* 0->1 card addr will be sent */ | |
388 | /* 100ms later the link status */ | |
389 | /* bits are valid */ | |
390 | #define HP100_LINK_CMD 0x08 /* 0->1 link will attempt to log in. */ | |
391 | /* 100ms later the link status */ | |
392 | /* bits are valid */ | |
393 | #define HP100_TRN_DONE 0x04 /* NEW ETR-Chips only: Will be reset */ | |
394 | /* after LinkUp Cmd is given and set */ | |
395 | /* when training has completed. */ | |
396 | #define HP100_LINK_GOOD_ST 0x02 /* 0:No, 1:Yes cable passed training */ | |
397 | #define HP100_VG_RESET 0x01 /* 0:Yes, 1:No reset the 100VG MAC */ | |
398 | ||
399 | ||
400 | /* | |
401 | * MAC Configuration Register I | |
402 | * (Page MAC_CTRL, MAC_CFG_1, Offset 0x0c) | |
403 | */ | |
404 | #define HP100_RX_IDLE 0x80 /* 0:Yes, 1:No currently receiving pkts */ | |
405 | #define HP100_TX_IDLE 0x40 /* 0:Yes, 1:No currently Txing pkts */ | |
406 | #define HP100_RX_EN 0x20 /* 1: allow receiving of pkts */ | |
407 | #define HP100_TX_EN 0x10 /* 1: allow transmitting of pkts */ | |
408 | #define HP100_ACC_ERRORED 0x08 /* 0:No, 1:Yes allow Rx of errored pkts */ | |
409 | #define HP100_ACC_MC 0x04 /* 0:No, 1:Yes allow Rx of multicast pkts */ | |
410 | #define HP100_ACC_BC 0x02 /* 0:No, 1:Yes allow Rx of broadcast pkts */ | |
411 | #define HP100_ACC_PHY 0x01 /* 0:No, 1:Yes allow Rx of ALL phys. pkts */ | |
412 | #define HP100_MAC1MODEMASK 0xf0 /* Hide ACC bits */ | |
413 | #define HP100_MAC1MODE1 0x00 /* Receive nothing, must also disable RX */ | |
414 | #define HP100_MAC1MODE2 0x00 | |
415 | #define HP100_MAC1MODE3 HP100_MAC1MODE2 | HP100_ACC_BC | |
416 | #define HP100_MAC1MODE4 HP100_MAC1MODE3 | HP100_ACC_MC | |
417 | #define HP100_MAC1MODE5 HP100_MAC1MODE4 /* set mc hash to all ones also */ | |
418 | #define HP100_MAC1MODE6 HP100_MAC1MODE5 | HP100_ACC_PHY /* Promiscuous */ | |
419 | /* Note MODE6 will receive all GOOD packets on the LAN. This really needs | |
420 | a mode 7 defined to be LAN Analyzer mode, which will receive errored and | |
421 | runt packets, and keep the CRC bytes. */ | |
422 | #define HP100_MAC1MODE7 HP100_MAC1MODE6 | HP100_ACC_ERRORED | |
423 | ||
424 | /* | |
6aa20a22 | 425 | * MAC Configuration Register II |
1da177e4 LT |
426 | * (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d) |
427 | */ | |
428 | #define HP100_TR_MODE 0x80 /* 0:No, 1:Yes support Token Ring formats */ | |
429 | #define HP100_TX_SAME 0x40 /* 0:No, 1:Yes Tx same packet continuous */ | |
430 | #define HP100_LBK_XCVR 0x20 /* 0:No, 1:Yes loopback through MAC & */ | |
431 | /* transceiver */ | |
432 | #define HP100_LBK_MAC 0x10 /* 0:No, 1:Yes loopback through MAC */ | |
433 | #define HP100_CRC_I 0x08 /* 0:No, 1:Yes inhibit CRC on Tx packets */ | |
434 | #define HP100_ACCNA 0x04 /* 1: For 802.5: Accept only token ring | |
435 | * group addr that maches NA mask */ | |
436 | #define HP100_KEEP_CRC 0x02 /* 0:No, 1:Yes keep CRC on Rx packets. */ | |
437 | /* The length will reflect this. */ | |
438 | #define HP100_ACCFA 0x01 /* 1: For 802.5: Accept only functional | |
439 | * addrs that match FA mask (page1) */ | |
440 | #define HP100_MAC2MODEMASK 0x02 | |
441 | #define HP100_MAC2MODE1 0x00 | |
442 | #define HP100_MAC2MODE2 0x00 | |
443 | #define HP100_MAC2MODE3 0x00 | |
444 | #define HP100_MAC2MODE4 0x00 | |
445 | #define HP100_MAC2MODE5 0x00 | |
446 | #define HP100_MAC2MODE6 0x00 | |
447 | #define HP100_MAC2MODE7 KEEP_CRC | |
448 | ||
449 | /* | |
6aa20a22 JG |
450 | * MAC Configuration Register III |
451 | * (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e) | |
1da177e4 LT |
452 | */ |
453 | #define HP100_PACKET_PACE 0x03 /* Packet Pacing: | |
454 | * 00: No packet pacing | |
455 | * 01: 8 to 16 uS delay | |
456 | * 10: 16 to 32 uS delay | |
457 | * 11: 32 to 64 uS delay | |
458 | */ | |
459 | #define HP100_LRF_EN 0x04 /* 1: External LAN Rcv Filter and | |
460 | * TCP/IP Checksumming enabled. */ | |
461 | #define HP100_AUTO_MODE 0x10 /* 1: AutoSelect between 10/100 */ | |
462 | ||
463 | /* | |
6aa20a22 | 464 | * MAC Configuration Register IV |
1da177e4 LT |
465 | * (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f) |
466 | */ | |
467 | #define HP100_MAC_SEL_ST 0x01 /* (R): Status of external VGSEL | |
468 | * Signal, 1=100VG, 0=10Mbit sel. */ | |
469 | #define HP100_LINK_FAIL_ST 0x02 /* (R): Status of Link Fail portion | |
470 | * of the Misc. Interrupt */ | |
471 | ||
6aa20a22 JG |
472 | /* |
473 | * 100 MB LAN Training Request/Allowed Registers | |
1da177e4 LT |
474 | * (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only) |
475 | */ | |
6aa20a22 | 476 | #define HP100_MACRQ_REPEATER 0x0001 /* 1: MAC tells HUB it wants to be |
1da177e4 LT |
477 | * a cascaded repeater |
478 | * 0: ... wants to be a DTE */ | |
479 | #define HP100_MACRQ_PROMSC 0x0006 /* 2 bits: Promiscious mode | |
480 | * 00: Rcv only unicast packets | |
481 | * specifically addr to this | |
482 | * endnode | |
6aa20a22 | 483 | * 10: Rcv all pckts fwded by |
1da177e4 LT |
484 | * the local repeater */ |
485 | #define HP100_MACRQ_FRAMEFMT_EITHER 0x0018 /* 11: either format allowed */ | |
486 | #define HP100_MACRQ_FRAMEFMT_802_3 0x0000 /* 00: 802.3 is requested */ | |
487 | #define HP100_MACRQ_FRAMEFMT_802_5 0x0010 /* 10: 802.5 format is requested */ | |
488 | #define HP100_CARD_MACVER 0xe000 /* R: 3 bit Cards 100VG MAC version */ | |
489 | #define HP100_MALLOW_REPEATER 0x0001 /* If reset, requested access as an | |
490 | * end node is allowed */ | |
491 | #define HP100_MALLOW_PROMSC 0x0004 /* 2 bits: Promiscious mode | |
492 | * 00: Rcv only unicast packets | |
493 | * specifically addr to this | |
494 | * endnode | |
6aa20a22 | 495 | * 10: Rcv all pckts fwded by |
1da177e4 LT |
496 | * the local repeater */ |
497 | #define HP100_MALLOW_FRAMEFMT 0x00e0 /* 2 bits: Frame Format | |
498 | * 00: 802.3 format will be used | |
499 | * 10: 802.5 format will be used */ | |
500 | #define HP100_MALLOW_ACCDENIED 0x0400 /* N bit */ | |
501 | #define HP100_MALLOW_CONFIGURE 0x0f00 /* C bit */ | |
502 | #define HP100_MALLOW_DUPADDR 0x1000 /* D bit */ | |
503 | #define HP100_HUB_MACVER 0xe000 /* R: 3 bit 802.12 MAC/RMAC training */ | |
504 | /* protocol of repeater */ | |
505 | ||
506 | /* ****************************************************************************** */ | |
507 | ||
508 | /* | |
509 | * Set/Reset bits | |
510 | */ | |
511 | #define HP100_SET_HB 0x0100 /* 0:Set fields to 0 whose mask is 1 */ | |
512 | #define HP100_SET_LB 0x0001 /* HB sets upper byte, LB sets lower byte */ | |
513 | #define HP100_RESET_HB 0x0000 /* For readability when resetting bits */ | |
514 | #define HP100_RESET_LB 0x0000 /* For readability when resetting bits */ | |
515 | ||
516 | /* | |
517 | * Misc. Constants | |
518 | */ | |
519 | #define HP100_LAN_100 100 /* lan_type value for VG */ | |
520 | #define HP100_LAN_10 10 /* lan_type value for 10BaseT */ | |
521 | #define HP100_LAN_COAX 9 /* lan_type value for Coax */ | |
522 | #define HP100_LAN_ERR (-1) /* lan_type value for link down */ | |
523 | ||
6aa20a22 | 524 | /* |
1da177e4 LT |
525 | * Bus Master Data Structures ---------------------------------------------- |
526 | */ | |
527 | ||
528 | #define MAX_RX_PDL 30 /* Card limit = 31 */ | |
529 | #define MAX_RX_FRAG 2 /* Don't need more... */ | |
530 | #define MAX_TX_PDL 29 | |
531 | #define MAX_TX_FRAG 2 /* Limit = 31 */ | |
532 | ||
533 | /* Define total PDL area size in bytes (should be 4096) */ | |
534 | /* This is the size of kernel (dma) memory that will be allocated. */ | |
535 | #define MAX_RINGSIZE ((MAX_RX_FRAG*8+4+4)*MAX_RX_PDL+(MAX_TX_FRAG*8+4+4)*MAX_TX_PDL)+16 | |
536 | ||
537 | /* Ethernet Packet Sizes */ | |
538 | #define MIN_ETHER_SIZE 60 | |
539 | #define MAX_ETHER_SIZE 1514 /* Needed for preallocation of */ | |
540 | /* skb buffer when busmastering */ | |
541 | ||
542 | /* Tx or Rx Ring Entry */ | |
543 | typedef struct hp100_ring { | |
544 | u_int *pdl; /* Address of PDLs PDH, dword before | |
545 | * this address is used for rx hdr */ | |
546 | u_int pdl_paddr; /* Physical address of PDL */ | |
547 | struct sk_buff *skb; | |
548 | struct hp100_ring *next; | |
549 | } hp100_ring_t; | |
550 | ||
551 | ||
552 | ||
553 | /* Mask for Header Descriptor */ | |
554 | #define HP100_PKT_LEN_MASK 0x1FFF /* AND with RxLength to get length */ | |
555 | ||
556 | ||
6aa20a22 | 557 | /* Receive Packet Status. Note, the error bits are only valid if ACC_ERRORED |
1da177e4 LT |
558 | bit in the MAC Configuration Register 1 is set. */ |
559 | #define HP100_RX_PRI 0x8000 /* 0:No, 1:Yes packet is priority */ | |
560 | #define HP100_SDF_ERR 0x4000 /* 0:No, 1:Yes start of frame error */ | |
561 | #define HP100_SKEW_ERR 0x2000 /* 0:No, 1:Yes skew out of range */ | |
562 | #define HP100_BAD_SYMBOL_ERR 0x1000 /* 0:No, 1:Yes invalid symbol received */ | |
563 | #define HP100_RCV_IPM_ERR 0x0800 /* 0:No, 1:Yes pkt had an invalid packet */ | |
564 | /* marker */ | |
565 | #define HP100_SYMBOL_BAL_ERR 0x0400 /* 0:No, 1:Yes symbol balance error */ | |
566 | #define HP100_VG_ALN_ERR 0x0200 /* 0:No, 1:Yes non-octet received */ | |
567 | #define HP100_TRUNC_ERR 0x0100 /* 0:No, 1:Yes the packet was truncated */ | |
568 | #define HP100_RUNT_ERR 0x0040 /* 0:No, 1:Yes pkt length < Min Pkt */ | |
569 | /* Length Reg. */ | |
570 | #define HP100_ALN_ERR 0x0010 /* 0:No, 1:Yes align error. */ | |
571 | #define HP100_CRC_ERR 0x0008 /* 0:No, 1:Yes CRC occurred. */ | |
572 | ||
573 | /* The last three bits indicate the type of destination address */ | |
574 | ||
575 | #define HP100_MULTI_ADDR_HASH 0x0006 /* 110: Addr multicast, matched hash */ | |
576 | #define HP100_BROADCAST_ADDR 0x0003 /* x11: Addr broadcast */ | |
577 | #define HP100_MULTI_ADDR_NO_HASH 0x0002 /* 010: Addr multicast, didn't match hash */ | |
578 | #define HP100_PHYS_ADDR_MATCH 0x0001 /* x01: Addr was physical and mine */ | |
579 | #define HP100_PHYS_ADDR_NO_MATCH 0x0000 /* x00: Addr was physical but not mine */ | |
580 | ||
581 | /* | |
582 | * macros | |
583 | */ | |
584 | ||
585 | #define hp100_inb( reg ) \ | |
586 | inb( ioaddr + HP100_REG_##reg ) | |
587 | #define hp100_inw( reg ) \ | |
588 | inw( ioaddr + HP100_REG_##reg ) | |
589 | #define hp100_inl( reg ) \ | |
590 | inl( ioaddr + HP100_REG_##reg ) | |
591 | #define hp100_outb( data, reg ) \ | |
592 | outb( data, ioaddr + HP100_REG_##reg ) | |
593 | #define hp100_outw( data, reg ) \ | |
594 | outw( data, ioaddr + HP100_REG_##reg ) | |
595 | #define hp100_outl( data, reg ) \ | |
596 | outl( data, ioaddr + HP100_REG_##reg ) | |
597 | #define hp100_orb( data, reg ) \ | |
598 | outb( inb( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg ) | |
599 | #define hp100_orw( data, reg ) \ | |
600 | outw( inw( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg ) | |
601 | #define hp100_andb( data, reg ) \ | |
602 | outb( inb( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg ) | |
603 | #define hp100_andw( data, reg ) \ | |
604 | outw( inw( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg ) | |
605 | ||
606 | #define hp100_page( page ) \ | |
607 | outw( HP100_PAGE_##page, ioaddr + HP100_REG_PAGING ) | |
608 | #define hp100_ints_off() \ | |
609 | outw( HP100_INT_EN | HP100_RESET_LB, ioaddr + HP100_REG_OPTION_LSW ) | |
610 | #define hp100_ints_on() \ | |
611 | outw( HP100_INT_EN | HP100_SET_LB, ioaddr + HP100_REG_OPTION_LSW ) | |
612 | #define hp100_mem_map_enable() \ | |
613 | outw( HP100_MMAP_DIS | HP100_RESET_HB, ioaddr + HP100_REG_OPTION_LSW ) | |
614 | #define hp100_mem_map_disable() \ | |
615 | outw( HP100_MMAP_DIS | HP100_SET_HB, ioaddr + HP100_REG_OPTION_LSW ) |