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a6a53252 JY |
1 | /* |
2 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. | |
3 | * | |
4 | * Derived from Intel e1000 driver | |
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the Free | |
9 | * Software Foundation; either version 2 of the License, or (at your option) | |
10 | * any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #ifndef _ATHL1E_HW_H_ | |
23 | #define _ATHL1E_HW_H_ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/mii.h> | |
27 | ||
28 | struct atl1e_adapter; | |
29 | struct atl1e_hw; | |
30 | ||
31 | /* function prototype */ | |
32 | s32 atl1e_reset_hw(struct atl1e_hw *hw); | |
33 | s32 atl1e_read_mac_addr(struct atl1e_hw *hw); | |
34 | s32 atl1e_init_hw(struct atl1e_hw *hw); | |
35 | s32 atl1e_phy_commit(struct atl1e_hw *hw); | |
36 | s32 atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex); | |
37 | u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex); | |
38 | u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr); | |
39 | void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value); | |
40 | s32 atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data); | |
41 | s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data); | |
42 | s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw); | |
43 | void atl1e_hw_set_mac_addr(struct atl1e_hw *hw); | |
44 | bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value); | |
45 | bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value); | |
46 | s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw); | |
47 | s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw); | |
48 | s32 atl1e_phy_init(struct atl1e_hw *hw); | |
49 | int atl1e_check_eeprom_exist(struct atl1e_hw *hw); | |
50 | void atl1e_force_ps(struct atl1e_hw *hw); | |
51 | s32 atl1e_restart_autoneg(struct atl1e_hw *hw); | |
52 | ||
53 | /* register definition */ | |
54 | #define REG_PM_CTRLSTAT 0x44 | |
55 | ||
56 | #define REG_PCIE_CAP_LIST 0x58 | |
57 | ||
58 | #define REG_DEVICE_CAP 0x5C | |
59 | #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 | |
60 | #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 | |
61 | ||
62 | #define REG_DEVICE_CTRL 0x60 | |
63 | #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7 | |
64 | #define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5 | |
65 | #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7 | |
66 | #define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12 | |
67 | ||
68 | #define REG_VPD_CAP 0x6C | |
69 | #define VPD_CAP_ID_MASK 0xff | |
70 | #define VPD_CAP_ID_SHIFT 0 | |
71 | #define VPD_CAP_NEXT_PTR_MASK 0xFF | |
72 | #define VPD_CAP_NEXT_PTR_SHIFT 8 | |
73 | #define VPD_CAP_VPD_ADDR_MASK 0x7FFF | |
74 | #define VPD_CAP_VPD_ADDR_SHIFT 16 | |
75 | #define VPD_CAP_VPD_FLAG 0x80000000 | |
76 | ||
77 | #define REG_VPD_DATA 0x70 | |
78 | ||
79 | #define REG_SPI_FLASH_CTRL 0x200 | |
80 | #define SPI_FLASH_CTRL_STS_NON_RDY 0x1 | |
81 | #define SPI_FLASH_CTRL_STS_WEN 0x2 | |
82 | #define SPI_FLASH_CTRL_STS_WPEN 0x80 | |
83 | #define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF | |
84 | #define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 | |
85 | #define SPI_FLASH_CTRL_INS_MASK 0x7 | |
86 | #define SPI_FLASH_CTRL_INS_SHIFT 8 | |
87 | #define SPI_FLASH_CTRL_START 0x800 | |
88 | #define SPI_FLASH_CTRL_EN_VPD 0x2000 | |
89 | #define SPI_FLASH_CTRL_LDSTART 0x8000 | |
90 | #define SPI_FLASH_CTRL_CS_HI_MASK 0x3 | |
91 | #define SPI_FLASH_CTRL_CS_HI_SHIFT 16 | |
92 | #define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 | |
93 | #define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 | |
94 | #define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 | |
95 | #define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 | |
96 | #define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 | |
97 | #define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 | |
98 | #define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 | |
99 | #define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 | |
100 | #define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 | |
101 | #define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 | |
102 | #define SPI_FLASH_CTRL_WAIT_READY 0x10000000 | |
103 | ||
104 | #define REG_SPI_ADDR 0x204 | |
105 | ||
106 | #define REG_SPI_DATA 0x208 | |
107 | ||
108 | #define REG_SPI_FLASH_CONFIG 0x20C | |
109 | #define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF | |
110 | #define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 | |
111 | #define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 | |
112 | #define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 | |
113 | #define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 | |
114 | ||
115 | ||
116 | #define REG_SPI_FLASH_OP_PROGRAM 0x210 | |
117 | #define REG_SPI_FLASH_OP_SC_ERASE 0x211 | |
118 | #define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 | |
119 | #define REG_SPI_FLASH_OP_RDID 0x213 | |
120 | #define REG_SPI_FLASH_OP_WREN 0x214 | |
121 | #define REG_SPI_FLASH_OP_RDSR 0x215 | |
122 | #define REG_SPI_FLASH_OP_WRSR 0x216 | |
123 | #define REG_SPI_FLASH_OP_READ 0x217 | |
124 | ||
125 | #define REG_TWSI_CTRL 0x218 | |
126 | #define TWSI_CTRL_LD_OFFSET_MASK 0xFF | |
127 | #define TWSI_CTRL_LD_OFFSET_SHIFT 0 | |
128 | #define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 | |
129 | #define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 | |
130 | #define TWSI_CTRL_SW_LDSTART 0x800 | |
131 | #define TWSI_CTRL_HW_LDSTART 0x1000 | |
132 | #define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F | |
133 | #define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 | |
134 | #define TWSI_CTRL_LD_EXIST 0x400000 | |
135 | #define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 | |
136 | #define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 | |
137 | #define TWSI_CTRL_FREQ_SEL_100K 0 | |
138 | #define TWSI_CTRL_FREQ_SEL_200K 1 | |
139 | #define TWSI_CTRL_FREQ_SEL_300K 2 | |
140 | #define TWSI_CTRL_FREQ_SEL_400K 3 | |
141 | #define TWSI_CTRL_SMB_SLV_ADDR | |
142 | #define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 | |
143 | #define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 | |
144 | ||
145 | ||
146 | #define REG_PCIE_DEV_MISC_CTRL 0x21C | |
147 | #define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 | |
148 | #define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 | |
149 | #define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 | |
150 | #define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 | |
151 | #define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 | |
152 | ||
153 | #define REG_PCIE_PHYMISC 0x1000 | |
154 | #define PCIE_PHYMISC_FORCE_RCV_DET 0x4 | |
155 | ||
156 | #define REG_LTSSM_TEST_MODE 0x12FC | |
157 | #define LTSSM_TEST_MODE_DEF 0xE000 | |
158 | ||
159 | /* Selene Master Control Register */ | |
160 | #define REG_MASTER_CTRL 0x1400 | |
161 | #define MASTER_CTRL_SOFT_RST 0x1 | |
162 | #define MASTER_CTRL_MTIMER_EN 0x2 | |
163 | #define MASTER_CTRL_ITIMER_EN 0x4 | |
164 | #define MASTER_CTRL_MANUAL_INT 0x8 | |
165 | #define MASTER_CTRL_ITIMER2_EN 0x20 | |
166 | #define MASTER_CTRL_INT_RDCLR 0x40 | |
167 | #define MASTER_CTRL_LED_MODE 0x200 | |
168 | #define MASTER_CTRL_REV_NUM_SHIFT 16 | |
169 | #define MASTER_CTRL_REV_NUM_MASK 0xff | |
170 | #define MASTER_CTRL_DEV_ID_SHIFT 24 | |
171 | #define MASTER_CTRL_DEV_ID_MASK 0xff | |
172 | ||
173 | /* Timer Initial Value Register */ | |
174 | #define REG_MANUAL_TIMER_INIT 0x1404 | |
175 | ||
176 | ||
177 | /* IRQ ModeratorTimer Initial Value Register */ | |
178 | #define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */ | |
179 | #define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */ | |
180 | ||
181 | ||
182 | #define REG_GPHY_CTRL 0x140C | |
183 | #define GPHY_CTRL_EXT_RESET 1 | |
184 | #define GPHY_CTRL_PIPE_MOD 2 | |
185 | #define GPHY_CTRL_TEST_MODE_MASK 3 | |
186 | #define GPHY_CTRL_TEST_MODE_SHIFT 2 | |
187 | #define GPHY_CTRL_BERT_START 0x10 | |
188 | #define GPHY_CTRL_GATE_25M_EN 0x20 | |
189 | #define GPHY_CTRL_LPW_EXIT 0x40 | |
190 | #define GPHY_CTRL_PHY_IDDQ 0x80 | |
191 | #define GPHY_CTRL_PHY_IDDQ_DIS 0x100 | |
192 | #define GPHY_CTRL_PCLK_SEL_DIS 0x200 | |
193 | #define GPHY_CTRL_HIB_EN 0x400 | |
194 | #define GPHY_CTRL_HIB_PULSE 0x800 | |
195 | #define GPHY_CTRL_SEL_ANA_RST 0x1000 | |
196 | #define GPHY_CTRL_PHY_PLL_ON 0x2000 | |
197 | #define GPHY_CTRL_PWDOWN_HW 0x4000 | |
198 | #define GPHY_CTRL_DEFAULT (\ | |
199 | GPHY_CTRL_PHY_PLL_ON |\ | |
200 | GPHY_CTRL_SEL_ANA_RST |\ | |
201 | GPHY_CTRL_HIB_PULSE |\ | |
202 | GPHY_CTRL_HIB_EN) | |
203 | ||
204 | #define GPHY_CTRL_PW_WOL_DIS (\ | |
205 | GPHY_CTRL_PHY_PLL_ON |\ | |
206 | GPHY_CTRL_SEL_ANA_RST |\ | |
207 | GPHY_CTRL_HIB_PULSE |\ | |
208 | GPHY_CTRL_HIB_EN |\ | |
209 | GPHY_CTRL_PWDOWN_HW |\ | |
210 | GPHY_CTRL_PCLK_SEL_DIS |\ | |
211 | GPHY_CTRL_PHY_IDDQ) | |
212 | ||
213 | /* IRQ Anti-Lost Timer Initial Value Register */ | |
214 | #define REG_CMBDISDMA_TIMER 0x140E | |
215 | ||
216 | ||
217 | /* Block IDLE Status Register */ | |
218 | #define REG_IDLE_STATUS 0x1410 | |
219 | #define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */ | |
220 | #define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */ | |
221 | #define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */ | |
222 | #define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */ | |
223 | #define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */ | |
224 | #define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */ | |
225 | #define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */ | |
226 | #define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */ | |
227 | ||
228 | /* MDIO Control Register */ | |
229 | #define REG_MDIO_CTRL 0x1414 | |
230 | #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */ | |
231 | #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/ | |
232 | #define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */ | |
233 | #define MDIO_REG_ADDR_SHIFT 16 | |
234 | #define MDIO_RW 0x200000 /* 1: read, 0: write */ | |
235 | #define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */ | |
236 | #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/ | |
237 | #define MDIO_CLK_SEL_SHIFT 24 | |
238 | #define MDIO_CLK_25_4 0 | |
239 | #define MDIO_CLK_25_6 2 | |
240 | #define MDIO_CLK_25_8 3 | |
241 | #define MDIO_CLK_25_10 4 | |
242 | #define MDIO_CLK_25_14 5 | |
243 | #define MDIO_CLK_25_20 6 | |
244 | #define MDIO_CLK_25_28 7 | |
245 | #define MDIO_BUSY 0x8000000 | |
246 | #define MDIO_AP_EN 0x10000000 | |
247 | #define MDIO_WAIT_TIMES 10 | |
248 | ||
249 | /* MII PHY Status Register */ | |
250 | #define REG_PHY_STATUS 0x1418 | |
251 | #define PHY_STATUS_100M 0x20000 | |
252 | #define PHY_STATUS_EMI_CA 0x40000 | |
253 | ||
254 | /* BIST Control and Status Register0 (for the Packet Memory) */ | |
255 | #define REG_BIST0_CTRL 0x141c | |
256 | #define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */ | |
257 | /* BIST process and reset to zero when BIST is done */ | |
258 | #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */ | |
259 | /* decoder failure or more than 1 cell stuck-to-x failure */ | |
260 | #define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */ | |
261 | ||
262 | /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ | |
263 | #define REG_BIST1_CTRL 0x1420 | |
264 | #define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */ | |
265 | /* BIST process and reset to zero when BIST is done */ | |
266 | #define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */ | |
267 | /* decoder failure or more than 1 cell stuck-to-x failure.*/ | |
268 | #define BIST1_FUSE_FLAG 0x4 | |
269 | ||
270 | /* SerDes Lock Detect Control and Status Register */ | |
271 | #define REG_SERDES_LOCK 0x1424 | |
272 | #define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */ | |
273 | #define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */ | |
274 | ||
275 | /* MAC Control Register */ | |
276 | #define REG_MAC_CTRL 0x1480 | |
277 | #define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */ | |
278 | #define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */ | |
279 | #define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */ | |
280 | #define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */ | |
281 | #define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */ | |
282 | #define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */ | |
283 | #define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */ | |
284 | #define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */ | |
285 | #define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */ | |
286 | #define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */ | |
287 | #define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */ | |
288 | #define MAC_CTRL_PRMLEN_MASK 0xf | |
289 | #define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */ | |
290 | #define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */ | |
291 | #define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */ | |
292 | #define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */ | |
293 | #define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */ | |
294 | #define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */ | |
295 | #define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */ | |
296 | #define MAC_CTRL_SPEED_MASK 0x300000 | |
297 | #define MAC_CTRL_SPEED_1000 2 | |
298 | #define MAC_CTRL_SPEED_10_100 1 | |
299 | #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */ | |
300 | #define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */ | |
301 | #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */ | |
302 | #define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */ | |
303 | #define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */ | |
304 | #define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */ | |
305 | ||
306 | /* MAC IPG/IFG Control Register */ | |
307 | #define REG_MAC_IPG_IFG 0x1484 | |
308 | #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */ | |
309 | #define MAC_IPG_IFG_IPGT_MASK 0x7f | |
310 | #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */ | |
311 | #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ | |
312 | #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ | |
313 | #define MAC_IPG_IFG_IPGR1_MASK 0x7f | |
314 | #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ | |
315 | #define MAC_IPG_IFG_IPGR2_MASK 0x7f | |
316 | ||
317 | /* MAC STATION ADDRESS */ | |
318 | #define REG_MAC_STA_ADDR 0x1488 | |
319 | ||
320 | /* Hash table for multicast address */ | |
321 | #define REG_RX_HASH_TABLE 0x1490 | |
322 | ||
323 | ||
324 | /* MAC Half-Duplex Control Register */ | |
325 | #define REG_MAC_HALF_DUPLX_CTRL 0x1498 | |
326 | #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ | |
327 | #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff | |
328 | #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */ | |
329 | #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf | |
330 | #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */ | |
331 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */ | |
332 | #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */ | |
333 | #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ | |
334 | #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ | |
335 | #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf | |
336 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ | |
337 | #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ | |
338 | ||
339 | /* Maximum Frame Length Control Register */ | |
340 | #define REG_MTU 0x149c | |
341 | ||
342 | /* Wake-On-Lan control register */ | |
343 | #define REG_WOL_CTRL 0x14a0 | |
344 | #define WOL_PATTERN_EN 0x00000001 | |
345 | #define WOL_PATTERN_PME_EN 0x00000002 | |
346 | #define WOL_MAGIC_EN 0x00000004 | |
347 | #define WOL_MAGIC_PME_EN 0x00000008 | |
348 | #define WOL_LINK_CHG_EN 0x00000010 | |
349 | #define WOL_LINK_CHG_PME_EN 0x00000020 | |
350 | #define WOL_PATTERN_ST 0x00000100 | |
351 | #define WOL_MAGIC_ST 0x00000200 | |
352 | #define WOL_LINKCHG_ST 0x00000400 | |
353 | #define WOL_CLK_SWITCH_EN 0x00008000 | |
354 | #define WOL_PT0_EN 0x00010000 | |
355 | #define WOL_PT1_EN 0x00020000 | |
356 | #define WOL_PT2_EN 0x00040000 | |
357 | #define WOL_PT3_EN 0x00080000 | |
358 | #define WOL_PT4_EN 0x00100000 | |
359 | #define WOL_PT5_EN 0x00200000 | |
360 | #define WOL_PT6_EN 0x00400000 | |
361 | /* WOL Length ( 2 DWORD ) */ | |
362 | #define REG_WOL_PATTERN_LEN 0x14a4 | |
363 | #define WOL_PT_LEN_MASK 0x7f | |
364 | #define WOL_PT0_LEN_SHIFT 0 | |
365 | #define WOL_PT1_LEN_SHIFT 8 | |
366 | #define WOL_PT2_LEN_SHIFT 16 | |
367 | #define WOL_PT3_LEN_SHIFT 24 | |
368 | #define WOL_PT4_LEN_SHIFT 0 | |
369 | #define WOL_PT5_LEN_SHIFT 8 | |
370 | #define WOL_PT6_LEN_SHIFT 16 | |
371 | ||
372 | /* Internal SRAM Partition Register */ | |
373 | #define REG_SRAM_TRD_ADDR 0x1518 | |
374 | #define REG_SRAM_TRD_LEN 0x151C | |
375 | #define REG_SRAM_RXF_ADDR 0x1520 | |
376 | #define REG_SRAM_RXF_LEN 0x1524 | |
377 | #define REG_SRAM_TXF_ADDR 0x1528 | |
378 | #define REG_SRAM_TXF_LEN 0x152C | |
379 | #define REG_SRAM_TCPH_ADDR 0x1530 | |
380 | #define REG_SRAM_PKTH_ADDR 0x1532 | |
381 | ||
382 | /* Load Ptr Register */ | |
383 | #define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */ | |
384 | ||
385 | /* | |
386 | * addresses of all descriptors, as well as the following descriptor | |
387 | * control register, which triggers each function block to load the head | |
388 | * pointer to prepare for the operation. This bit is then self-cleared | |
389 | * after one cycle. | |
390 | */ | |
391 | ||
392 | /* Descriptor Control register */ | |
393 | #define REG_RXF3_BASE_ADDR_HI 0x153C | |
394 | #define REG_DESC_BASE_ADDR_HI 0x1540 | |
395 | #define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */ | |
396 | #define REG_HOST_RXF0_PAGE0_LO 0x1544 | |
397 | #define REG_HOST_RXF0_PAGE1_LO 0x1548 | |
398 | #define REG_TPD_BASE_ADDR_LO 0x154C | |
399 | #define REG_RXF1_BASE_ADDR_HI 0x1550 | |
400 | #define REG_RXF2_BASE_ADDR_HI 0x1554 | |
401 | #define REG_HOST_RXFPAGE_SIZE 0x1558 | |
402 | #define REG_TPD_RING_SIZE 0x155C | |
403 | /* RSS about */ | |
404 | #define REG_RSS_KEY0 0x14B0 | |
405 | #define REG_RSS_KEY1 0x14B4 | |
406 | #define REG_RSS_KEY2 0x14B8 | |
407 | #define REG_RSS_KEY3 0x14BC | |
408 | #define REG_RSS_KEY4 0x14C0 | |
409 | #define REG_RSS_KEY5 0x14C4 | |
410 | #define REG_RSS_KEY6 0x14C8 | |
411 | #define REG_RSS_KEY7 0x14CC | |
412 | #define REG_RSS_KEY8 0x14D0 | |
413 | #define REG_RSS_KEY9 0x14D4 | |
414 | #define REG_IDT_TABLE4 0x14E0 | |
415 | #define REG_IDT_TABLE5 0x14E4 | |
416 | #define REG_IDT_TABLE6 0x14E8 | |
417 | #define REG_IDT_TABLE7 0x14EC | |
418 | #define REG_IDT_TABLE0 0x1560 | |
419 | #define REG_IDT_TABLE1 0x1564 | |
420 | #define REG_IDT_TABLE2 0x1568 | |
421 | #define REG_IDT_TABLE3 0x156C | |
422 | #define REG_IDT_TABLE REG_IDT_TABLE0 | |
423 | #define REG_RSS_HASH_VALUE 0x1570 | |
424 | #define REG_RSS_HASH_FLAG 0x1574 | |
425 | #define REG_BASE_CPU_NUMBER 0x157C | |
426 | ||
427 | ||
428 | /* TXQ Control Register */ | |
429 | #define REG_TXQ_CTRL 0x1580 | |
430 | #define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF | |
431 | #define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0 | |
432 | #define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */ | |
433 | #define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */ | |
434 | #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */ | |
435 | #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff | |
436 | ||
437 | /* Jumbo packet Threshold for task offload */ | |
438 | #define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */ | |
439 | /* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */ | |
440 | #define TX_TX_EARLY_TH_MASK 0x7ff | |
441 | #define TX_TX_EARLY_TH_SHIFT 0 | |
442 | ||
443 | ||
444 | /* RXQ Control Register */ | |
445 | #define REG_RXQ_CTRL 0x15A0 | |
446 | #define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */ | |
447 | #define RXQ_CTRL_PBA_ALIGN_64 1 | |
448 | #define RXQ_CTRL_PBA_ALIGN_128 2 | |
449 | #define RXQ_CTRL_PBA_ALIGN_256 3 | |
450 | #define RXQ_CTRL_Q1_EN 0x10 | |
451 | #define RXQ_CTRL_Q2_EN 0x20 | |
452 | #define RXQ_CTRL_Q3_EN 0x40 | |
453 | #define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80 | |
454 | #define RXQ_CTRL_HASH_TLEN_SHIFT 8 | |
455 | #define RXQ_CTRL_HASH_TLEN_MASK 0xFF | |
456 | #define RXQ_CTRL_HASH_TYPE_IPV4 0x10000 | |
457 | #define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000 | |
458 | #define RXQ_CTRL_HASH_TYPE_IPV6 0x40000 | |
459 | #define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000 | |
460 | #define RXQ_CTRL_RSS_MODE_DISABLE 0 | |
461 | #define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000 | |
462 | #define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000 | |
463 | #define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000 | |
464 | #define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000 | |
465 | #define RXQ_CTRL_HASH_ENABLE 0x20000000 | |
466 | #define RXQ_CTRL_CUT_THRU_EN 0x40000000 | |
467 | #define RXQ_CTRL_EN 0x80000000 | |
468 | ||
469 | /* Rx jumbo packet threshold and rrd retirement timer */ | |
470 | #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4 | |
471 | /* | |
472 | * Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit. | |
473 | * When the packet length greater than or equal to this value, RXQ | |
474 | * shall start cut-through forwarding of the received packet. | |
475 | */ | |
476 | #define RXQ_JMBOSZ_TH_MASK 0x7ff | |
477 | #define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/ | |
478 | #define RXQ_JMBO_LKAH_MASK 0xf | |
479 | #define RXQ_JMBO_LKAH_SHIFT 11 | |
480 | ||
481 | /* RXF flow control register */ | |
482 | #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 | |
483 | #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 | |
484 | #define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff | |
485 | #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 | |
486 | #define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff | |
487 | ||
488 | ||
489 | /* DMA Engine Control Register */ | |
490 | #define REG_DMA_CTRL 0x15C0 | |
491 | #define DMA_CTRL_DMAR_IN_ORDER 0x1 | |
492 | #define DMA_CTRL_DMAR_ENH_ORDER 0x2 | |
493 | #define DMA_CTRL_DMAR_OUT_ORDER 0x4 | |
494 | #define DMA_CTRL_RCB_VALUE 0x8 | |
495 | #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 | |
496 | #define DMA_CTRL_DMAR_BURST_LEN_MASK 7 | |
497 | #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 | |
498 | #define DMA_CTRL_DMAW_BURST_LEN_MASK 7 | |
499 | #define DMA_CTRL_DMAR_REQ_PRI 0x400 | |
500 | #define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F | |
501 | #define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11 | |
502 | #define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF | |
503 | #define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16 | |
504 | #define DMA_CTRL_TXCMB_EN 0x100000 | |
505 | #define DMA_CTRL_RXCMB_EN 0x200000 | |
506 | ||
507 | ||
508 | /* CMB/SMB Control Register */ | |
509 | #define REG_SMB_STAT_TIMER 0x15C4 | |
510 | #define REG_TRIG_RRD_THRESH 0x15CA | |
511 | #define REG_TRIG_TPD_THRESH 0x15C8 | |
512 | #define REG_TRIG_TXTIMER 0x15CC | |
513 | #define REG_TRIG_RXTIMER 0x15CE | |
514 | ||
515 | /* HOST RXF Page 1,2,3 address */ | |
516 | #define REG_HOST_RXF1_PAGE0_LO 0x15D0 | |
517 | #define REG_HOST_RXF1_PAGE1_LO 0x15D4 | |
518 | #define REG_HOST_RXF2_PAGE0_LO 0x15D8 | |
519 | #define REG_HOST_RXF2_PAGE1_LO 0x15DC | |
520 | #define REG_HOST_RXF3_PAGE0_LO 0x15E0 | |
521 | #define REG_HOST_RXF3_PAGE1_LO 0x15E4 | |
522 | ||
523 | /* Mail box */ | |
524 | #define REG_MB_RXF1_RADDR 0x15B4 | |
525 | #define REG_MB_RXF2_RADDR 0x15B8 | |
526 | #define REG_MB_RXF3_RADDR 0x15BC | |
527 | #define REG_MB_TPD_PROD_IDX 0x15F0 | |
528 | ||
529 | /* RXF-Page 0-3 PageNo & Valid bit */ | |
530 | #define REG_HOST_RXF0_PAGE0_VLD 0x15F4 | |
531 | #define HOST_RXF_VALID 1 | |
532 | #define HOST_RXF_PAGENO_SHIFT 1 | |
533 | #define HOST_RXF_PAGENO_MASK 0x7F | |
534 | #define REG_HOST_RXF0_PAGE1_VLD 0x15F5 | |
535 | #define REG_HOST_RXF1_PAGE0_VLD 0x15F6 | |
536 | #define REG_HOST_RXF1_PAGE1_VLD 0x15F7 | |
537 | #define REG_HOST_RXF2_PAGE0_VLD 0x15F8 | |
538 | #define REG_HOST_RXF2_PAGE1_VLD 0x15F9 | |
539 | #define REG_HOST_RXF3_PAGE0_VLD 0x15FA | |
540 | #define REG_HOST_RXF3_PAGE1_VLD 0x15FB | |
541 | ||
542 | /* Interrupt Status Register */ | |
543 | #define REG_ISR 0x1600 | |
544 | #define ISR_SMB 1 | |
545 | #define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */ | |
546 | /* | |
547 | * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set | |
548 | * in Table 51 Selene Master Control Register (Offset 0x1400). | |
549 | */ | |
550 | #define ISR_MANUAL 4 | |
551 | #define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */ | |
552 | #define ISR_HOST_RXF0_OV 0x10 | |
553 | #define ISR_HOST_RXF1_OV 0x20 | |
554 | #define ISR_HOST_RXF2_OV 0x40 | |
555 | #define ISR_HOST_RXF3_OV 0x80 | |
556 | #define ISR_TXF_UN 0x100 | |
557 | #define ISR_RX0_PAGE_FULL 0x200 | |
558 | #define ISR_DMAR_TO_RST 0x400 | |
559 | #define ISR_DMAW_TO_RST 0x800 | |
560 | #define ISR_GPHY 0x1000 | |
561 | #define ISR_TX_CREDIT 0x2000 | |
562 | #define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */ | |
563 | #define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */ | |
564 | #define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */ | |
565 | #define ISR_TX_DMA 0x40000 | |
566 | #define ISR_RX_PKT_1 0x80000 | |
567 | #define ISR_RX_PKT_2 0x100000 | |
568 | #define ISR_RX_PKT_3 0x200000 | |
569 | #define ISR_MAC_RX 0x400000 | |
570 | #define ISR_MAC_TX 0x800000 | |
571 | #define ISR_UR_DETECTED 0x1000000 | |
572 | #define ISR_FERR_DETECTED 0x2000000 | |
573 | #define ISR_NFERR_DETECTED 0x4000000 | |
574 | #define ISR_CERR_DETECTED 0x8000000 | |
575 | #define ISR_PHY_LINKDOWN 0x10000000 | |
576 | #define ISR_DIS_INT 0x80000000 | |
577 | ||
578 | ||
579 | /* Interrupt Mask Register */ | |
580 | #define REG_IMR 0x1604 | |
581 | ||
582 | ||
583 | #define IMR_NORMAL_MASK (\ | |
584 | ISR_SMB |\ | |
585 | ISR_TXF_UN |\ | |
586 | ISR_HW_RXF_OV |\ | |
587 | ISR_HOST_RXF0_OV|\ | |
588 | ISR_MANUAL |\ | |
589 | ISR_GPHY |\ | |
590 | ISR_GPHY_LPW |\ | |
591 | ISR_DMAR_TO_RST |\ | |
592 | ISR_DMAW_TO_RST |\ | |
593 | ISR_PHY_LINKDOWN|\ | |
594 | ISR_RX_PKT |\ | |
595 | ISR_TX_PKT) | |
596 | ||
597 | #define ISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT) | |
598 | #define ISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT) | |
599 | ||
600 | #define REG_MAC_RX_STATUS_BIN 0x1700 | |
601 | #define REG_MAC_RX_STATUS_END 0x175c | |
602 | #define REG_MAC_TX_STATUS_BIN 0x1760 | |
603 | #define REG_MAC_TX_STATUS_END 0x17c0 | |
604 | ||
605 | /* Hardware Offset Register */ | |
606 | #define REG_HOST_RXF0_PAGEOFF 0x1800 | |
607 | #define REG_TPD_CONS_IDX 0x1804 | |
608 | #define REG_HOST_RXF1_PAGEOFF 0x1808 | |
609 | #define REG_HOST_RXF2_PAGEOFF 0x180C | |
610 | #define REG_HOST_RXF3_PAGEOFF 0x1810 | |
611 | ||
612 | /* RXF-Page 0-3 Offset DMA Address */ | |
613 | #define REG_HOST_RXF0_MB0_LO 0x1820 | |
614 | #define REG_HOST_RXF0_MB1_LO 0x1824 | |
615 | #define REG_HOST_RXF1_MB0_LO 0x1828 | |
616 | #define REG_HOST_RXF1_MB1_LO 0x182C | |
617 | #define REG_HOST_RXF2_MB0_LO 0x1830 | |
618 | #define REG_HOST_RXF2_MB1_LO 0x1834 | |
619 | #define REG_HOST_RXF3_MB0_LO 0x1838 | |
620 | #define REG_HOST_RXF3_MB1_LO 0x183C | |
621 | ||
622 | /* Tpd CMB DMA Address */ | |
623 | #define REG_HOST_TX_CMB_LO 0x1840 | |
624 | #define REG_HOST_SMB_ADDR_LO 0x1844 | |
625 | ||
626 | /* DEBUG ADDR */ | |
627 | #define REG_DEBUG_DATA0 0x1900 | |
628 | #define REG_DEBUG_DATA1 0x1904 | |
629 | ||
630 | /***************************** MII definition ***************************************/ | |
631 | /* PHY Common Register */ | |
632 | #define MII_BMCR 0x00 | |
633 | #define MII_BMSR 0x01 | |
634 | #define MII_PHYSID1 0x02 | |
635 | #define MII_PHYSID2 0x03 | |
636 | #define MII_ADVERTISE 0x04 | |
637 | #define MII_LPA 0x05 | |
638 | #define MII_EXPANSION 0x06 | |
639 | #define MII_AT001_CR 0x09 | |
640 | #define MII_AT001_SR 0x0A | |
641 | #define MII_AT001_ESR 0x0F | |
642 | #define MII_AT001_PSCR 0x10 | |
643 | #define MII_AT001_PSSR 0x11 | |
644 | #define MII_INT_CTRL 0x12 | |
645 | #define MII_INT_STATUS 0x13 | |
646 | #define MII_SMARTSPEED 0x14 | |
647 | #define MII_RERRCOUNTER 0x15 | |
648 | #define MII_SREVISION 0x16 | |
649 | #define MII_RESV1 0x17 | |
650 | #define MII_LBRERROR 0x18 | |
651 | #define MII_PHYADDR 0x19 | |
652 | #define MII_RESV2 0x1a | |
653 | #define MII_TPISTATUS 0x1b | |
654 | #define MII_NCONFIG 0x1c | |
655 | ||
656 | #define MII_DBG_ADDR 0x1D | |
657 | #define MII_DBG_DATA 0x1E | |
658 | ||
659 | ||
660 | /* PHY Control Register */ | |
661 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
662 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | |
663 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | |
664 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | |
665 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | |
666 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | |
667 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | |
668 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | |
669 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | |
670 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | |
671 | #define MII_CR_SPEED_MASK 0x2040 | |
672 | #define MII_CR_SPEED_1000 0x0040 | |
673 | #define MII_CR_SPEED_100 0x2000 | |
674 | #define MII_CR_SPEED_10 0x0000 | |
675 | ||
676 | ||
677 | /* PHY Status Register */ | |
678 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | |
679 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | |
680 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | |
681 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | |
682 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | |
683 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | |
684 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | |
685 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | |
686 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | |
687 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | |
688 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | |
689 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | |
690 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | |
691 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | |
692 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | |
693 | ||
694 | /* Link partner ability register. */ | |
695 | #define MII_LPA_SLCT 0x001f /* Same as advertise selector */ | |
696 | #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ | |
697 | #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ | |
698 | #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ | |
699 | #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ | |
700 | #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ | |
701 | #define MII_LPA_PAUSE 0x0400 /* PAUSE */ | |
702 | #define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ | |
703 | #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ | |
704 | #define MII_LPA_LPACK 0x4000 /* Link partner acked us */ | |
705 | #define MII_LPA_NPAGE 0x8000 /* Next page bit */ | |
706 | ||
707 | /* Autoneg Advertisement Register */ | |
708 | #define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ | |
709 | #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | |
710 | #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | |
711 | #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | |
712 | #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | |
713 | #define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ | |
714 | #define MII_AR_PAUSE 0x0400 /* Pause operation desired */ | |
715 | #define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | |
716 | #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ | |
717 | #define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | |
718 | #define MII_AR_SPEED_MASK 0x01E0 | |
719 | #define MII_AR_DEFAULT_CAP_MASK 0x0DE0 | |
720 | ||
721 | /* 1000BASE-T Control Register */ | |
722 | #define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | |
723 | #define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | |
724 | #define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ | |
725 | /* 0=DTE device */ | |
726 | #define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ | |
727 | /* 0=Configure PHY as Slave */ | |
728 | #define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | |
729 | /* 0=Automatic Master/Slave config */ | |
730 | #define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | |
731 | #define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | |
732 | #define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | |
733 | #define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | |
734 | #define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | |
735 | #define MII_AT001_CR_1000T_SPEED_MASK 0x0300 | |
736 | #define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300 | |
737 | ||
738 | /* 1000BASE-T Status Register */ | |
739 | #define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ | |
740 | #define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ | |
741 | #define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | |
742 | #define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | |
743 | #define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ | |
744 | #define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ | |
745 | #define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 | |
746 | #define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 | |
747 | ||
748 | /* Extended Status Register */ | |
749 | #define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ | |
750 | #define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ | |
751 | #define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ | |
752 | #define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ | |
753 | ||
754 | /* AT001 PHY Specific Control Register */ | |
755 | #define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ | |
756 | #define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | |
757 | #define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ | |
758 | #define MII_AT001_PSCR_MAC_POWERDOWN 0x0008 | |
759 | #define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, | |
760 | * 0=CLK125 toggling | |
761 | */ | |
762 | #define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ | |
763 | /* Manual MDI configuration */ | |
764 | #define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | |
765 | #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, | |
766 | * 100BASE-TX/10BASE-T: | |
767 | * MDI Mode | |
768 | */ | |
769 | #define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled | |
770 | * all speeds. | |
771 | */ | |
772 | #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 | |
773 | /* 1=Enable Extended 10BASE-T distance | |
774 | * (Lower 10BASE-T RX Threshold) | |
775 | * 0=Normal 10BASE-T RX Threshold */ | |
776 | #define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 | |
777 | /* 1=5-Bit interface in 100BASE-TX | |
778 | * 0=MII interface in 100BASE-TX */ | |
779 | #define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ | |
780 | #define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ | |
781 | #define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | |
782 | #define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1 | |
783 | #define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5 | |
784 | #define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 | |
785 | /* AT001 PHY Specific Status Register */ | |
786 | #define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ | |
787 | #define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ | |
788 | #define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | |
789 | #define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */ | |
790 | #define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */ | |
791 | #define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | |
792 | ||
793 | #endif /*_ATHL1E_HW_H_*/ |