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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This software may be redistributed and/or modified under | |
6 | * the terms of the GNU General Public License as published by the Free | |
7 | * Software Foundation; either version 2 of the License, or | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * File: via-velocity.h | |
16 | * | |
17 | * Purpose: Header file to define driver's private structures. | |
18 | * | |
19 | * Author: Chuang Liang-Shing, AJ Jiang | |
20 | * | |
21 | * Date: Jan 24, 2003 | |
22 | */ | |
23 | ||
24 | ||
25 | #ifndef VELOCITY_H | |
26 | #define VELOCITY_H | |
27 | ||
28 | #define VELOCITY_TX_CSUM_SUPPORT | |
29 | ||
30 | #define VELOCITY_NAME "via-velocity" | |
31 | #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" | |
d5b20697 | 32 | #define VELOCITY_VERSION "1.14" |
1da177e4 | 33 | |
cabb7667 JG |
34 | #define VELOCITY_IO_SIZE 256 |
35 | ||
1da177e4 LT |
36 | #define PKT_BUF_SZ 1540 |
37 | ||
38 | #define MAX_UNITS 8 | |
39 | #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} | |
40 | ||
41 | #define REV_ID_VT6110 (0) | |
42 | ||
43 | #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0) | |
44 | #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0) | |
45 | #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0) | |
46 | ||
47 | #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x)) | |
48 | #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x)) | |
49 | #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x)) | |
50 | ||
51 | #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0) | |
52 | #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0) | |
53 | #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0) | |
54 | ||
55 | #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0) | |
56 | #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0) | |
57 | #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0) | |
58 | ||
59 | #define VAR_USED(p) do {(p)=(p);} while (0) | |
60 | ||
61 | /* | |
62 | * Purpose: Structures for MAX RX/TX descriptors. | |
63 | */ | |
64 | ||
65 | ||
66 | #define B_OWNED_BY_CHIP 1 | |
67 | #define B_OWNED_BY_HOST 0 | |
68 | ||
69 | /* | |
70 | * Bits in the RSR0 register | |
71 | */ | |
72 | ||
73 | #define RSR_DETAG 0x0080 | |
74 | #define RSR_SNTAG 0x0040 | |
75 | #define RSR_RXER 0x0020 | |
76 | #define RSR_RL 0x0010 | |
77 | #define RSR_CE 0x0008 | |
78 | #define RSR_FAE 0x0004 | |
79 | #define RSR_CRC 0x0002 | |
80 | #define RSR_VIDM 0x0001 | |
81 | ||
82 | /* | |
83 | * Bits in the RSR1 register | |
84 | */ | |
85 | ||
86 | #define RSR_RXOK 0x8000 // rx OK | |
87 | #define RSR_PFT 0x4000 // Perfect filtering address match | |
88 | #define RSR_MAR 0x2000 // MAC accept multicast address packet | |
89 | #define RSR_BAR 0x1000 // MAC accept broadcast address packet | |
90 | #define RSR_PHY 0x0800 // MAC accept physical address packet | |
91 | #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator | |
92 | #define RSR_STP 0x0200 // start of packet | |
93 | #define RSR_EDP 0x0100 // end of packet | |
94 | ||
95 | /* | |
96 | * Bits in the RSR1 register | |
97 | */ | |
98 | ||
99 | #define RSR1_RXOK 0x80 // rx OK | |
100 | #define RSR1_PFT 0x40 // Perfect filtering address match | |
101 | #define RSR1_MAR 0x20 // MAC accept multicast address packet | |
102 | #define RSR1_BAR 0x10 // MAC accept broadcast address packet | |
103 | #define RSR1_PHY 0x08 // MAC accept physical address packet | |
104 | #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator | |
105 | #define RSR1_STP 0x02 // start of packet | |
106 | #define RSR1_EDP 0x01 // end of packet | |
107 | ||
108 | /* | |
109 | * Bits in the CSM register | |
110 | */ | |
111 | ||
112 | #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok | |
113 | #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok | |
114 | #define CSM_FRAG 0x10 //Fragment IP datagram | |
115 | #define CSM_IPKT 0x04 //Received an IP packet | |
116 | #define CSM_TCPKT 0x02 //Received a TCP packet | |
117 | #define CSM_UDPKT 0x01 //Received a UDP packet | |
118 | ||
119 | /* | |
120 | * Bits in the TSR0 register | |
121 | */ | |
122 | ||
123 | #define TSR0_ABT 0x0080 // Tx abort because of excessive collision | |
124 | #define TSR0_OWT 0x0040 // Jumbo frame Tx abort | |
125 | #define TSR0_OWC 0x0020 // Out of window collision | |
126 | #define TSR0_COLS 0x0010 // experience collision in this transmit event | |
127 | #define TSR0_NCR3 0x0008 // collision retry counter[3] | |
128 | #define TSR0_NCR2 0x0004 // collision retry counter[2] | |
129 | #define TSR0_NCR1 0x0002 // collision retry counter[1] | |
130 | #define TSR0_NCR0 0x0001 // collision retry counter[0] | |
131 | #define TSR0_TERR 0x8000 // | |
132 | #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode | |
133 | #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode | |
134 | #define TSR0_LNKFL 0x1000 // packet serviced during link down | |
135 | #define TSR0_SHDN 0x0400 // shutdown case | |
136 | #define TSR0_CRS 0x0200 // carrier sense lost | |
137 | #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat) | |
138 | ||
139 | /* | |
140 | * Bits in the TSR1 register | |
141 | */ | |
142 | ||
143 | #define TSR1_TERR 0x80 // | |
144 | #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode | |
145 | #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode | |
146 | #define TSR1_LNKFL 0x10 // packet serviced during link down | |
147 | #define TSR1_SHDN 0x04 // shutdown case | |
148 | #define TSR1_CRS 0x02 // carrier sense lost | |
149 | #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat) | |
150 | ||
151 | // | |
152 | // Bits in the TCR0 register | |
153 | // | |
154 | #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete | |
155 | #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme | |
156 | #define TCR0_VETAG 0x20 // enable VLAN tag | |
157 | #define TCR0_IPCK 0x10 // request IP checksum calculation. | |
158 | #define TCR0_UDPCK 0x08 // request UDP checksum calculation. | |
159 | #define TCR0_TCPCK 0x04 // request TCP checksum calculation. | |
160 | #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side | |
161 | #define TCR0_CRC 0x01 // disable CRC generation | |
162 | ||
163 | #define TCPLS_NORMAL 3 | |
164 | #define TCPLS_START 2 | |
165 | #define TCPLS_END 1 | |
166 | #define TCPLS_MED 0 | |
167 | ||
168 | ||
169 | // max transmit or receive buffer size | |
170 | #define CB_RX_BUF_SIZE 2048UL // max buffer size | |
171 | // NOTE: must be multiple of 4 | |
172 | ||
173 | #define CB_MAX_RD_NUM 512 // MAX # of RD | |
174 | #define CB_MAX_TD_NUM 256 // MAX # of TD | |
175 | ||
176 | #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119 | |
177 | #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119 | |
178 | ||
179 | #define CB_INIT_RD_NUM 128 // init # of RD, for setup default | |
180 | #define CB_INIT_TD_NUM 64 // init # of TD, for setup default | |
181 | ||
182 | // for 3119 | |
183 | #define CB_TD_RING_NUM 4 // # of TD rings. | |
184 | #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx) | |
185 | ||
186 | ||
187 | /* | |
188 | * If collisions excess 15 times , tx will abort, and | |
189 | * if tx fifo underflow, tx will fail | |
190 | * we should try to resend it | |
191 | */ | |
192 | ||
193 | #define CB_MAX_TX_ABORT_RETRY 3 | |
194 | ||
195 | /* | |
196 | * Receive descriptor | |
197 | */ | |
198 | ||
199 | struct rdesc0 { | |
200 | u16 RSR; /* Receive status */ | |
201 | u16 len:14; /* Received packet length */ | |
202 | u16 reserved:1; | |
203 | u16 owner:1; /* Who owns this buffer ? */ | |
204 | }; | |
205 | ||
206 | struct rdesc1 { | |
207 | u16 PQTAG; | |
208 | u8 CSM; | |
209 | u8 IPKT; | |
210 | }; | |
211 | ||
212 | struct rx_desc { | |
213 | struct rdesc0 rdesc0; | |
214 | struct rdesc1 rdesc1; | |
215 | u32 pa_low; /* Low 32 bit PCI address */ | |
216 | u16 pa_high; /* Next 16 bit PCI address (48 total) */ | |
217 | u16 len:15; /* Frame size */ | |
218 | u16 inten:1; /* Enable interrupt */ | |
219 | } __attribute__ ((__packed__)); | |
220 | ||
221 | /* | |
222 | * Transmit descriptor | |
223 | */ | |
224 | ||
225 | struct tdesc0 { | |
226 | u16 TSR; /* Transmit status register */ | |
227 | u16 pktsize:14; /* Size of frame */ | |
228 | u16 reserved:1; | |
229 | u16 owner:1; /* Who owns the buffer */ | |
230 | }; | |
231 | ||
232 | struct pqinf { /* Priority queue info */ | |
233 | u16 VID:12; | |
234 | u16 CFI:1; | |
235 | u16 priority:3; | |
236 | } __attribute__ ((__packed__)); | |
237 | ||
238 | struct tdesc1 { | |
239 | struct pqinf pqinf; | |
240 | u8 TCR; | |
241 | u8 TCPLS:2; | |
242 | u8 reserved:2; | |
243 | u8 CMDZ:4; | |
244 | } __attribute__ ((__packed__)); | |
245 | ||
246 | struct td_buf { | |
247 | u32 pa_low; | |
248 | u16 pa_high; | |
6aa20a22 | 249 | u16 bufsize:14; |
1da177e4 LT |
250 | u16 reserved:1; |
251 | u16 queue:1; | |
252 | } __attribute__ ((__packed__)); | |
253 | ||
254 | struct tx_desc { | |
255 | struct tdesc0 tdesc0; | |
256 | struct tdesc1 tdesc1; | |
257 | struct td_buf td_buf[7]; | |
258 | }; | |
259 | ||
260 | struct velocity_rd_info { | |
261 | struct sk_buff *skb; | |
262 | dma_addr_t skb_dma; | |
263 | }; | |
264 | ||
1da177e4 LT |
265 | /* |
266 | * Used to track transmit side buffers. | |
267 | */ | |
268 | ||
269 | struct velocity_td_info { | |
270 | struct sk_buff *skb; | |
271 | u8 *buf; | |
272 | int nskb_dma; | |
273 | dma_addr_t skb_dma[7]; | |
274 | dma_addr_t buf_dma; | |
275 | }; | |
276 | ||
277 | enum velocity_owner { | |
278 | OWNED_BY_HOST = 0, | |
279 | OWNED_BY_NIC = 1 | |
280 | }; | |
281 | ||
282 | ||
283 | /* | |
284 | * MAC registers and macros. | |
285 | */ | |
286 | ||
287 | ||
288 | #define MCAM_SIZE 64 | |
289 | #define VCAM_SIZE 64 | |
290 | #define TX_QUEUE_NO 4 | |
291 | ||
292 | #define MAX_HW_MIB_COUNTER 32 | |
83055d46 | 293 | #define VELOCITY_MIN_MTU (64) |
1da177e4 LT |
294 | #define VELOCITY_MAX_MTU (9000) |
295 | ||
296 | /* | |
297 | * Registers in the MAC | |
298 | */ | |
299 | ||
300 | #define MAC_REG_PAR 0x00 // physical address | |
301 | #define MAC_REG_RCR 0x06 | |
302 | #define MAC_REG_TCR 0x07 | |
303 | #define MAC_REG_CR0_SET 0x08 | |
304 | #define MAC_REG_CR1_SET 0x09 | |
305 | #define MAC_REG_CR2_SET 0x0A | |
306 | #define MAC_REG_CR3_SET 0x0B | |
307 | #define MAC_REG_CR0_CLR 0x0C | |
308 | #define MAC_REG_CR1_CLR 0x0D | |
309 | #define MAC_REG_CR2_CLR 0x0E | |
310 | #define MAC_REG_CR3_CLR 0x0F | |
311 | #define MAC_REG_MAR 0x10 | |
312 | #define MAC_REG_CAM 0x10 | |
313 | #define MAC_REG_DEC_BASE_HI 0x18 | |
314 | #define MAC_REG_DBF_BASE_HI 0x1C | |
315 | #define MAC_REG_ISR_CTL 0x20 | |
316 | #define MAC_REG_ISR_HOTMR 0x20 | |
317 | #define MAC_REG_ISR_TSUPTHR 0x20 | |
318 | #define MAC_REG_ISR_RSUPTHR 0x20 | |
319 | #define MAC_REG_ISR_CTL1 0x21 | |
320 | #define MAC_REG_TXE_SR 0x22 | |
321 | #define MAC_REG_RXE_SR 0x23 | |
322 | #define MAC_REG_ISR 0x24 | |
323 | #define MAC_REG_ISR0 0x24 | |
324 | #define MAC_REG_ISR1 0x25 | |
325 | #define MAC_REG_ISR2 0x26 | |
326 | #define MAC_REG_ISR3 0x27 | |
327 | #define MAC_REG_IMR 0x28 | |
328 | #define MAC_REG_IMR0 0x28 | |
329 | #define MAC_REG_IMR1 0x29 | |
330 | #define MAC_REG_IMR2 0x2A | |
331 | #define MAC_REG_IMR3 0x2B | |
332 | #define MAC_REG_TDCSR_SET 0x30 | |
333 | #define MAC_REG_RDCSR_SET 0x32 | |
334 | #define MAC_REG_TDCSR_CLR 0x34 | |
335 | #define MAC_REG_RDCSR_CLR 0x36 | |
336 | #define MAC_REG_RDBASE_LO 0x38 | |
337 | #define MAC_REG_RDINDX 0x3C | |
338 | #define MAC_REG_TDBASE_LO 0x40 | |
339 | #define MAC_REG_RDCSIZE 0x50 | |
340 | #define MAC_REG_TDCSIZE 0x52 | |
341 | #define MAC_REG_TDINDX 0x54 | |
342 | #define MAC_REG_TDIDX0 0x54 | |
343 | #define MAC_REG_TDIDX1 0x56 | |
344 | #define MAC_REG_TDIDX2 0x58 | |
345 | #define MAC_REG_TDIDX3 0x5A | |
346 | #define MAC_REG_PAUSE_TIMER 0x5C | |
347 | #define MAC_REG_RBRDU 0x5E | |
348 | #define MAC_REG_FIFO_TEST0 0x60 | |
349 | #define MAC_REG_FIFO_TEST1 0x64 | |
350 | #define MAC_REG_CAMADDR 0x68 | |
351 | #define MAC_REG_CAMCR 0x69 | |
352 | #define MAC_REG_GFTEST 0x6A | |
353 | #define MAC_REG_FTSTCMD 0x6B | |
354 | #define MAC_REG_MIICFG 0x6C | |
355 | #define MAC_REG_MIISR 0x6D | |
356 | #define MAC_REG_PHYSR0 0x6E | |
357 | #define MAC_REG_PHYSR1 0x6F | |
358 | #define MAC_REG_MIICR 0x70 | |
359 | #define MAC_REG_MIIADR 0x71 | |
360 | #define MAC_REG_MIIDATA 0x72 | |
361 | #define MAC_REG_SOFT_TIMER0 0x74 | |
362 | #define MAC_REG_SOFT_TIMER1 0x76 | |
363 | #define MAC_REG_CFGA 0x78 | |
364 | #define MAC_REG_CFGB 0x79 | |
365 | #define MAC_REG_CFGC 0x7A | |
366 | #define MAC_REG_CFGD 0x7B | |
367 | #define MAC_REG_DCFG0 0x7C | |
368 | #define MAC_REG_DCFG1 0x7D | |
369 | #define MAC_REG_MCFG0 0x7E | |
370 | #define MAC_REG_MCFG1 0x7F | |
371 | ||
372 | #define MAC_REG_TBIST 0x80 | |
373 | #define MAC_REG_RBIST 0x81 | |
374 | #define MAC_REG_PMCC 0x82 | |
375 | #define MAC_REG_STICKHW 0x83 | |
376 | #define MAC_REG_MIBCR 0x84 | |
377 | #define MAC_REG_EERSV 0x85 | |
378 | #define MAC_REG_REVID 0x86 | |
379 | #define MAC_REG_MIBREAD 0x88 | |
380 | #define MAC_REG_BPMA 0x8C | |
381 | #define MAC_REG_EEWR_DATA 0x8C | |
382 | #define MAC_REG_BPMD_WR 0x8F | |
383 | #define MAC_REG_BPCMD 0x90 | |
384 | #define MAC_REG_BPMD_RD 0x91 | |
385 | #define MAC_REG_EECHKSUM 0x92 | |
386 | #define MAC_REG_EECSR 0x93 | |
387 | #define MAC_REG_EERD_DATA 0x94 | |
388 | #define MAC_REG_EADDR 0x96 | |
389 | #define MAC_REG_EMBCMD 0x97 | |
390 | #define MAC_REG_JMPSR0 0x98 | |
391 | #define MAC_REG_JMPSR1 0x99 | |
392 | #define MAC_REG_JMPSR2 0x9A | |
393 | #define MAC_REG_JMPSR3 0x9B | |
394 | #define MAC_REG_CHIPGSR 0x9C | |
395 | #define MAC_REG_TESTCFG 0x9D | |
396 | #define MAC_REG_DEBUG 0x9E | |
397 | #define MAC_REG_CHIPGCR 0x9F | |
398 | #define MAC_REG_WOLCR0_SET 0xA0 | |
399 | #define MAC_REG_WOLCR1_SET 0xA1 | |
400 | #define MAC_REG_PWCFG_SET 0xA2 | |
401 | #define MAC_REG_WOLCFG_SET 0xA3 | |
402 | #define MAC_REG_WOLCR0_CLR 0xA4 | |
403 | #define MAC_REG_WOLCR1_CLR 0xA5 | |
404 | #define MAC_REG_PWCFG_CLR 0xA6 | |
405 | #define MAC_REG_WOLCFG_CLR 0xA7 | |
406 | #define MAC_REG_WOLSR0_SET 0xA8 | |
407 | #define MAC_REG_WOLSR1_SET 0xA9 | |
408 | #define MAC_REG_WOLSR0_CLR 0xAC | |
409 | #define MAC_REG_WOLSR1_CLR 0xAD | |
410 | #define MAC_REG_PATRN_CRC0 0xB0 | |
411 | #define MAC_REG_PATRN_CRC1 0xB2 | |
412 | #define MAC_REG_PATRN_CRC2 0xB4 | |
413 | #define MAC_REG_PATRN_CRC3 0xB6 | |
414 | #define MAC_REG_PATRN_CRC4 0xB8 | |
415 | #define MAC_REG_PATRN_CRC5 0xBA | |
416 | #define MAC_REG_PATRN_CRC6 0xBC | |
417 | #define MAC_REG_PATRN_CRC7 0xBE | |
418 | #define MAC_REG_BYTEMSK0_0 0xC0 | |
419 | #define MAC_REG_BYTEMSK0_1 0xC4 | |
420 | #define MAC_REG_BYTEMSK0_2 0xC8 | |
421 | #define MAC_REG_BYTEMSK0_3 0xCC | |
422 | #define MAC_REG_BYTEMSK1_0 0xD0 | |
423 | #define MAC_REG_BYTEMSK1_1 0xD4 | |
424 | #define MAC_REG_BYTEMSK1_2 0xD8 | |
425 | #define MAC_REG_BYTEMSK1_3 0xDC | |
426 | #define MAC_REG_BYTEMSK2_0 0xE0 | |
427 | #define MAC_REG_BYTEMSK2_1 0xE4 | |
428 | #define MAC_REG_BYTEMSK2_2 0xE8 | |
429 | #define MAC_REG_BYTEMSK2_3 0xEC | |
430 | #define MAC_REG_BYTEMSK3_0 0xF0 | |
431 | #define MAC_REG_BYTEMSK3_1 0xF4 | |
432 | #define MAC_REG_BYTEMSK3_2 0xF8 | |
433 | #define MAC_REG_BYTEMSK3_3 0xFC | |
434 | ||
435 | /* | |
436 | * Bits in the RCR register | |
437 | */ | |
438 | ||
439 | #define RCR_AS 0x80 | |
440 | #define RCR_AP 0x40 | |
441 | #define RCR_AL 0x20 | |
442 | #define RCR_PROM 0x10 | |
443 | #define RCR_AB 0x08 | |
444 | #define RCR_AM 0x04 | |
445 | #define RCR_AR 0x02 | |
446 | #define RCR_SEP 0x01 | |
447 | ||
448 | /* | |
449 | * Bits in the TCR register | |
450 | */ | |
451 | ||
452 | #define TCR_TB2BDIS 0x80 | |
453 | #define TCR_COLTMC1 0x08 | |
454 | #define TCR_COLTMC0 0x04 | |
455 | #define TCR_LB1 0x02 /* loopback[1] */ | |
456 | #define TCR_LB0 0x01 /* loopback[0] */ | |
457 | ||
458 | /* | |
459 | * Bits in the CR0 register | |
460 | */ | |
461 | ||
462 | #define CR0_TXON 0x00000008UL | |
463 | #define CR0_RXON 0x00000004UL | |
464 | #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */ | |
465 | #define CR0_STRT 0x00000001UL /* start MAC */ | |
466 | #define CR0_SFRST 0x00008000UL /* software reset */ | |
467 | #define CR0_TM1EN 0x00004000UL | |
468 | #define CR0_TM0EN 0x00002000UL | |
469 | #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */ | |
470 | #define CR0_DISAU 0x00000100UL | |
471 | #define CR0_XONEN 0x00800000UL | |
472 | #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */ | |
473 | #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */ | |
474 | #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */ | |
475 | #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */ | |
476 | #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */ | |
477 | #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */ | |
478 | #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */ | |
479 | #define CR0_GSPRST 0x80000000UL | |
480 | #define CR0_FORSRST 0x40000000UL | |
481 | #define CR0_FPHYRST 0x20000000UL | |
482 | #define CR0_DIAG 0x10000000UL | |
483 | #define CR0_INTPCTL 0x04000000UL | |
484 | #define CR0_GINTMSK1 0x02000000UL | |
485 | #define CR0_GINTMSK0 0x01000000UL | |
486 | ||
487 | /* | |
488 | * Bits in the CR1 register | |
489 | */ | |
490 | ||
491 | #define CR1_SFRST 0x80 /* software reset */ | |
492 | #define CR1_TM1EN 0x40 | |
493 | #define CR1_TM0EN 0x20 | |
494 | #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ | |
495 | #define CR1_DISAU 0x01 | |
496 | ||
497 | /* | |
498 | * Bits in the CR2 register | |
499 | */ | |
500 | ||
501 | #define CR2_XONEN 0x80 | |
502 | #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */ | |
503 | #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */ | |
504 | #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */ | |
505 | #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */ | |
506 | #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */ | |
507 | #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */ | |
508 | #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */ | |
509 | ||
510 | /* | |
511 | * Bits in the CR3 register | |
512 | */ | |
513 | ||
514 | #define CR3_GSPRST 0x80 | |
515 | #define CR3_FORSRST 0x40 | |
516 | #define CR3_FPHYRST 0x20 | |
517 | #define CR3_DIAG 0x10 | |
518 | #define CR3_INTPCTL 0x04 | |
519 | #define CR3_GINTMSK1 0x02 | |
520 | #define CR3_GINTMSK0 0x01 | |
521 | ||
522 | #define ISRCTL_UDPINT 0x8000 | |
523 | #define ISRCTL_TSUPDIS 0x4000 | |
524 | #define ISRCTL_RSUPDIS 0x2000 | |
525 | #define ISRCTL_PMSK1 0x1000 | |
526 | #define ISRCTL_PMSK0 0x0800 | |
527 | #define ISRCTL_INTPD 0x0400 | |
528 | #define ISRCTL_HCRLD 0x0200 | |
529 | #define ISRCTL_SCRLD 0x0100 | |
530 | ||
531 | /* | |
532 | * Bits in the ISR_CTL1 register | |
533 | */ | |
534 | ||
535 | #define ISRCTL1_UDPINT 0x80 | |
536 | #define ISRCTL1_TSUPDIS 0x40 | |
537 | #define ISRCTL1_RSUPDIS 0x20 | |
538 | #define ISRCTL1_PMSK1 0x10 | |
539 | #define ISRCTL1_PMSK0 0x08 | |
540 | #define ISRCTL1_INTPD 0x04 | |
541 | #define ISRCTL1_HCRLD 0x02 | |
542 | #define ISRCTL1_SCRLD 0x01 | |
543 | ||
544 | /* | |
545 | * Bits in the TXE_SR register | |
546 | */ | |
547 | ||
548 | #define TXESR_TFDBS 0x08 | |
549 | #define TXESR_TDWBS 0x04 | |
550 | #define TXESR_TDRBS 0x02 | |
551 | #define TXESR_TDSTR 0x01 | |
552 | ||
553 | /* | |
554 | * Bits in the RXE_SR register | |
555 | */ | |
556 | ||
557 | #define RXESR_RFDBS 0x08 | |
558 | #define RXESR_RDWBS 0x04 | |
559 | #define RXESR_RDRBS 0x02 | |
560 | #define RXESR_RDSTR 0x01 | |
561 | ||
562 | /* | |
563 | * Bits in the ISR register | |
564 | */ | |
565 | ||
566 | #define ISR_ISR3 0x80000000UL | |
567 | #define ISR_ISR2 0x40000000UL | |
568 | #define ISR_ISR1 0x20000000UL | |
569 | #define ISR_ISR0 0x10000000UL | |
570 | #define ISR_TXSTLI 0x02000000UL | |
571 | #define ISR_RXSTLI 0x01000000UL | |
572 | #define ISR_HFLD 0x00800000UL | |
573 | #define ISR_UDPI 0x00400000UL | |
574 | #define ISR_MIBFI 0x00200000UL | |
575 | #define ISR_SHDNI 0x00100000UL | |
576 | #define ISR_PHYI 0x00080000UL | |
577 | #define ISR_PWEI 0x00040000UL | |
578 | #define ISR_TMR1I 0x00020000UL | |
579 | #define ISR_TMR0I 0x00010000UL | |
580 | #define ISR_SRCI 0x00008000UL | |
581 | #define ISR_LSTPEI 0x00004000UL | |
582 | #define ISR_LSTEI 0x00002000UL | |
583 | #define ISR_OVFI 0x00001000UL | |
584 | #define ISR_FLONI 0x00000800UL | |
585 | #define ISR_RACEI 0x00000400UL | |
586 | #define ISR_TXWB1I 0x00000200UL | |
587 | #define ISR_TXWB0I 0x00000100UL | |
588 | #define ISR_PTX3I 0x00000080UL | |
589 | #define ISR_PTX2I 0x00000040UL | |
590 | #define ISR_PTX1I 0x00000020UL | |
591 | #define ISR_PTX0I 0x00000010UL | |
592 | #define ISR_PTXI 0x00000008UL | |
593 | #define ISR_PRXI 0x00000004UL | |
594 | #define ISR_PPTXI 0x00000002UL | |
595 | #define ISR_PPRXI 0x00000001UL | |
596 | ||
597 | /* | |
598 | * Bits in the IMR register | |
599 | */ | |
600 | ||
601 | #define IMR_TXSTLM 0x02000000UL | |
602 | #define IMR_UDPIM 0x00400000UL | |
603 | #define IMR_MIBFIM 0x00200000UL | |
604 | #define IMR_SHDNIM 0x00100000UL | |
605 | #define IMR_PHYIM 0x00080000UL | |
606 | #define IMR_PWEIM 0x00040000UL | |
607 | #define IMR_TMR1IM 0x00020000UL | |
608 | #define IMR_TMR0IM 0x00010000UL | |
609 | ||
610 | #define IMR_SRCIM 0x00008000UL | |
611 | #define IMR_LSTPEIM 0x00004000UL | |
612 | #define IMR_LSTEIM 0x00002000UL | |
613 | #define IMR_OVFIM 0x00001000UL | |
614 | #define IMR_FLONIM 0x00000800UL | |
615 | #define IMR_RACEIM 0x00000400UL | |
616 | #define IMR_TXWB1IM 0x00000200UL | |
617 | #define IMR_TXWB0IM 0x00000100UL | |
618 | ||
619 | #define IMR_PTX3IM 0x00000080UL | |
620 | #define IMR_PTX2IM 0x00000040UL | |
621 | #define IMR_PTX1IM 0x00000020UL | |
622 | #define IMR_PTX0IM 0x00000010UL | |
623 | #define IMR_PTXIM 0x00000008UL | |
624 | #define IMR_PRXIM 0x00000004UL | |
625 | #define IMR_PPTXIM 0x00000002UL | |
626 | #define IMR_PPRXIM 0x00000001UL | |
627 | ||
628 | /* 0x0013FB0FUL = initial value of IMR */ | |
629 | ||
630 | #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ | |
631 | IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ | |
632 | IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ | |
633 | IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM) | |
634 | ||
635 | /* | |
636 | * Bits in the TDCSR0/1, RDCSR0 register | |
637 | */ | |
638 | ||
639 | #define TRDCSR_DEAD 0x0008 | |
640 | #define TRDCSR_WAK 0x0004 | |
641 | #define TRDCSR_ACT 0x0002 | |
642 | #define TRDCSR_RUN 0x0001 | |
643 | ||
644 | /* | |
645 | * Bits in the CAMADDR register | |
646 | */ | |
647 | ||
648 | #define CAMADDR_CAMEN 0x80 | |
649 | #define CAMADDR_VCAMSL 0x40 | |
650 | ||
651 | /* | |
652 | * Bits in the CAMCR register | |
653 | */ | |
654 | ||
655 | #define CAMCR_PS1 0x80 | |
656 | #define CAMCR_PS0 0x40 | |
657 | #define CAMCR_AITRPKT 0x20 | |
658 | #define CAMCR_AITR16 0x10 | |
659 | #define CAMCR_CAMRD 0x08 | |
660 | #define CAMCR_CAMWR 0x04 | |
661 | #define CAMCR_PS_CAM_MASK 0x40 | |
662 | #define CAMCR_PS_CAM_DATA 0x80 | |
663 | #define CAMCR_PS_MAR 0x00 | |
664 | ||
665 | /* | |
666 | * Bits in the MIICFG register | |
667 | */ | |
668 | ||
669 | #define MIICFG_MPO1 0x80 | |
670 | #define MIICFG_MPO0 0x40 | |
671 | #define MIICFG_MFDC 0x20 | |
672 | ||
673 | /* | |
674 | * Bits in the MIISR register | |
675 | */ | |
676 | ||
677 | #define MIISR_MIDLE 0x80 | |
678 | ||
679 | /* | |
680 | * Bits in the PHYSR0 register | |
681 | */ | |
682 | ||
683 | #define PHYSR0_PHYRST 0x80 | |
684 | #define PHYSR0_LINKGD 0x40 | |
685 | #define PHYSR0_FDPX 0x10 | |
686 | #define PHYSR0_SPDG 0x08 | |
687 | #define PHYSR0_SPD10 0x04 | |
688 | #define PHYSR0_RXFLC 0x02 | |
689 | #define PHYSR0_TXFLC 0x01 | |
690 | ||
691 | /* | |
692 | * Bits in the PHYSR1 register | |
693 | */ | |
694 | ||
695 | #define PHYSR1_PHYTBI 0x01 | |
696 | ||
697 | /* | |
698 | * Bits in the MIICR register | |
699 | */ | |
700 | ||
701 | #define MIICR_MAUTO 0x80 | |
702 | #define MIICR_RCMD 0x40 | |
703 | #define MIICR_WCMD 0x20 | |
704 | #define MIICR_MDPM 0x10 | |
705 | #define MIICR_MOUT 0x08 | |
706 | #define MIICR_MDO 0x04 | |
707 | #define MIICR_MDI 0x02 | |
708 | #define MIICR_MDC 0x01 | |
709 | ||
710 | /* | |
711 | * Bits in the MIIADR register | |
712 | */ | |
713 | ||
714 | #define MIIADR_SWMPL 0x80 | |
715 | ||
716 | /* | |
717 | * Bits in the CFGA register | |
718 | */ | |
719 | ||
720 | #define CFGA_PMHCTG 0x08 | |
721 | #define CFGA_GPIO1PD 0x04 | |
722 | #define CFGA_ABSHDN 0x02 | |
723 | #define CFGA_PACPI 0x01 | |
724 | ||
725 | /* | |
726 | * Bits in the CFGB register | |
727 | */ | |
728 | ||
729 | #define CFGB_GTCKOPT 0x80 | |
730 | #define CFGB_MIIOPT 0x40 | |
731 | #define CFGB_CRSEOPT 0x20 | |
732 | #define CFGB_OFSET 0x10 | |
733 | #define CFGB_CRANDOM 0x08 | |
734 | #define CFGB_CAP 0x04 | |
735 | #define CFGB_MBA 0x02 | |
736 | #define CFGB_BAKOPT 0x01 | |
737 | ||
738 | /* | |
739 | * Bits in the CFGC register | |
740 | */ | |
741 | ||
742 | #define CFGC_EELOAD 0x80 | |
743 | #define CFGC_BROPT 0x40 | |
744 | #define CFGC_DLYEN 0x20 | |
745 | #define CFGC_DTSEL 0x10 | |
746 | #define CFGC_BTSEL 0x08 | |
747 | #define CFGC_BPS2 0x04 /* bootrom select[2] */ | |
748 | #define CFGC_BPS1 0x02 /* bootrom select[1] */ | |
749 | #define CFGC_BPS0 0x01 /* bootrom select[0] */ | |
750 | ||
751 | /* | |
752 | * Bits in the CFGD register | |
753 | */ | |
754 | ||
755 | #define CFGD_IODIS 0x80 | |
756 | #define CFGD_MSLVDACEN 0x40 | |
757 | #define CFGD_CFGDACEN 0x20 | |
758 | #define CFGD_PCI64EN 0x10 | |
759 | #define CFGD_HTMRL4 0x08 | |
760 | ||
761 | /* | |
762 | * Bits in the DCFG1 register | |
763 | */ | |
764 | ||
765 | #define DCFG_XMWI 0x8000 | |
766 | #define DCFG_XMRM 0x4000 | |
767 | #define DCFG_XMRL 0x2000 | |
768 | #define DCFG_PERDIS 0x1000 | |
769 | #define DCFG_MRWAIT 0x0400 | |
770 | #define DCFG_MWWAIT 0x0200 | |
771 | #define DCFG_LATMEN 0x0100 | |
772 | ||
773 | /* | |
774 | * Bits in the MCFG0 register | |
775 | */ | |
776 | ||
777 | #define MCFG_RXARB 0x0080 | |
778 | #define MCFG_RFT1 0x0020 | |
779 | #define MCFG_RFT0 0x0010 | |
780 | #define MCFG_LOWTHOPT 0x0008 | |
781 | #define MCFG_PQEN 0x0004 | |
782 | #define MCFG_RTGOPT 0x0002 | |
783 | #define MCFG_VIDFR 0x0001 | |
784 | ||
785 | /* | |
786 | * Bits in the MCFG1 register | |
787 | */ | |
788 | ||
789 | #define MCFG_TXARB 0x8000 | |
790 | #define MCFG_TXQBK1 0x0800 | |
791 | #define MCFG_TXQBK0 0x0400 | |
792 | #define MCFG_TXQNOBK 0x0200 | |
793 | #define MCFG_SNAPOPT 0x0100 | |
794 | ||
795 | /* | |
796 | * Bits in the PMCC register | |
797 | */ | |
798 | ||
799 | #define PMCC_DSI 0x80 | |
800 | #define PMCC_D2_DIS 0x40 | |
801 | #define PMCC_D1_DIS 0x20 | |
802 | #define PMCC_D3C_EN 0x10 | |
803 | #define PMCC_D3H_EN 0x08 | |
804 | #define PMCC_D2_EN 0x04 | |
805 | #define PMCC_D1_EN 0x02 | |
806 | #define PMCC_D0_EN 0x01 | |
807 | ||
808 | /* | |
809 | * Bits in STICKHW | |
810 | */ | |
811 | ||
812 | #define STICKHW_SWPTAG 0x10 | |
813 | #define STICKHW_WOLSR 0x08 | |
814 | #define STICKHW_WOLEN 0x04 | |
815 | #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */ | |
816 | #define STICKHW_DS0 0x01 /* suspend well DS write port */ | |
817 | ||
818 | /* | |
819 | * Bits in the MIBCR register | |
820 | */ | |
821 | ||
822 | #define MIBCR_MIBISTOK 0x80 | |
823 | #define MIBCR_MIBISTGO 0x40 | |
824 | #define MIBCR_MIBINC 0x20 | |
825 | #define MIBCR_MIBHI 0x10 | |
826 | #define MIBCR_MIBFRZ 0x08 | |
827 | #define MIBCR_MIBFLSH 0x04 | |
828 | #define MIBCR_MPTRINI 0x02 | |
829 | #define MIBCR_MIBCLR 0x01 | |
830 | ||
831 | /* | |
832 | * Bits in the EERSV register | |
833 | */ | |
834 | ||
835 | #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */ | |
836 | ||
837 | #define EERSV_BOOT_MASK ((u8) 0x06) | |
838 | #define EERSV_BOOT_INT19 ((u8) 0x00) | |
839 | #define EERSV_BOOT_INT18 ((u8) 0x02) | |
840 | #define EERSV_BOOT_LOCAL ((u8) 0x04) | |
841 | #define EERSV_BOOT_BEV ((u8) 0x06) | |
842 | ||
843 | ||
844 | /* | |
845 | * Bits in BPCMD | |
846 | */ | |
847 | ||
848 | #define BPCMD_BPDNE 0x80 | |
849 | #define BPCMD_EBPWR 0x02 | |
850 | #define BPCMD_EBPRD 0x01 | |
851 | ||
852 | /* | |
853 | * Bits in the EECSR register | |
854 | */ | |
855 | ||
856 | #define EECSR_EMBP 0x40 /* eeprom embeded programming */ | |
857 | #define EECSR_RELOAD 0x20 /* eeprom content reload */ | |
858 | #define EECSR_DPM 0x10 /* eeprom direct programming */ | |
859 | #define EECSR_ECS 0x08 /* eeprom CS pin */ | |
860 | #define EECSR_ECK 0x04 /* eeprom CK pin */ | |
861 | #define EECSR_EDI 0x02 /* eeprom DI pin */ | |
862 | #define EECSR_EDO 0x01 /* eeprom DO pin */ | |
863 | ||
864 | /* | |
865 | * Bits in the EMBCMD register | |
866 | */ | |
867 | ||
868 | #define EMBCMD_EDONE 0x80 | |
869 | #define EMBCMD_EWDIS 0x08 | |
870 | #define EMBCMD_EWEN 0x04 | |
871 | #define EMBCMD_EWR 0x02 | |
872 | #define EMBCMD_ERD 0x01 | |
873 | ||
874 | /* | |
875 | * Bits in TESTCFG register | |
876 | */ | |
877 | ||
878 | #define TESTCFG_HBDIS 0x80 | |
879 | ||
880 | /* | |
881 | * Bits in CHIPGCR register | |
882 | */ | |
883 | ||
884 | #define CHIPGCR_FCGMII 0x80 | |
885 | #define CHIPGCR_FCFDX 0x40 | |
886 | #define CHIPGCR_FCRESV 0x20 | |
887 | #define CHIPGCR_FCMODE 0x10 | |
888 | #define CHIPGCR_LPSOPT 0x08 | |
889 | #define CHIPGCR_TM1US 0x04 | |
890 | #define CHIPGCR_TM0US 0x02 | |
891 | #define CHIPGCR_PHYINTEN 0x01 | |
892 | ||
893 | /* | |
894 | * Bits in WOLCR0 | |
895 | */ | |
896 | ||
897 | #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */ | |
898 | #define WOLCR_MSWOLEN6 0x0040 | |
899 | #define WOLCR_MSWOLEN5 0x0020 | |
900 | #define WOLCR_MSWOLEN4 0x0010 | |
901 | #define WOLCR_MSWOLEN3 0x0008 | |
902 | #define WOLCR_MSWOLEN2 0x0004 | |
903 | #define WOLCR_MSWOLEN1 0x0002 | |
904 | #define WOLCR_MSWOLEN0 0x0001 | |
905 | #define WOLCR_ARP_EN 0x0001 | |
906 | ||
907 | /* | |
908 | * Bits in WOLCR1 | |
909 | */ | |
910 | ||
911 | #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */ | |
912 | #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */ | |
913 | #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */ | |
914 | #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */ | |
915 | ||
916 | ||
917 | /* | |
918 | * Bits in PWCFG | |
919 | */ | |
920 | ||
921 | #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */ | |
922 | #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */ | |
923 | #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */ | |
924 | #define PWCFG_LEGCY_WOL 0x10 | |
925 | #define PWCFG_PMCSR_PME_SR 0x08 | |
926 | #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */ | |
927 | #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */ | |
928 | #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */ | |
929 | ||
930 | /* | |
931 | * Bits in WOLCFG | |
932 | */ | |
933 | ||
934 | #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */ | |
935 | #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */ | |
936 | #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */ | |
937 | #define WOLCFG_SMIIACC 0x08 /* ?? */ | |
938 | #define WOLCFG_SGENWH 0x02 | |
939 | #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII | |
940 | to report status change */ | |
941 | /* | |
942 | * Bits in WOLSR1 | |
943 | */ | |
944 | ||
945 | #define WOLSR_LINKOFF_INT 0x0800 | |
946 | #define WOLSR_LINKON_INT 0x0400 | |
947 | #define WOLSR_MAGIC_INT 0x0200 | |
948 | #define WOLSR_UNICAST_INT 0x0100 | |
949 | ||
950 | /* | |
951 | * Ethernet address filter type | |
952 | */ | |
953 | ||
954 | #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */ | |
955 | #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */ | |
956 | #define PKT_TYPE_MULTICAST 0x0002 | |
957 | #define PKT_TYPE_ALL_MULTICAST 0x0004 | |
958 | #define PKT_TYPE_BROADCAST 0x0008 | |
959 | #define PKT_TYPE_PROMISCUOUS 0x0020 | |
960 | #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */ | |
961 | #define PKT_TYPE_RUNT 0x4000 | |
962 | #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */ | |
963 | ||
964 | /* | |
965 | * Loopback mode | |
966 | */ | |
967 | ||
968 | #define MAC_LB_NONE 0x00 | |
969 | #define MAC_LB_INTERNAL 0x01 | |
970 | #define MAC_LB_EXTERNAL 0x02 | |
971 | ||
972 | /* | |
973 | * Enabled mask value of irq | |
974 | */ | |
975 | ||
976 | #if defined(_SIM) | |
977 | #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR | |
978 | set IMR0 to 0x0F according to spec */ | |
979 | ||
980 | #else | |
981 | #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR | |
982 | ignore MIBFI,RACEI to | |
983 | reduce intr. frequency | |
984 | NOTE.... do not enable NoBuf int mask at driver driver | |
985 | when (1) NoBuf -> RxThreshold = SF | |
986 | (2) OK -> RxThreshold = original value | |
987 | */ | |
988 | #endif | |
989 | ||
990 | /* | |
991 | * Revision id | |
992 | */ | |
993 | ||
994 | #define REV_ID_VT3119_A0 0x00 | |
995 | #define REV_ID_VT3119_A1 0x01 | |
996 | #define REV_ID_VT3216_A0 0x10 | |
997 | ||
998 | /* | |
999 | * Max time out delay time | |
1000 | */ | |
1001 | ||
1002 | #define W_MAX_TIMEOUT 0x0FFFU | |
1003 | ||
1004 | ||
1005 | /* | |
1006 | * MAC registers as a structure. Cannot be directly accessed this | |
1007 | * way but generates offsets for readl/writel() calls | |
1008 | */ | |
1009 | ||
1010 | struct mac_regs { | |
1011 | volatile u8 PAR[6]; /* 0x00 */ | |
1012 | volatile u8 RCR; | |
1013 | volatile u8 TCR; | |
1014 | ||
1015 | volatile u32 CR0Set; /* 0x08 */ | |
1016 | volatile u32 CR0Clr; /* 0x0C */ | |
1017 | ||
1018 | volatile u8 MARCAM[8]; /* 0x10 */ | |
1019 | ||
1020 | volatile u32 DecBaseHi; /* 0x18 */ | |
1021 | volatile u16 DbfBaseHi; /* 0x1C */ | |
1022 | volatile u16 reserved_1E; | |
1023 | ||
1024 | volatile u16 ISRCTL; /* 0x20 */ | |
1025 | volatile u8 TXESR; | |
1026 | volatile u8 RXESR; | |
1027 | ||
1028 | volatile u32 ISR; /* 0x24 */ | |
1029 | volatile u32 IMR; | |
1030 | ||
1031 | volatile u32 TDStatusPort; /* 0x2C */ | |
1032 | ||
1033 | volatile u16 TDCSRSet; /* 0x30 */ | |
1034 | volatile u8 RDCSRSet; | |
1035 | volatile u8 reserved_33; | |
1036 | volatile u16 TDCSRClr; | |
1037 | volatile u8 RDCSRClr; | |
1038 | volatile u8 reserved_37; | |
1039 | ||
1040 | volatile u32 RDBaseLo; /* 0x38 */ | |
1041 | volatile u16 RDIdx; /* 0x3C */ | |
1042 | volatile u16 reserved_3E; | |
1043 | ||
1044 | volatile u32 TDBaseLo[4]; /* 0x40 */ | |
1045 | ||
1046 | volatile u16 RDCSize; /* 0x50 */ | |
1047 | volatile u16 TDCSize; /* 0x52 */ | |
1048 | volatile u16 TDIdx[4]; /* 0x54 */ | |
1049 | volatile u16 tx_pause_timer; /* 0x5C */ | |
1050 | volatile u16 RBRDU; /* 0x5E */ | |
1051 | ||
1052 | volatile u32 FIFOTest0; /* 0x60 */ | |
1053 | volatile u32 FIFOTest1; /* 0x64 */ | |
1054 | ||
1055 | volatile u8 CAMADDR; /* 0x68 */ | |
1056 | volatile u8 CAMCR; /* 0x69 */ | |
1057 | volatile u8 GFTEST; /* 0x6A */ | |
1058 | volatile u8 FTSTCMD; /* 0x6B */ | |
1059 | ||
1060 | volatile u8 MIICFG; /* 0x6C */ | |
1061 | volatile u8 MIISR; | |
1062 | volatile u8 PHYSR0; | |
1063 | volatile u8 PHYSR1; | |
1064 | volatile u8 MIICR; | |
1065 | volatile u8 MIIADR; | |
1066 | volatile u16 MIIDATA; | |
1067 | ||
1068 | volatile u16 SoftTimer0; /* 0x74 */ | |
1069 | volatile u16 SoftTimer1; | |
1070 | ||
1071 | volatile u8 CFGA; /* 0x78 */ | |
1072 | volatile u8 CFGB; | |
1073 | volatile u8 CFGC; | |
1074 | volatile u8 CFGD; | |
1075 | ||
1076 | volatile u16 DCFG; /* 0x7C */ | |
1077 | volatile u16 MCFG; | |
1078 | ||
1079 | volatile u8 TBIST; /* 0x80 */ | |
1080 | volatile u8 RBIST; | |
1081 | volatile u8 PMCPORT; | |
1082 | volatile u8 STICKHW; | |
1083 | ||
1084 | volatile u8 MIBCR; /* 0x84 */ | |
1085 | volatile u8 reserved_85; | |
1086 | volatile u8 rev_id; | |
1087 | volatile u8 PORSTS; | |
1088 | ||
1089 | volatile u32 MIBData; /* 0x88 */ | |
1090 | ||
1091 | volatile u16 EEWrData; | |
1092 | ||
1093 | volatile u8 reserved_8E; | |
1094 | volatile u8 BPMDWr; | |
1095 | volatile u8 BPCMD; | |
1096 | volatile u8 BPMDRd; | |
1097 | ||
1098 | volatile u8 EECHKSUM; /* 0x92 */ | |
1099 | volatile u8 EECSR; | |
1100 | ||
1101 | volatile u16 EERdData; /* 0x94 */ | |
1102 | volatile u8 EADDR; | |
1103 | volatile u8 EMBCMD; | |
1104 | ||
1105 | ||
1106 | volatile u8 JMPSR0; /* 0x98 */ | |
1107 | volatile u8 JMPSR1; | |
1108 | volatile u8 JMPSR2; | |
1109 | volatile u8 JMPSR3; | |
1110 | volatile u8 CHIPGSR; /* 0x9C */ | |
1111 | volatile u8 TESTCFG; | |
1112 | volatile u8 DEBUG; | |
1113 | volatile u8 CHIPGCR; | |
1114 | ||
1115 | volatile u16 WOLCRSet; /* 0xA0 */ | |
1116 | volatile u8 PWCFGSet; | |
1117 | volatile u8 WOLCFGSet; | |
1118 | ||
1119 | volatile u16 WOLCRClr; /* 0xA4 */ | |
1120 | volatile u8 PWCFGCLR; | |
1121 | volatile u8 WOLCFGClr; | |
1122 | ||
1123 | volatile u16 WOLSRSet; /* 0xA8 */ | |
1124 | volatile u16 reserved_AA; | |
1125 | ||
1126 | volatile u16 WOLSRClr; /* 0xAC */ | |
1127 | volatile u16 reserved_AE; | |
1128 | ||
1129 | volatile u16 PatternCRC[8]; /* 0xB0 */ | |
1130 | volatile u32 ByteMask[4][4]; /* 0xC0 */ | |
1131 | } __attribute__ ((__packed__)); | |
1132 | ||
1133 | ||
1134 | enum hw_mib { | |
1135 | HW_MIB_ifRxAllPkts = 0, | |
1136 | HW_MIB_ifRxOkPkts, | |
1137 | HW_MIB_ifTxOkPkts, | |
1138 | HW_MIB_ifRxErrorPkts, | |
1139 | HW_MIB_ifRxRuntOkPkt, | |
1140 | HW_MIB_ifRxRuntErrPkt, | |
1141 | HW_MIB_ifRx64Pkts, | |
1142 | HW_MIB_ifTx64Pkts, | |
1143 | HW_MIB_ifRx65To127Pkts, | |
1144 | HW_MIB_ifTx65To127Pkts, | |
1145 | HW_MIB_ifRx128To255Pkts, | |
1146 | HW_MIB_ifTx128To255Pkts, | |
1147 | HW_MIB_ifRx256To511Pkts, | |
1148 | HW_MIB_ifTx256To511Pkts, | |
1149 | HW_MIB_ifRx512To1023Pkts, | |
1150 | HW_MIB_ifTx512To1023Pkts, | |
1151 | HW_MIB_ifRx1024To1518Pkts, | |
1152 | HW_MIB_ifTx1024To1518Pkts, | |
1153 | HW_MIB_ifTxEtherCollisions, | |
1154 | HW_MIB_ifRxPktCRCE, | |
1155 | HW_MIB_ifRxJumboPkts, | |
1156 | HW_MIB_ifTxJumboPkts, | |
1157 | HW_MIB_ifRxMacControlFrames, | |
1158 | HW_MIB_ifTxMacControlFrames, | |
1159 | HW_MIB_ifRxPktFAE, | |
1160 | HW_MIB_ifRxLongOkPkt, | |
1161 | HW_MIB_ifRxLongPktErrPkt, | |
1162 | HW_MIB_ifTXSQEErrors, | |
1163 | HW_MIB_ifRxNobuf, | |
1164 | HW_MIB_ifRxSymbolErrors, | |
1165 | HW_MIB_ifInRangeLengthErrors, | |
1166 | HW_MIB_ifLateCollisions, | |
1167 | HW_MIB_SIZE | |
1168 | }; | |
1169 | ||
1170 | enum chip_type { | |
1171 | CHIP_TYPE_VT6110 = 1, | |
1172 | }; | |
1173 | ||
1174 | struct velocity_info_tbl { | |
1175 | enum chip_type chip_id; | |
01faccbf | 1176 | const char *name; |
1da177e4 LT |
1177 | int txqueue; |
1178 | u32 flags; | |
1179 | }; | |
1180 | ||
1181 | #define mac_hw_mibs_init(regs) {\ | |
1182 | BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
1183 | BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\ | |
1184 | do {}\ | |
1185 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\ | |
1186 | BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
1187 | } | |
1188 | ||
1189 | #define mac_read_isr(regs) readl(&((regs)->ISR)) | |
1190 | #define mac_write_isr(regs, x) writel((x),&((regs)->ISR)) | |
1191 | #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR)) | |
1192 | ||
1193 | #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); | |
1194 | #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr)) | |
1195 | #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set)) | |
1196 | ||
1da177e4 LT |
1197 | #define mac_set_dma_length(regs, n) {\ |
1198 | BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\ | |
1199 | } | |
1200 | ||
1201 | #define mac_set_rx_thresh(regs, n) {\ | |
1202 | BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\ | |
1203 | } | |
1204 | ||
1205 | #define mac_rx_queue_run(regs) {\ | |
1206 | writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\ | |
1207 | } | |
1208 | ||
1209 | #define mac_rx_queue_wake(regs) {\ | |
1210 | writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\ | |
1211 | } | |
1212 | ||
1213 | #define mac_tx_queue_run(regs, n) {\ | |
1214 | writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\ | |
1215 | } | |
1216 | ||
1217 | #define mac_tx_queue_wake(regs, n) {\ | |
1218 | writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\ | |
1219 | } | |
1220 | ||
01faccbf SH |
1221 | static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) { |
1222 | int i=0; | |
1da177e4 | 1223 | |
01faccbf SH |
1224 | BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); |
1225 | do { | |
1226 | udelay(10); | |
1227 | if (i++>0x1000) | |
1228 | break; | |
1229 | } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); | |
1da177e4 LT |
1230 | } |
1231 | ||
1da177e4 LT |
1232 | /* |
1233 | * Header for WOL definitions. Used to compute hashes | |
1234 | */ | |
1235 | ||
1236 | typedef u8 MCAM_ADDR[ETH_ALEN]; | |
1237 | ||
1238 | struct arp_packet { | |
1239 | u8 dest_mac[ETH_ALEN]; | |
1240 | u8 src_mac[ETH_ALEN]; | |
1241 | u16 type; | |
1242 | u16 ar_hrd; | |
1243 | u16 ar_pro; | |
1244 | u8 ar_hln; | |
1245 | u8 ar_pln; | |
1246 | u16 ar_op; | |
1247 | u8 ar_sha[ETH_ALEN]; | |
1248 | u8 ar_sip[4]; | |
1249 | u8 ar_tha[ETH_ALEN]; | |
1250 | u8 ar_tip[4]; | |
1251 | } __attribute__ ((__packed__)); | |
1252 | ||
1253 | struct _magic_packet { | |
1254 | u8 dest_mac[6]; | |
1255 | u8 src_mac[6]; | |
1256 | u16 type; | |
1257 | u8 MAC[16][6]; | |
1258 | u8 password[6]; | |
1259 | } __attribute__ ((__packed__)); | |
1260 | ||
1261 | /* | |
1262 | * Store for chip context when saving and restoring status. Not | |
1263 | * all fields are saved/restored currently. | |
1264 | */ | |
1265 | ||
1266 | struct velocity_context { | |
1267 | u8 mac_reg[256]; | |
1268 | MCAM_ADDR cam_addr[MCAM_SIZE]; | |
1269 | u16 vcam[VCAM_SIZE]; | |
1270 | u32 cammask[2]; | |
1271 | u32 patcrc[2]; | |
1272 | u32 pattern[8]; | |
1273 | }; | |
1274 | ||
1275 | ||
1276 | /* | |
1277 | * MII registers. | |
1278 | */ | |
1279 | ||
1280 | ||
1281 | /* | |
1282 | * Registers in the MII (offset unit is WORD) | |
1283 | */ | |
1284 | ||
1285 | #define MII_REG_BMCR 0x00 // physical address | |
1286 | #define MII_REG_BMSR 0x01 // | |
1287 | #define MII_REG_PHYID1 0x02 // OUI | |
1288 | #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID | |
1289 | #define MII_REG_ANAR 0x04 // | |
1290 | #define MII_REG_ANLPAR 0x05 // | |
1291 | #define MII_REG_G1000CR 0x09 // | |
1292 | #define MII_REG_G1000SR 0x0A // | |
1293 | #define MII_REG_MODCFG 0x10 // | |
1294 | #define MII_REG_TCSR 0x16 // | |
1295 | #define MII_REG_PLED 0x1B // | |
1296 | // NS, MYSON only | |
1297 | #define MII_REG_PCR 0x17 // | |
1298 | // ESI only | |
1299 | #define MII_REG_PCSR 0x17 // | |
1300 | #define MII_REG_AUXCR 0x1C // | |
1301 | ||
1302 | // Marvell 88E1000/88E1000S | |
1303 | #define MII_REG_PSCR 0x10 // PHY specific control register | |
1304 | ||
1305 | // | |
1306 | // Bits in the BMCR register | |
1307 | // | |
1308 | #define BMCR_RESET 0x8000 // | |
1309 | #define BMCR_LBK 0x4000 // | |
1310 | #define BMCR_SPEED100 0x2000 // | |
1311 | #define BMCR_AUTO 0x1000 // | |
1312 | #define BMCR_PD 0x0800 // | |
1313 | #define BMCR_ISO 0x0400 // | |
1314 | #define BMCR_REAUTO 0x0200 // | |
1315 | #define BMCR_FDX 0x0100 // | |
1316 | #define BMCR_SPEED1G 0x0040 // | |
1317 | // | |
1318 | // Bits in the BMSR register | |
1319 | // | |
1320 | #define BMSR_AUTOCM 0x0020 // | |
1321 | #define BMSR_LNK 0x0004 // | |
1322 | ||
1323 | // | |
1324 | // Bits in the ANAR register | |
1325 | // | |
1326 | #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support | |
1327 | #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support | |
1328 | #define ANAR_T4 0x0200 // | |
1329 | #define ANAR_TXFD 0x0100 // | |
1330 | #define ANAR_TX 0x0080 // | |
1331 | #define ANAR_10FD 0x0040 // | |
1332 | #define ANAR_10 0x0020 // | |
1333 | // | |
1334 | // Bits in the ANLPAR register | |
1335 | // | |
1336 | #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support | |
1337 | #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support | |
1338 | #define ANLPAR_T4 0x0200 // | |
1339 | #define ANLPAR_TXFD 0x0100 // | |
1340 | #define ANLPAR_TX 0x0080 // | |
1341 | #define ANLPAR_10FD 0x0040 // | |
1342 | #define ANLPAR_10 0x0020 // | |
1343 | ||
1344 | // | |
1345 | // Bits in the G1000CR register | |
1346 | // | |
1347 | #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable | |
1348 | #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable | |
1349 | ||
1350 | // | |
1351 | // Bits in the G1000SR register | |
1352 | // | |
1353 | #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable | |
1354 | #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable | |
1355 | ||
1356 | #define TCSR_ECHODIS 0x2000 // | |
1357 | #define AUXCR_MDPPS 0x0004 // | |
1358 | ||
1359 | // Bits in the PLED register | |
1360 | #define PLED_LALBE 0x0004 // | |
1361 | ||
1362 | // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h) | |
1363 | #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit | |
1364 | ||
1365 | #define PHYID_CICADA_CS8201 0x000FC410UL | |
1366 | #define PHYID_VT3216_32BIT 0x000FC610UL | |
1367 | #define PHYID_VT3216_64BIT 0x000FC600UL | |
1368 | #define PHYID_MARVELL_1000 0x01410C50UL | |
1369 | #define PHYID_MARVELL_1000S 0x01410C40UL | |
1370 | ||
1371 | #define PHYID_REV_ID_MASK 0x0000000FUL | |
1372 | ||
1373 | #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK) | |
1374 | #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK) | |
1375 | ||
1376 | #define MII_REG_BITS_ON(x,i,p) do {\ | |
1377 | u16 w;\ | |
1378 | velocity_mii_read((p),(i),&(w));\ | |
1379 | (w)|=(x);\ | |
1380 | velocity_mii_write((p),(i),(w));\ | |
1381 | } while (0) | |
1382 | ||
1383 | #define MII_REG_BITS_OFF(x,i,p) do {\ | |
1384 | u16 w;\ | |
1385 | velocity_mii_read((p),(i),&(w));\ | |
1386 | (w)&=(~(x));\ | |
1387 | velocity_mii_write((p),(i),(w));\ | |
1388 | } while (0) | |
1389 | ||
1390 | #define MII_REG_BITS_IS_ON(x,i,p) ({\ | |
1391 | u16 w;\ | |
1392 | velocity_mii_read((p),(i),&(w));\ | |
1393 | ((int) ((w) & (x)));}) | |
1394 | ||
1395 | #define MII_GET_PHY_ID(p) ({\ | |
1396 | u32 id;\ | |
1397 | velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\ | |
1398 | velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\ | |
1399 | (id);}) | |
1400 | ||
1401 | /* | |
1402 | * Inline debug routine | |
1403 | */ | |
1404 | ||
1405 | ||
1406 | enum velocity_msg_level { | |
1407 | MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation. | |
1408 | MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified. | |
1409 | MSG_LEVEL_INFO = 2, //Normal message. | |
1410 | MSG_LEVEL_VERBOSE = 3, //Will report all trival errors. | |
1411 | MSG_LEVEL_DEBUG = 4 //Only for debug purpose. | |
1412 | }; | |
1413 | ||
1414 | #ifdef VELOCITY_DEBUG | |
1415 | #define ASSERT(x) { \ | |
1416 | if (!(x)) { \ | |
1417 | printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\ | |
1418 | __FUNCTION__, __LINE__);\ | |
1419 | BUG(); \ | |
1420 | }\ | |
1421 | } | |
1422 | #define VELOCITY_DBG(p,args...) printk(p, ##args) | |
1423 | #else | |
1424 | #define ASSERT(x) | |
1425 | #define VELOCITY_DBG(x) | |
1426 | #endif | |
1427 | ||
1428 | #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0) | |
1429 | ||
1430 | #define VELOCITY_PRT_CAMMASK(p,t) {\ | |
1431 | int i;\ | |
1432 | if ((t)==VELOCITY_MULTICAST_CAM) {\ | |
1433 | for (i=0;i<(MCAM_SIZE/8);i++)\ | |
1434 | printk("%02X",(p)->mCAMmask[i]);\ | |
1435 | }\ | |
1436 | else {\ | |
1437 | for (i=0;i<(VCAM_SIZE/8);i++)\ | |
1438 | printk("%02X",(p)->vCAMmask[i]);\ | |
1439 | }\ | |
1440 | printk("\n");\ | |
1441 | } | |
1442 | ||
1443 | ||
1444 | ||
1445 | #define VELOCITY_WOL_MAGIC 0x00000000UL | |
1446 | #define VELOCITY_WOL_PHY 0x00000001UL | |
1447 | #define VELOCITY_WOL_ARP 0x00000002UL | |
1448 | #define VELOCITY_WOL_UCAST 0x00000004UL | |
1449 | #define VELOCITY_WOL_BCAST 0x00000010UL | |
1450 | #define VELOCITY_WOL_MCAST 0x00000020UL | |
1451 | #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL | |
1452 | ||
1453 | /* | |
1454 | * Flags for options | |
1455 | */ | |
1456 | ||
1457 | #define VELOCITY_FLAGS_TAGGING 0x00000001UL | |
1458 | #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL | |
1459 | #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL | |
1460 | #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL | |
1461 | #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL | |
1462 | ||
1463 | #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL | |
1464 | ||
1465 | /* | |
1466 | * Flags for driver status | |
1467 | */ | |
1468 | ||
1469 | #define VELOCITY_FLAGS_OPENED 0x00010000UL | |
1470 | #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL | |
1471 | #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL | |
1472 | #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL | |
1473 | ||
1474 | /* | |
1475 | * Flags for MII status | |
1476 | */ | |
1477 | ||
1478 | #define VELOCITY_LINK_FAIL 0x00000001UL | |
1479 | #define VELOCITY_SPEED_10 0x00000002UL | |
1480 | #define VELOCITY_SPEED_100 0x00000004UL | |
1481 | #define VELOCITY_SPEED_1000 0x00000008UL | |
1482 | #define VELOCITY_DUPLEX_FULL 0x00000010UL | |
1483 | #define VELOCITY_AUTONEG_ENABLE 0x00000020UL | |
1484 | #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL | |
1485 | ||
1486 | /* | |
1487 | * For velocity_set_media_duplex | |
1488 | */ | |
1489 | ||
1490 | #define VELOCITY_LINK_CHANGE 0x00000001UL | |
1491 | ||
1492 | enum speed_opt { | |
1493 | SPD_DPX_AUTO = 0, | |
1494 | SPD_DPX_100_HALF = 1, | |
1495 | SPD_DPX_100_FULL = 2, | |
1496 | SPD_DPX_10_HALF = 3, | |
1497 | SPD_DPX_10_FULL = 4 | |
1498 | }; | |
1499 | ||
1500 | enum velocity_init_type { | |
1501 | VELOCITY_INIT_COLD = 0, | |
1502 | VELOCITY_INIT_RESET, | |
1503 | VELOCITY_INIT_WOL | |
1504 | }; | |
1505 | ||
1506 | enum velocity_flow_cntl_type { | |
1507 | FLOW_CNTL_DEFAULT = 1, | |
1508 | FLOW_CNTL_TX, | |
1509 | FLOW_CNTL_RX, | |
1510 | FLOW_CNTL_TX_RX, | |
1511 | FLOW_CNTL_DISABLE, | |
1512 | }; | |
1513 | ||
1514 | struct velocity_opt { | |
1515 | int numrx; /* Number of RX descriptors */ | |
1516 | int numtx; /* Number of TX descriptors */ | |
1517 | enum speed_opt spd_dpx; /* Media link mode */ | |
501e4d24 | 1518 | |
1da177e4 LT |
1519 | int DMA_length; /* DMA length */ |
1520 | int rx_thresh; /* RX_THRESH */ | |
1521 | int flow_cntl; | |
1522 | int wol_opts; /* Wake on lan options */ | |
1523 | int td_int_count; | |
1524 | int int_works; | |
1525 | int rx_bandwidth_hi; | |
1526 | int rx_bandwidth_lo; | |
1527 | int rx_bandwidth_en; | |
1528 | u32 flags; | |
1529 | }; | |
1530 | ||
1531 | struct velocity_info { | |
1532 | struct list_head list; | |
1533 | ||
1534 | struct pci_dev *pdev; | |
1535 | struct net_device *dev; | |
1536 | struct net_device_stats stats; | |
1537 | ||
1538 | dma_addr_t rd_pool_dma; | |
1539 | dma_addr_t td_pool_dma[TX_QUEUE_NO]; | |
1540 | ||
1541 | dma_addr_t tx_bufs_dma; | |
1542 | u8 *tx_bufs; | |
1543 | ||
501e4d24 | 1544 | struct vlan_group *vlgrp; |
1da177e4 LT |
1545 | u8 ip_addr[4]; |
1546 | enum chip_type chip_id; | |
1547 | ||
1548 | struct mac_regs __iomem * mac_regs; | |
1549 | unsigned long memaddr; | |
1550 | unsigned long ioaddr; | |
1da177e4 LT |
1551 | |
1552 | u8 rev_id; | |
1553 | ||
1554 | #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)])) | |
1555 | ||
1556 | int num_txq; | |
1557 | ||
1558 | volatile int td_used[TX_QUEUE_NO]; | |
1559 | int td_curr[TX_QUEUE_NO]; | |
1560 | int td_tail[TX_QUEUE_NO]; | |
1561 | struct tx_desc *td_rings[TX_QUEUE_NO]; | |
1562 | struct velocity_td_info *td_infos[TX_QUEUE_NO]; | |
1563 | ||
1564 | int rd_curr; | |
1565 | int rd_dirty; | |
1566 | u32 rd_filled; | |
1567 | struct rx_desc *rd_ring; | |
1568 | struct velocity_rd_info *rd_info; /* It's an array */ | |
1569 | ||
1570 | #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) | |
1571 | u32 mib_counter[MAX_HW_MIB_COUNTER]; | |
1572 | struct velocity_opt options; | |
1573 | ||
1574 | u32 int_mask; | |
1575 | ||
1576 | u32 flags; | |
1577 | ||
1578 | int rx_buf_sz; | |
1579 | u32 mii_status; | |
1580 | u32 phy_id; | |
1581 | int multicast_limit; | |
1582 | ||
1583 | u8 vCAMmask[(VCAM_SIZE / 8)]; | |
1584 | u8 mCAMmask[(MCAM_SIZE / 8)]; | |
1585 | ||
1586 | spinlock_t lock; | |
1587 | ||
1588 | int wol_opts; | |
1589 | u8 wol_passwd[6]; | |
1590 | ||
1591 | struct velocity_context context; | |
1592 | ||
1593 | u32 ticks; | |
1594 | u32 rx_bytes; | |
1595 | ||
1596 | }; | |
1597 | ||
1598 | /** | |
1599 | * velocity_get_ip - find an IP address for the device | |
1600 | * @vptr: Velocity to query | |
1601 | * | |
1602 | * Dig out an IP address for this interface so that we can | |
1603 | * configure wakeup with WOL for ARP. If there are multiple IP | |
1604 | * addresses on this chain then we use the first - multi-IP WOL is not | |
1605 | * supported. | |
1606 | * | |
1607 | * CHECK ME: locking | |
1608 | */ | |
1609 | ||
77933d72 | 1610 | static inline int velocity_get_ip(struct velocity_info *vptr) |
1da177e4 LT |
1611 | { |
1612 | struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr; | |
1613 | struct in_ifaddr *ifa; | |
1614 | ||
1615 | if (in_dev != NULL) { | |
1616 | ifa = (struct in_ifaddr *) in_dev->ifa_list; | |
1617 | if (ifa != NULL) { | |
1618 | memcpy(vptr->ip_addr, &ifa->ifa_address, 4); | |
1619 | return 0; | |
1620 | } | |
1621 | } | |
1622 | return -ENOENT; | |
1623 | } | |
1624 | ||
1625 | /** | |
1626 | * velocity_update_hw_mibs - fetch MIB counters from chip | |
1627 | * @vptr: velocity to update | |
1628 | * | |
1629 | * The velocity hardware keeps certain counters in the hardware | |
1630 | * side. We need to read these when the user asks for statistics | |
1631 | * or when they overflow (causing an interrupt). The read of the | |
1632 | * statistic clears it, so we keep running master counters in user | |
1633 | * space. | |
1634 | */ | |
1635 | ||
1636 | static inline void velocity_update_hw_mibs(struct velocity_info *vptr) | |
1637 | { | |
1638 | u32 tmp; | |
1639 | int i; | |
1640 | BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); | |
1641 | ||
1642 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); | |
1643 | ||
1644 | BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); | |
1645 | for (i = 0; i < HW_MIB_SIZE; i++) { | |
1646 | tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; | |
1647 | vptr->mib_counter[i] += tmp; | |
1648 | } | |
1649 | } | |
1650 | ||
1651 | /** | |
1652 | * init_flow_control_register - set up flow control | |
1653 | * @vptr: velocity to configure | |
1654 | * | |
1655 | * Configure the flow control registers for this velocity device. | |
1656 | */ | |
1657 | ||
1658 | static inline void init_flow_control_register(struct velocity_info *vptr) | |
1659 | { | |
1660 | struct mac_regs __iomem * regs = vptr->mac_regs; | |
1661 | ||
1662 | /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} | |
1663 | depend on RD=64, and Turn on XNOEN in FlowCR1 */ | |
1664 | writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); | |
1665 | writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); | |
1666 | ||
1667 | /* Set TxPauseTimer to 0xFFFF */ | |
1668 | writew(0xFFFF, ®s->tx_pause_timer); | |
1669 | ||
1670 | /* Initialize RBRDU to Rx buffer count. */ | |
1671 | writew(vptr->options.numrx, ®s->RBRDU); | |
1672 | } | |
1673 | ||
1674 | ||
1675 | #endif |