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30340998 PG |
1 | /* |
2 | * SBC8548 Device Tree Source | |
3 | * | |
4 | * Copyright 2007 Wind River Systems Inc. | |
5 | * | |
6 | * Paul Gortmaker (see MAINTAINERS for contact information) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | ||
15 | /dts-v1/; | |
16 | ||
17 | / { | |
18 | model = "SBC8548"; | |
19 | compatible = "SBC8548"; | |
20 | #address-cells = <1>; | |
21 | #size-cells = <1>; | |
22 | ||
23 | aliases { | |
24 | ethernet0 = &enet0; | |
25 | ethernet1 = &enet1; | |
26 | serial0 = &serial0; | |
27 | serial1 = &serial1; | |
28 | pci0 = &pci0; | |
29 | /* pci1 doesn't have a corresponding physical connector */ | |
30 | pci2 = &pci2; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | PowerPC,8548@0 { | |
38 | device_type = "cpu"; | |
39 | reg = <0>; | |
40 | d-cache-line-size = <0x20>; // 32 bytes | |
41 | i-cache-line-size = <0x20>; // 32 bytes | |
42 | d-cache-size = <0x8000>; // L1, 32K | |
43 | i-cache-size = <0x8000>; // L1, 32K | |
44 | timebase-frequency = <0>; // From uboot | |
45 | bus-frequency = <0>; | |
46 | clock-frequency = <0>; | |
47 | }; | |
48 | }; | |
49 | ||
50 | memory { | |
51 | device_type = "memory"; | |
52 | reg = <0x00000000 0x10000000>; | |
53 | }; | |
54 | ||
bfd123bf JM |
55 | localbus@e0000000 { |
56 | #address-cells = <2>; | |
57 | #size-cells = <1>; | |
58 | compatible = "simple-bus"; | |
59 | reg = <0xe0000000 0x5000>; | |
60 | interrupt-parent = <&mpic>; | |
61 | ||
62 | ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/ | |
63 | 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ | |
64 | 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ | |
65 | 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ | |
66 | 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/ | |
67 | ||
68 | ||
69 | flash@0,0 { | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | compatible = "cfi-flash"; | |
73 | reg = <0x0 0x0 0x800000>; | |
74 | bank-width = <1>; | |
75 | device-width = <1>; | |
76 | partition@0x0 { | |
77 | label = "space"; | |
78 | reg = <0x00000000 0x00100000>; | |
79 | }; | |
80 | partition@0x100000 { | |
81 | label = "bootloader"; | |
82 | reg = <0x00100000 0x00700000>; | |
83 | read-only; | |
84 | }; | |
85 | }; | |
86 | ||
87 | epld@5,0 { | |
88 | compatible = "wrs,epld-localbus"; | |
89 | #address-cells = <2>; | |
90 | #size-cells = <1>; | |
91 | reg = <0x5 0x0 0x00b10000>; | |
92 | ranges = < | |
93 | 0x0 0x0 0x5 0x000000 0x1fff /* LED */ | |
94 | 0x1 0x0 0x5 0x100000 0x1fff /* Switches */ | |
95 | 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */ | |
96 | 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */ | |
97 | >; | |
98 | ||
99 | led@0,0 { | |
100 | compatible = "led"; | |
101 | reg = <0x0 0x0 0x1fff>; | |
102 | }; | |
103 | ||
104 | switches@1,0 { | |
105 | compatible = "switches"; | |
106 | reg = <0x1 0x0 0x1fff>; | |
107 | }; | |
108 | ||
109 | hw-rev@3,0 { | |
110 | compatible = "hw-rev"; | |
111 | reg = <0x3 0x0 0x1fff>; | |
112 | }; | |
113 | ||
114 | eeprom@b,0 { | |
115 | compatible = "eeprom"; | |
116 | reg = <0xb 0 0x1fff>; | |
117 | }; | |
118 | ||
119 | }; | |
120 | ||
121 | alt-flash@6,0 { | |
122 | #address-cells = <1>; | |
123 | #size-cells = <1>; | |
124 | reg = <0x6 0x0 0x04000000>; | |
125 | compatible = "cfi-flash"; | |
126 | bank-width = <4>; | |
127 | device-width = <1>; | |
128 | partition@0x0 { | |
129 | label = "bootloader"; | |
130 | reg = <0x00000000 0x00100000>; | |
131 | read-only; | |
132 | }; | |
133 | partition@0x00100000 { | |
134 | label = "file-system"; | |
135 | reg = <0x00100000 0x01f00000>; | |
136 | }; | |
137 | partition@0x02000000 { | |
138 | label = "boot-config"; | |
139 | reg = <0x02000000 0x00100000>; | |
140 | }; | |
141 | partition@0x02100000 { | |
142 | label = "space"; | |
143 | reg = <0x02100000 0x01f00000>; | |
144 | }; | |
145 | }; | |
146 | }; | |
147 | ||
30340998 PG |
148 | soc8548@e0000000 { |
149 | #address-cells = <1>; | |
150 | #size-cells = <1>; | |
151 | device_type = "soc"; | |
152 | ranges = <0x00000000 0xe0000000 0x00100000>; | |
153 | reg = <0xe0000000 0x00001000>; // CCSRBAR | |
154 | bus-frequency = <0>; | |
bfd123bf | 155 | compatible = "simple-bus"; |
30340998 PG |
156 | |
157 | memory-controller@2000 { | |
158 | compatible = "fsl,8548-memory-controller"; | |
159 | reg = <0x2000 0x1000>; | |
160 | interrupt-parent = <&mpic>; | |
161 | interrupts = <0x12 0x2>; | |
162 | }; | |
163 | ||
164 | l2-cache-controller@20000 { | |
165 | compatible = "fsl,8548-l2-cache-controller"; | |
166 | reg = <0x20000 0x1000>; | |
167 | cache-line-size = <0x20>; // 32 bytes | |
168 | cache-size = <0x80000>; // L2, 512K | |
169 | interrupt-parent = <&mpic>; | |
170 | interrupts = <0x10 0x2>; | |
171 | }; | |
172 | ||
173 | i2c@3000 { | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | cell-index = <0>; | |
177 | compatible = "fsl-i2c"; | |
178 | reg = <0x3000 0x100>; | |
179 | interrupts = <0x2b 0x2>; | |
180 | interrupt-parent = <&mpic>; | |
181 | dfsrr; | |
182 | }; | |
183 | ||
184 | i2c@3100 { | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | cell-index = <1>; | |
188 | compatible = "fsl-i2c"; | |
189 | reg = <0x3100 0x100>; | |
190 | interrupts = <0x2b 0x2>; | |
191 | interrupt-parent = <&mpic>; | |
192 | dfsrr; | |
193 | }; | |
194 | ||
195 | mdio@24520 { | |
196 | #address-cells = <1>; | |
197 | #size-cells = <0>; | |
198 | compatible = "fsl,gianfar-mdio"; | |
199 | reg = <0x24520 0x20>; | |
200 | ||
201 | phy0: ethernet-phy@19 { | |
202 | interrupt-parent = <&mpic>; | |
203 | interrupts = <0x6 0x1>; | |
204 | reg = <0x19>; | |
205 | device_type = "ethernet-phy"; | |
206 | }; | |
207 | phy1: ethernet-phy@1a { | |
208 | interrupt-parent = <&mpic>; | |
209 | interrupts = <0x7 0x1>; | |
210 | reg = <0x1a>; | |
211 | device_type = "ethernet-phy"; | |
212 | }; | |
213 | }; | |
214 | ||
215 | enet0: ethernet@24000 { | |
216 | cell-index = <0>; | |
217 | device_type = "network"; | |
218 | model = "eTSEC"; | |
219 | compatible = "gianfar"; | |
220 | reg = <0x24000 0x1000>; | |
221 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
222 | interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; | |
223 | interrupt-parent = <&mpic>; | |
224 | phy-handle = <&phy0>; | |
225 | }; | |
226 | ||
227 | enet1: ethernet@25000 { | |
228 | cell-index = <1>; | |
229 | device_type = "network"; | |
230 | model = "eTSEC"; | |
231 | compatible = "gianfar"; | |
232 | reg = <0x25000 0x1000>; | |
233 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
234 | interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; | |
235 | interrupt-parent = <&mpic>; | |
236 | phy-handle = <&phy1>; | |
237 | }; | |
238 | ||
239 | serial0: serial@4500 { | |
240 | cell-index = <0>; | |
241 | device_type = "serial"; | |
242 | compatible = "ns16550"; | |
243 | reg = <0x4500 0x100>; // reg base, size | |
244 | clock-frequency = <0>; // should we fill in in uboot? | |
245 | interrupts = <0x2a 0x2>; | |
246 | interrupt-parent = <&mpic>; | |
247 | }; | |
248 | ||
249 | serial1: serial@4600 { | |
250 | cell-index = <1>; | |
251 | device_type = "serial"; | |
252 | compatible = "ns16550"; | |
253 | reg = <0x4600 0x100>; // reg base, size | |
254 | clock-frequency = <0>; // should we fill in in uboot? | |
255 | interrupts = <0x2a 0x2>; | |
256 | interrupt-parent = <&mpic>; | |
257 | }; | |
258 | ||
259 | global-utilities@e0000 { //global utilities reg | |
260 | compatible = "fsl,mpc8548-guts"; | |
261 | reg = <0xe0000 0x1000>; | |
262 | fsl,has-rstcr; | |
263 | }; | |
264 | ||
265 | mpic: pic@40000 { | |
266 | interrupt-controller; | |
267 | #address-cells = <0>; | |
268 | #size-cells = <0>; | |
269 | #interrupt-cells = <2>; | |
270 | reg = <0x40000 0x40000>; | |
271 | compatible = "chrp,open-pic"; | |
272 | device_type = "open-pic"; | |
273 | big-endian; | |
274 | }; | |
275 | }; | |
276 | ||
277 | pci0: pci@e0008000 { | |
278 | cell-index = <0>; | |
279 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
280 | interrupt-map = < | |
3e0d65bf JM |
281 | /* IDSEL 0x01 (PCI-X slot) @66MHz */ |
282 | 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
283 | 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
284 | 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
285 | 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1 | |
286 | ||
287 | /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */ | |
288 | 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 | |
289 | 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 | |
290 | 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 | |
291 | 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>; | |
30340998 PG |
292 | |
293 | interrupt-parent = <&mpic>; | |
294 | interrupts = <0x18 0x2>; | |
295 | bus-range = <0 0>; | |
296 | ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
297 | 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; | |
298 | clock-frequency = <66666666>; | |
299 | #interrupt-cells = <1>; | |
300 | #size-cells = <2>; | |
301 | #address-cells = <3>; | |
302 | reg = <0xe0008000 0x1000>; | |
303 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | |
304 | device_type = "pci"; | |
305 | }; | |
306 | ||
307 | pci2: pcie@e000a000 { | |
308 | cell-index = <2>; | |
309 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
310 | interrupt-map = < | |
311 | ||
312 | /* IDSEL 0x0 (PEX) */ | |
313 | 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 | |
314 | 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 | |
315 | 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 | |
316 | 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>; | |
317 | ||
318 | interrupt-parent = <&mpic>; | |
319 | interrupts = <0x1a 0x2>; | |
320 | bus-range = <0x0 0xff>; | |
321 | ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 | |
322 | 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>; | |
323 | clock-frequency = <33333333>; | |
324 | #interrupt-cells = <1>; | |
325 | #size-cells = <2>; | |
326 | #address-cells = <3>; | |
327 | reg = <0xe000a000 0x1000>; | |
328 | compatible = "fsl,mpc8548-pcie"; | |
329 | device_type = "pci"; | |
330 | pcie@0 { | |
331 | reg = <0x0 0x0 0x0 0x0 0x0>; | |
332 | #size-cells = <2>; | |
333 | #address-cells = <3>; | |
334 | device_type = "pci"; | |
335 | ranges = <0x02000000 0x0 0xa0000000 | |
336 | 0x02000000 0x0 0xa0000000 | |
337 | 0x0 0x20000000 | |
338 | ||
339 | 0x01000000 0x0 0x00000000 | |
340 | 0x01000000 0x0 0x00000000 | |
341 | 0x0 0x08000000>; | |
342 | }; | |
343 | }; | |
344 | }; |