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1da177e4 LT |
1 | /* |
2 | * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000 | |
3 | * | |
4 | * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * May be copied or modified under the terms of the GNU General Public License | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Special Thanks to Mark for his Six years of work. | |
10 | * | |
11 | * Copyright (c) 1995-1998 Mark Lord | |
12 | * May be copied or modified under the terms of the GNU General Public License | |
13 | */ | |
14 | ||
15 | /* | |
16 | * This module provides support for the bus-master IDE DMA functions | |
17 | * of various PCI chipsets, including the Intel PIIX (i82371FB for | |
18 | * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and | |
19 | * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset) | |
20 | * ("PIIX" stands for "PCI ISA IDE Xcellerator"). | |
21 | * | |
22 | * Pretty much the same code works for other IDE PCI bus-mastering chipsets. | |
23 | * | |
24 | * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies). | |
25 | * | |
26 | * By default, DMA support is prepared for use, but is currently enabled only | |
27 | * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single), | |
28 | * or which are recognized as "good" (see table below). Drives with only mode0 | |
29 | * or mode1 (multi/single) DMA should also work with this chipset/driver | |
30 | * (eg. MC2112A) but are not enabled by default. | |
31 | * | |
32 | * Use "hdparm -i" to view modes supported by a given drive. | |
33 | * | |
34 | * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling | |
35 | * DMA support, but must be (re-)compiled against this kernel version or later. | |
36 | * | |
37 | * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting. | |
38 | * If problems arise, ide.c will disable DMA operation after a few retries. | |
39 | * This error recovery mechanism works and has been extremely well exercised. | |
40 | * | |
41 | * IDE drives, depending on their vintage, may support several different modes | |
42 | * of DMA operation. The boot-time modes are indicated with a "*" in | |
43 | * the "hdparm -i" listing, and can be changed with *knowledgeable* use of | |
44 | * the "hdparm -X" feature. There is seldom a need to do this, as drives | |
45 | * normally power-up with their "best" PIO/DMA modes enabled. | |
46 | * | |
47 | * Testing has been done with a rather extensive number of drives, | |
48 | * with Quantum & Western Digital models generally outperforming the pack, | |
49 | * and Fujitsu & Conner (and some Seagate which are really Conner) drives | |
50 | * showing more lackluster throughput. | |
51 | * | |
52 | * Keep an eye on /var/adm/messages for "DMA disabled" messages. | |
53 | * | |
54 | * Some people have reported trouble with Intel Zappa motherboards. | |
55 | * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0, | |
56 | * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe | |
57 | * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this). | |
58 | * | |
59 | * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for | |
60 | * fixing the problem with the BIOS on some Acer motherboards. | |
61 | * | |
62 | * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing | |
63 | * "TX" chipset compatibility and for providing patches for the "TX" chipset. | |
64 | * | |
65 | * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack | |
66 | * at generic DMA -- his patches were referred to when preparing this code. | |
67 | * | |
68 | * Most importantly, thanks to Robert Bringman <rob@mars.trion.com> | |
69 | * for supplying a Promise UDMA board & WD UDMA drive for this work! | |
70 | * | |
71 | * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports. | |
72 | * | |
73 | * ATA-66/100 and recovery functions, I forgot the rest...... | |
74 | * | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/kernel.h> | |
80 | #include <linux/timer.h> | |
81 | #include <linux/mm.h> | |
82 | #include <linux/interrupt.h> | |
83 | #include <linux/pci.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/ide.h> | |
86 | #include <linux/delay.h> | |
87 | #include <linux/scatterlist.h> | |
88 | ||
89 | #include <asm/io.h> | |
90 | #include <asm/irq.h> | |
91 | ||
1da177e4 LT |
92 | static const struct drive_list_entry drive_whitelist [] = { |
93 | ||
c2d3ce8c JH |
94 | { "Micropolis 2112A" , NULL }, |
95 | { "CONNER CTMA 4000" , NULL }, | |
96 | { "CONNER CTT8000-A" , NULL }, | |
97 | { "ST34342A" , NULL }, | |
1da177e4 LT |
98 | { NULL , NULL } |
99 | }; | |
100 | ||
101 | static const struct drive_list_entry drive_blacklist [] = { | |
102 | ||
c2d3ce8c JH |
103 | { "WDC AC11000H" , NULL }, |
104 | { "WDC AC22100H" , NULL }, | |
105 | { "WDC AC32500H" , NULL }, | |
106 | { "WDC AC33100H" , NULL }, | |
107 | { "WDC AC31600H" , NULL }, | |
1da177e4 LT |
108 | { "WDC AC32100H" , "24.09P07" }, |
109 | { "WDC AC23200L" , "21.10N21" }, | |
c2d3ce8c JH |
110 | { "Compaq CRD-8241B" , NULL }, |
111 | { "CRD-8400B" , NULL }, | |
112 | { "CRD-8480B", NULL }, | |
113 | { "CRD-8482B", NULL }, | |
114 | { "CRD-84" , NULL }, | |
115 | { "SanDisk SDP3B" , NULL }, | |
116 | { "SanDisk SDP3B-64" , NULL }, | |
117 | { "SANYO CD-ROM CRD" , NULL }, | |
118 | { "HITACHI CDR-8" , NULL }, | |
119 | { "HITACHI CDR-8335" , NULL }, | |
120 | { "HITACHI CDR-8435" , NULL }, | |
121 | { "Toshiba CD-ROM XM-6202B" , NULL }, | |
122 | { "TOSHIBA CD-ROM XM-1702BC", NULL }, | |
123 | { "CD-532E-A" , NULL }, | |
124 | { "E-IDE CD-ROM CR-840", NULL }, | |
125 | { "CD-ROM Drive/F5A", NULL }, | |
126 | { "WPI CDD-820", NULL }, | |
127 | { "SAMSUNG CD-ROM SC-148C", NULL }, | |
128 | { "SAMSUNG CD-ROM SC", NULL }, | |
129 | { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL }, | |
130 | { "_NEC DV5800A", NULL }, | |
5a6248ca | 131 | { "SAMSUNG CD-ROM SN-124", "N001" }, |
c2d3ce8c | 132 | { "Seagate STT20000A", NULL }, |
b0bc65b9 | 133 | { "CD-ROM CDR_U200", "1.09" }, |
1da177e4 LT |
134 | { NULL , NULL } |
135 | ||
136 | }; | |
137 | ||
1da177e4 LT |
138 | /** |
139 | * ide_dma_intr - IDE DMA interrupt handler | |
140 | * @drive: the drive the interrupt is for | |
141 | * | |
142 | * Handle an interrupt completing a read/write DMA transfer on an | |
143 | * IDE device | |
144 | */ | |
145 | ||
146 | ide_startstop_t ide_dma_intr (ide_drive_t *drive) | |
147 | { | |
148 | u8 stat = 0, dma_stat = 0; | |
149 | ||
150 | dma_stat = HWIF(drive)->ide_dma_end(drive); | |
151 | stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ | |
152 | if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { | |
153 | if (!dma_stat) { | |
154 | struct request *rq = HWGROUP(drive)->rq; | |
155 | ||
4d7a984b | 156 | task_end_request(drive, rq, stat); |
1da177e4 LT |
157 | return ide_stopped; |
158 | } | |
159 | printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n", | |
160 | drive->name, dma_stat); | |
161 | } | |
162 | return ide_error(drive, "dma_intr", stat); | |
163 | } | |
164 | ||
165 | EXPORT_SYMBOL_GPL(ide_dma_intr); | |
166 | ||
75d7d963 BZ |
167 | static int ide_dma_good_drive(ide_drive_t *drive) |
168 | { | |
169 | return ide_in_drive_list(drive->id, drive_whitelist); | |
170 | } | |
171 | ||
1da177e4 LT |
172 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
173 | /** | |
174 | * ide_build_sglist - map IDE scatter gather for DMA I/O | |
175 | * @drive: the drive to build the DMA table for | |
176 | * @rq: the request holding the sg list | |
177 | * | |
178 | * Perform the PCI mapping magic necessary to access the source or | |
179 | * target buffers of a request via PCI DMA. The lower layers of the | |
180 | * kernel provide the necessary cache management so that we can | |
181 | * operate in a portable fashion | |
182 | */ | |
183 | ||
184 | int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |
185 | { | |
186 | ide_hwif_t *hwif = HWIF(drive); | |
187 | struct scatterlist *sg = hwif->sg_table; | |
188 | ||
4aff5e23 | 189 | BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256); |
1da177e4 LT |
190 | |
191 | ide_map_sg(drive, rq); | |
192 | ||
193 | if (rq_data_dir(rq) == READ) | |
194 | hwif->sg_dma_direction = PCI_DMA_FROMDEVICE; | |
195 | else | |
196 | hwif->sg_dma_direction = PCI_DMA_TODEVICE; | |
197 | ||
198 | return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction); | |
199 | } | |
200 | ||
201 | EXPORT_SYMBOL_GPL(ide_build_sglist); | |
202 | ||
203 | /** | |
204 | * ide_build_dmatable - build IDE DMA table | |
205 | * | |
206 | * ide_build_dmatable() prepares a dma request. We map the command | |
207 | * to get the pci bus addresses of the buffers and then build up | |
208 | * the PRD table that the IDE layer wants to be fed. The code | |
209 | * knows about the 64K wrap bug in the CS5530. | |
210 | * | |
211 | * Returns the number of built PRD entries if all went okay, | |
212 | * returns 0 otherwise. | |
213 | * | |
214 | * May also be invoked from trm290.c | |
215 | */ | |
216 | ||
217 | int ide_build_dmatable (ide_drive_t *drive, struct request *rq) | |
218 | { | |
219 | ide_hwif_t *hwif = HWIF(drive); | |
220 | unsigned int *table = hwif->dmatable_cpu; | |
221 | unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0; | |
222 | unsigned int count = 0; | |
223 | int i; | |
224 | struct scatterlist *sg; | |
225 | ||
226 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
227 | ||
228 | if (!i) | |
229 | return 0; | |
230 | ||
231 | sg = hwif->sg_table; | |
232 | while (i) { | |
233 | u32 cur_addr; | |
234 | u32 cur_len; | |
235 | ||
236 | cur_addr = sg_dma_address(sg); | |
237 | cur_len = sg_dma_len(sg); | |
238 | ||
239 | /* | |
240 | * Fill in the dma table, without crossing any 64kB boundaries. | |
241 | * Most hardware requires 16-bit alignment of all blocks, | |
242 | * but the trm290 requires 32-bit alignment. | |
243 | */ | |
244 | ||
245 | while (cur_len) { | |
246 | if (count++ >= PRD_ENTRIES) { | |
247 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
248 | goto use_pio_instead; | |
249 | } else { | |
250 | u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff); | |
251 | ||
252 | if (bcount > cur_len) | |
253 | bcount = cur_len; | |
254 | *table++ = cpu_to_le32(cur_addr); | |
255 | xcount = bcount & 0xffff; | |
256 | if (is_trm290) | |
257 | xcount = ((xcount >> 2) - 1) << 16; | |
258 | if (xcount == 0x0000) { | |
259 | /* | |
260 | * Most chipsets correctly interpret a length of 0x0000 as 64KB, | |
261 | * but at least one (e.g. CS5530) misinterprets it as zero (!). | |
262 | * So here we break the 64KB entry into two 32KB entries instead. | |
263 | */ | |
264 | if (count++ >= PRD_ENTRIES) { | |
265 | printk(KERN_ERR "%s: DMA table too small\n", drive->name); | |
266 | goto use_pio_instead; | |
267 | } | |
268 | *table++ = cpu_to_le32(0x8000); | |
269 | *table++ = cpu_to_le32(cur_addr + 0x8000); | |
270 | xcount = 0x8000; | |
271 | } | |
272 | *table++ = cpu_to_le32(xcount); | |
273 | cur_addr += bcount; | |
274 | cur_len -= bcount; | |
275 | } | |
276 | } | |
277 | ||
55c16a70 | 278 | sg = sg_next(sg); |
1da177e4 LT |
279 | i--; |
280 | } | |
281 | ||
282 | if (count) { | |
283 | if (!is_trm290) | |
284 | *--table |= cpu_to_le32(0x80000000); | |
285 | return count; | |
286 | } | |
287 | printk(KERN_ERR "%s: empty DMA table?\n", drive->name); | |
288 | use_pio_instead: | |
289 | pci_unmap_sg(hwif->pci_dev, | |
290 | hwif->sg_table, | |
291 | hwif->sg_nents, | |
292 | hwif->sg_dma_direction); | |
293 | return 0; /* revert to PIO for this request */ | |
294 | } | |
295 | ||
296 | EXPORT_SYMBOL_GPL(ide_build_dmatable); | |
297 | ||
298 | /** | |
299 | * ide_destroy_dmatable - clean up DMA mapping | |
300 | * @drive: The drive to unmap | |
301 | * | |
302 | * Teardown mappings after DMA has completed. This must be called | |
303 | * after the completion of each use of ide_build_dmatable and before | |
304 | * the next use of ide_build_dmatable. Failure to do so will cause | |
305 | * an oops as only one mapping can be live for each target at a given | |
306 | * time. | |
307 | */ | |
308 | ||
309 | void ide_destroy_dmatable (ide_drive_t *drive) | |
310 | { | |
311 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
312 | struct scatterlist *sg = HWIF(drive)->sg_table; | |
313 | int nents = HWIF(drive)->sg_nents; | |
314 | ||
315 | pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction); | |
316 | } | |
317 | ||
318 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | |
319 | ||
320 | /** | |
321 | * config_drive_for_dma - attempt to activate IDE DMA | |
322 | * @drive: the drive to place in DMA mode | |
323 | * | |
324 | * If the drive supports at least mode 2 DMA or UDMA of any kind | |
325 | * then attempt to place it into DMA mode. Drives that are known to | |
326 | * support DMA but predate the DMA properties or that are known | |
327 | * to have DMA handling bugs are also set up appropriately based | |
328 | * on the good/bad drive lists. | |
329 | */ | |
330 | ||
331 | static int config_drive_for_dma (ide_drive_t *drive) | |
332 | { | |
1116fae5 | 333 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 | 334 | struct hd_driveid *id = drive->id; |
1da177e4 | 335 | |
33c1002e BZ |
336 | if (drive->media != ide_disk) { |
337 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
bcbf6ee3 | 338 | return 0; |
33c1002e | 339 | } |
1116fae5 | 340 | |
0ae2e178 BZ |
341 | /* |
342 | * Enable DMA on any drive that has | |
343 | * UltraDMA (mode 0/1/2/3/4/5/6) enabled | |
344 | */ | |
345 | if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f)) | |
346 | return 1; | |
347 | ||
348 | /* | |
349 | * Enable DMA on any drive that has mode2 DMA | |
350 | * (multi or single) enabled | |
351 | */ | |
352 | if (id->field_valid & 2) /* regular DMA */ | |
353 | if ((id->dma_mword & 0x404) == 0x404 || | |
354 | (id->dma_1word & 0x404) == 0x404) | |
355 | return 1; | |
3608b5d7 | 356 | |
0ae2e178 BZ |
357 | /* Consult the list of known "good" drives */ |
358 | if (ide_dma_good_drive(drive)) | |
359 | return 1; | |
360 | ||
361 | return 0; | |
1da177e4 LT |
362 | } |
363 | ||
364 | /** | |
365 | * dma_timer_expiry - handle a DMA timeout | |
366 | * @drive: Drive that timed out | |
367 | * | |
368 | * An IDE DMA transfer timed out. In the event of an error we ask | |
369 | * the driver to resolve the problem, if a DMA transfer is still | |
370 | * in progress we continue to wait (arguably we need to add a | |
371 | * secondary 'I don't care what the drive thinks' timeout here) | |
372 | * Finally if we have an interrupt we let it complete the I/O. | |
373 | * But only one time - we clear expiry and if it's still not | |
374 | * completed after WAIT_CMD, we error and retry in PIO. | |
375 | * This can occur if an interrupt is lost or due to hang or bugs. | |
376 | */ | |
377 | ||
378 | static int dma_timer_expiry (ide_drive_t *drive) | |
379 | { | |
380 | ide_hwif_t *hwif = HWIF(drive); | |
381 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
382 | ||
383 | printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n", | |
384 | drive->name, dma_stat); | |
385 | ||
386 | if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */ | |
387 | return WAIT_CMD; | |
388 | ||
389 | HWGROUP(drive)->expiry = NULL; /* one free ride for now */ | |
390 | ||
391 | /* 1 dmaing, 2 error, 4 intr */ | |
392 | if (dma_stat & 2) /* ERROR */ | |
393 | return -1; | |
394 | ||
395 | if (dma_stat & 1) /* DMAing */ | |
396 | return WAIT_CMD; | |
397 | ||
398 | if (dma_stat & 4) /* Got an Interrupt */ | |
399 | return WAIT_CMD; | |
400 | ||
401 | return 0; /* Status is unknown -- reset the bus */ | |
402 | } | |
403 | ||
404 | /** | |
15ce926a | 405 | * ide_dma_host_set - Enable/disable DMA on a host |
1da177e4 LT |
406 | * @drive: drive to control |
407 | * | |
15ce926a BZ |
408 | * Enable/disable DMA on an IDE controller following generic |
409 | * bus-mastering IDE controller behaviour. | |
1da177e4 LT |
410 | */ |
411 | ||
15ce926a | 412 | void ide_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 LT |
413 | { |
414 | ide_hwif_t *hwif = HWIF(drive); | |
415 | u8 unit = (drive->select.b.unit & 0x01); | |
416 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
417 | ||
15ce926a BZ |
418 | if (on) |
419 | dma_stat |= (1 << (5 + unit)); | |
420 | else | |
421 | dma_stat &= ~(1 << (5 + unit)); | |
422 | ||
423 | hwif->OUTB(dma_stat, hwif->dma_status); | |
1da177e4 LT |
424 | } |
425 | ||
15ce926a | 426 | EXPORT_SYMBOL_GPL(ide_dma_host_set); |
4a546e04 | 427 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
428 | |
429 | /** | |
7469aaf6 | 430 | * ide_dma_off_quietly - Generic DMA kill |
1da177e4 LT |
431 | * @drive: drive to control |
432 | * | |
433 | * Turn off the current DMA on this IDE controller. | |
434 | */ | |
435 | ||
7469aaf6 | 436 | void ide_dma_off_quietly(ide_drive_t *drive) |
1da177e4 LT |
437 | { |
438 | drive->using_dma = 0; | |
439 | ide_toggle_bounce(drive, 0); | |
440 | ||
15ce926a | 441 | drive->hwif->dma_host_set(drive, 0); |
1da177e4 LT |
442 | } |
443 | ||
7469aaf6 | 444 | EXPORT_SYMBOL(ide_dma_off_quietly); |
1da177e4 LT |
445 | |
446 | /** | |
7469aaf6 | 447 | * ide_dma_off - disable DMA on a device |
1da177e4 LT |
448 | * @drive: drive to disable DMA on |
449 | * | |
450 | * Disable IDE DMA for a device on this IDE controller. | |
451 | * Inform the user that DMA has been disabled. | |
452 | */ | |
453 | ||
7469aaf6 | 454 | void ide_dma_off(ide_drive_t *drive) |
1da177e4 LT |
455 | { |
456 | printk(KERN_INFO "%s: DMA disabled\n", drive->name); | |
4a546e04 | 457 | ide_dma_off_quietly(drive); |
1da177e4 LT |
458 | } |
459 | ||
7469aaf6 | 460 | EXPORT_SYMBOL(ide_dma_off); |
1da177e4 | 461 | |
1da177e4 | 462 | /** |
4a546e04 | 463 | * ide_dma_on - Enable DMA on a device |
1da177e4 LT |
464 | * @drive: drive to enable DMA on |
465 | * | |
466 | * Enable IDE DMA for a device on this IDE controller. | |
467 | */ | |
4a546e04 BZ |
468 | |
469 | void ide_dma_on(ide_drive_t *drive) | |
1da177e4 | 470 | { |
1da177e4 LT |
471 | drive->using_dma = 1; |
472 | ide_toggle_bounce(drive, 1); | |
473 | ||
15ce926a | 474 | drive->hwif->dma_host_set(drive, 1); |
1da177e4 LT |
475 | } |
476 | ||
4a546e04 | 477 | EXPORT_SYMBOL(ide_dma_on); |
1da177e4 | 478 | |
4a546e04 | 479 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
480 | /** |
481 | * ide_dma_setup - begin a DMA phase | |
482 | * @drive: target device | |
483 | * | |
484 | * Build an IDE DMA PRD (IDE speak for scatter gather table) | |
485 | * and then set up the DMA transfer registers for a device | |
486 | * that follows generic IDE PCI DMA behaviour. Controllers can | |
487 | * override this function if they need to | |
488 | * | |
489 | * Returns 0 on success. If a PIO fallback is required then 1 | |
490 | * is returned. | |
491 | */ | |
492 | ||
493 | int ide_dma_setup(ide_drive_t *drive) | |
494 | { | |
495 | ide_hwif_t *hwif = drive->hwif; | |
496 | struct request *rq = HWGROUP(drive)->rq; | |
497 | unsigned int reading; | |
498 | u8 dma_stat; | |
499 | ||
500 | if (rq_data_dir(rq)) | |
501 | reading = 0; | |
502 | else | |
503 | reading = 1 << 3; | |
504 | ||
505 | /* fall back to pio! */ | |
506 | if (!ide_build_dmatable(drive, rq)) { | |
507 | ide_map_sg(drive, rq); | |
508 | return 1; | |
509 | } | |
510 | ||
511 | /* PRD table */ | |
2ad1e558 | 512 | if (hwif->mmio) |
0ecdca26 BZ |
513 | writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); |
514 | else | |
515 | outl(hwif->dmatable_dma, hwif->dma_prdtable); | |
1da177e4 LT |
516 | |
517 | /* specify r/w */ | |
518 | hwif->OUTB(reading, hwif->dma_command); | |
519 | ||
520 | /* read dma_status for INTR & ERROR flags */ | |
521 | dma_stat = hwif->INB(hwif->dma_status); | |
522 | ||
523 | /* clear INTR & ERROR flags */ | |
524 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
525 | drive->waiting_for_dma = 1; | |
526 | return 0; | |
527 | } | |
528 | ||
529 | EXPORT_SYMBOL_GPL(ide_dma_setup); | |
530 | ||
531 | static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command) | |
532 | { | |
533 | /* issue cmd to drive */ | |
534 | ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry); | |
535 | } | |
536 | ||
537 | void ide_dma_start(ide_drive_t *drive) | |
538 | { | |
539 | ide_hwif_t *hwif = HWIF(drive); | |
540 | u8 dma_cmd = hwif->INB(hwif->dma_command); | |
541 | ||
542 | /* Note that this is done *after* the cmd has | |
543 | * been issued to the drive, as per the BM-IDE spec. | |
544 | * The Promise Ultra33 doesn't work correctly when | |
545 | * we do this part before issuing the drive cmd. | |
546 | */ | |
547 | /* start DMA */ | |
548 | hwif->OUTB(dma_cmd|1, hwif->dma_command); | |
549 | hwif->dma = 1; | |
550 | wmb(); | |
551 | } | |
552 | ||
553 | EXPORT_SYMBOL_GPL(ide_dma_start); | |
554 | ||
555 | /* returns 1 on error, 0 otherwise */ | |
556 | int __ide_dma_end (ide_drive_t *drive) | |
557 | { | |
558 | ide_hwif_t *hwif = HWIF(drive); | |
559 | u8 dma_stat = 0, dma_cmd = 0; | |
560 | ||
561 | drive->waiting_for_dma = 0; | |
562 | /* get dma_command mode */ | |
563 | dma_cmd = hwif->INB(hwif->dma_command); | |
564 | /* stop DMA */ | |
565 | hwif->OUTB(dma_cmd&~1, hwif->dma_command); | |
566 | /* get DMA status */ | |
567 | dma_stat = hwif->INB(hwif->dma_status); | |
568 | /* clear the INTR & ERROR bits */ | |
569 | hwif->OUTB(dma_stat|6, hwif->dma_status); | |
570 | /* purge DMA mappings */ | |
571 | ide_destroy_dmatable(drive); | |
572 | /* verify good DMA status */ | |
573 | hwif->dma = 0; | |
574 | wmb(); | |
575 | return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0; | |
576 | } | |
577 | ||
578 | EXPORT_SYMBOL(__ide_dma_end); | |
579 | ||
580 | /* returns 1 if dma irq issued, 0 otherwise */ | |
581 | static int __ide_dma_test_irq(ide_drive_t *drive) | |
582 | { | |
583 | ide_hwif_t *hwif = HWIF(drive); | |
584 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
585 | ||
1da177e4 LT |
586 | /* return 1 if INTR asserted */ |
587 | if ((dma_stat & 4) == 4) | |
588 | return 1; | |
589 | if (!drive->waiting_for_dma) | |
590 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
591 | drive->name, __FUNCTION__); | |
592 | return 0; | |
593 | } | |
0ae2e178 BZ |
594 | #else |
595 | static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } | |
1da177e4 LT |
596 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
597 | ||
598 | int __ide_dma_bad_drive (ide_drive_t *drive) | |
599 | { | |
600 | struct hd_driveid *id = drive->id; | |
601 | ||
65e5f2e3 | 602 | int blacklist = ide_in_drive_list(id, drive_blacklist); |
1da177e4 LT |
603 | if (blacklist) { |
604 | printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n", | |
605 | drive->name, id->model); | |
606 | return blacklist; | |
607 | } | |
608 | return 0; | |
609 | } | |
610 | ||
611 | EXPORT_SYMBOL(__ide_dma_bad_drive); | |
612 | ||
2d5eaa6d BZ |
613 | static const u8 xfer_mode_bases[] = { |
614 | XFER_UDMA_0, | |
615 | XFER_MW_DMA_0, | |
616 | XFER_SW_DMA_0, | |
617 | }; | |
618 | ||
7670df73 | 619 | static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) |
2d5eaa6d BZ |
620 | { |
621 | struct hd_driveid *id = drive->id; | |
622 | ide_hwif_t *hwif = drive->hwif; | |
623 | unsigned int mask = 0; | |
624 | ||
625 | switch(base) { | |
626 | case XFER_UDMA_0: | |
627 | if ((id->field_valid & 4) == 0) | |
628 | break; | |
629 | ||
2d5eaa6d | 630 | if (hwif->udma_filter) |
851dd33b SS |
631 | mask = hwif->udma_filter(drive); |
632 | else | |
633 | mask = hwif->ultra_mask; | |
634 | mask &= id->dma_ultra; | |
2d5eaa6d | 635 | |
7670df73 BZ |
636 | /* |
637 | * avoid false cable warning from eighty_ninty_three() | |
638 | */ | |
639 | if (req_mode > XFER_UDMA_2) { | |
640 | if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) | |
641 | mask &= 0x07; | |
642 | } | |
2d5eaa6d BZ |
643 | break; |
644 | case XFER_MW_DMA_0: | |
b4e44369 SS |
645 | if ((id->field_valid & 2) == 0) |
646 | break; | |
647 | if (hwif->mdma_filter) | |
648 | mask = hwif->mdma_filter(drive); | |
649 | else | |
650 | mask = hwif->mwdma_mask; | |
651 | mask &= id->dma_mword; | |
2d5eaa6d BZ |
652 | break; |
653 | case XFER_SW_DMA_0: | |
15a4f943 | 654 | if (id->field_valid & 2) { |
3649c06e | 655 | mask = id->dma_1word & hwif->swdma_mask; |
15a4f943 BZ |
656 | } else if (id->tDMA) { |
657 | /* | |
658 | * ide_fix_driveid() doesn't convert ->tDMA to the | |
659 | * CPU endianness so we need to do it here | |
660 | */ | |
661 | u8 mode = le16_to_cpu(id->tDMA); | |
662 | ||
663 | /* | |
664 | * if the mode is valid convert it to the mask | |
665 | * (the maximum allowed mode is XFER_SW_DMA_2) | |
666 | */ | |
667 | if (mode <= 2) | |
668 | mask = ((2 << mode) - 1) & hwif->swdma_mask; | |
669 | } | |
2d5eaa6d BZ |
670 | break; |
671 | default: | |
672 | BUG(); | |
673 | break; | |
674 | } | |
675 | ||
676 | return mask; | |
677 | } | |
678 | ||
679 | /** | |
7670df73 | 680 | * ide_find_dma_mode - compute DMA speed |
2d5eaa6d | 681 | * @drive: IDE device |
7670df73 BZ |
682 | * @req_mode: requested mode |
683 | * | |
684 | * Checks the drive/host capabilities and finds the speed to use for | |
685 | * the DMA transfer. The speed is then limited by the requested mode. | |
2d5eaa6d | 686 | * |
7670df73 BZ |
687 | * Returns 0 if the drive/host combination is incapable of DMA transfers |
688 | * or if the requested mode is not a DMA mode. | |
2d5eaa6d BZ |
689 | */ |
690 | ||
7670df73 | 691 | u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode) |
2d5eaa6d BZ |
692 | { |
693 | ide_hwif_t *hwif = drive->hwif; | |
694 | unsigned int mask; | |
695 | int x, i; | |
696 | u8 mode = 0; | |
697 | ||
33c1002e BZ |
698 | if (drive->media != ide_disk) { |
699 | if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA) | |
700 | return 0; | |
701 | } | |
2d5eaa6d BZ |
702 | |
703 | for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) { | |
7670df73 BZ |
704 | if (req_mode < xfer_mode_bases[i]) |
705 | continue; | |
706 | mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); | |
2d5eaa6d BZ |
707 | x = fls(mask) - 1; |
708 | if (x >= 0) { | |
709 | mode = xfer_mode_bases[i] + x; | |
710 | break; | |
711 | } | |
712 | } | |
713 | ||
75d7d963 BZ |
714 | if (hwif->chipset == ide_acorn && mode == 0) { |
715 | /* | |
716 | * is this correct? | |
717 | */ | |
718 | if (ide_dma_good_drive(drive) && drive->id->eide_dma_time < 150) | |
719 | mode = XFER_MW_DMA_1; | |
720 | } | |
721 | ||
3ab7efe8 BZ |
722 | mode = min(mode, req_mode); |
723 | ||
724 | printk(KERN_INFO "%s: %s mode selected\n", drive->name, | |
d34887da | 725 | mode ? ide_xfer_verbose(mode) : "no DMA"); |
2d5eaa6d | 726 | |
3ab7efe8 | 727 | return mode; |
2d5eaa6d BZ |
728 | } |
729 | ||
7670df73 | 730 | EXPORT_SYMBOL_GPL(ide_find_dma_mode); |
2d5eaa6d | 731 | |
0ae2e178 | 732 | static int ide_tune_dma(ide_drive_t *drive) |
29e744d0 | 733 | { |
8704de8f | 734 | ide_hwif_t *hwif = drive->hwif; |
29e744d0 BZ |
735 | u8 speed; |
736 | ||
c223701c | 737 | if (noautodma || drive->nodma || (drive->id->capability & 1) == 0) |
122ab088 BZ |
738 | return 0; |
739 | ||
740 | /* consult the list of known "bad" drives */ | |
741 | if (__ide_dma_bad_drive(drive)) | |
29e744d0 BZ |
742 | return 0; |
743 | ||
3ab7efe8 BZ |
744 | if (ide_id_dma_bug(drive)) |
745 | return 0; | |
746 | ||
8704de8f | 747 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) |
0ae2e178 BZ |
748 | return config_drive_for_dma(drive); |
749 | ||
29e744d0 BZ |
750 | speed = ide_max_dma_mode(drive); |
751 | ||
8704de8f BZ |
752 | if (!speed) { |
753 | /* is this really correct/needed? */ | |
754 | if ((hwif->host_flags & IDE_HFLAG_CY82C693) && | |
755 | ide_dma_good_drive(drive)) | |
756 | return 1; | |
757 | else | |
758 | return 0; | |
759 | } | |
29e744d0 | 760 | |
8704de8f | 761 | if (hwif->host_flags & IDE_HFLAG_NO_SET_MODE) |
88b2b32b BZ |
762 | return 0; |
763 | ||
764 | if (ide_set_dma_mode(drive, speed)) | |
4728d546 | 765 | return 0; |
29e744d0 | 766 | |
4728d546 | 767 | return 1; |
29e744d0 BZ |
768 | } |
769 | ||
0ae2e178 BZ |
770 | static int ide_dma_check(ide_drive_t *drive) |
771 | { | |
772 | ide_hwif_t *hwif = drive->hwif; | |
773 | int vdma = (hwif->host_flags & IDE_HFLAG_VDMA)? 1 : 0; | |
774 | ||
775 | if (!vdma && ide_tune_dma(drive)) | |
776 | return 0; | |
777 | ||
778 | /* TODO: always do PIO fallback */ | |
779 | if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA) | |
780 | return -1; | |
781 | ||
782 | ide_set_max_pio(drive); | |
783 | ||
784 | return vdma ? 0 : -1; | |
785 | } | |
786 | ||
3ab7efe8 | 787 | int ide_id_dma_bug(ide_drive_t *drive) |
1da177e4 | 788 | { |
3ab7efe8 | 789 | struct hd_driveid *id = drive->id; |
1da177e4 LT |
790 | |
791 | if (id->field_valid & 4) { | |
792 | if ((id->dma_ultra >> 8) && (id->dma_mword >> 8)) | |
3ab7efe8 | 793 | goto err_out; |
1da177e4 LT |
794 | } else if (id->field_valid & 2) { |
795 | if ((id->dma_mword >> 8) && (id->dma_1word >> 8)) | |
3ab7efe8 | 796 | goto err_out; |
1da177e4 | 797 | } |
3ab7efe8 BZ |
798 | return 0; |
799 | err_out: | |
800 | printk(KERN_ERR "%s: bad DMA info in identify block\n", drive->name); | |
801 | return 1; | |
1da177e4 LT |
802 | } |
803 | ||
3608b5d7 BZ |
804 | int ide_set_dma(ide_drive_t *drive) |
805 | { | |
3608b5d7 BZ |
806 | int rc; |
807 | ||
7b905994 BZ |
808 | /* |
809 | * Force DMAing for the beginning of the check. | |
810 | * Some chipsets appear to do interesting | |
811 | * things, if not checked and cleared. | |
812 | * PARANOIA!!! | |
813 | */ | |
4a546e04 | 814 | ide_dma_off_quietly(drive); |
3608b5d7 | 815 | |
7b905994 BZ |
816 | rc = ide_dma_check(drive); |
817 | if (rc) | |
818 | return rc; | |
3608b5d7 | 819 | |
4a546e04 BZ |
820 | ide_dma_on(drive); |
821 | ||
822 | return 0; | |
3608b5d7 BZ |
823 | } |
824 | ||
1da177e4 | 825 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
841d2a9b | 826 | void ide_dma_lost_irq (ide_drive_t *drive) |
1da177e4 LT |
827 | { |
828 | printk("%s: DMA interrupt recovery\n", drive->name); | |
1da177e4 LT |
829 | } |
830 | ||
841d2a9b | 831 | EXPORT_SYMBOL(ide_dma_lost_irq); |
1da177e4 | 832 | |
c283f5db | 833 | void ide_dma_timeout (ide_drive_t *drive) |
1da177e4 | 834 | { |
c283f5db SS |
835 | ide_hwif_t *hwif = HWIF(drive); |
836 | ||
1da177e4 | 837 | printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name); |
1da177e4 | 838 | |
c283f5db SS |
839 | if (hwif->ide_dma_test_irq(drive)) |
840 | return; | |
841 | ||
842 | hwif->ide_dma_end(drive); | |
1da177e4 LT |
843 | } |
844 | ||
c283f5db | 845 | EXPORT_SYMBOL(ide_dma_timeout); |
1da177e4 | 846 | |
a02bfd3c | 847 | static void ide_release_dma_engine(ide_hwif_t *hwif) |
1da177e4 LT |
848 | { |
849 | if (hwif->dmatable_cpu) { | |
850 | pci_free_consistent(hwif->pci_dev, | |
851 | PRD_ENTRIES * PRD_BYTES, | |
852 | hwif->dmatable_cpu, | |
853 | hwif->dmatable_dma); | |
854 | hwif->dmatable_cpu = NULL; | |
855 | } | |
1da177e4 LT |
856 | } |
857 | ||
858 | static int ide_release_iomio_dma(ide_hwif_t *hwif) | |
859 | { | |
1da177e4 | 860 | release_region(hwif->dma_base, 8); |
020e322d SS |
861 | if (hwif->extra_ports) |
862 | release_region(hwif->extra_base, hwif->extra_ports); | |
1da177e4 LT |
863 | return 1; |
864 | } | |
865 | ||
866 | /* | |
867 | * Needed for allowing full modular support of ide-driver | |
868 | */ | |
dc844e05 | 869 | int ide_release_dma(ide_hwif_t *hwif) |
1da177e4 | 870 | { |
dc844e05 SS |
871 | ide_release_dma_engine(hwif); |
872 | ||
2ad1e558 | 873 | if (hwif->mmio) |
1da177e4 | 874 | return 1; |
dc844e05 SS |
875 | else |
876 | return ide_release_iomio_dma(hwif); | |
1da177e4 LT |
877 | } |
878 | ||
879 | static int ide_allocate_dma_engine(ide_hwif_t *hwif) | |
880 | { | |
881 | hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev, | |
882 | PRD_ENTRIES * PRD_BYTES, | |
883 | &hwif->dmatable_dma); | |
884 | ||
885 | if (hwif->dmatable_cpu) | |
886 | return 0; | |
887 | ||
dc844e05 SS |
888 | printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n", |
889 | hwif->cds->name); | |
1da177e4 | 890 | |
1da177e4 LT |
891 | return 1; |
892 | } | |
893 | ||
894 | static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
895 | { | |
896 | printk(KERN_INFO " %s: MMIO-DMA ", hwif->name); | |
897 | ||
1da177e4 LT |
898 | return 0; |
899 | } | |
900 | ||
901 | static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
902 | { | |
903 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx", | |
020e322d SS |
904 | hwif->name, base, base + ports - 1); |
905 | ||
1da177e4 LT |
906 | if (!request_region(base, ports, hwif->name)) { |
907 | printk(" -- Error, ports in use.\n"); | |
908 | return 1; | |
909 | } | |
020e322d | 910 | |
020e322d SS |
911 | if (hwif->cds->extra) { |
912 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
913 | ||
914 | if (!hwif->mate || !hwif->mate->extra_ports) { | |
915 | if (!request_region(hwif->extra_base, | |
916 | hwif->cds->extra, hwif->cds->name)) { | |
917 | printk(" -- Error, extra ports in use.\n"); | |
918 | release_region(base, ports); | |
919 | return 1; | |
920 | } | |
921 | hwif->extra_ports = hwif->cds->extra; | |
922 | } | |
1da177e4 | 923 | } |
020e322d | 924 | |
1da177e4 LT |
925 | return 0; |
926 | } | |
927 | ||
928 | static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports) | |
929 | { | |
2ad1e558 | 930 | if (hwif->mmio) |
1da177e4 | 931 | return ide_mapped_mmio_dma(hwif, base,ports); |
2ad1e558 | 932 | |
1da177e4 LT |
933 | return ide_iomio_dma(hwif, base, ports); |
934 | } | |
935 | ||
a02bfd3c | 936 | void ide_setup_dma(ide_hwif_t *hwif, unsigned long base, unsigned num_ports) |
1da177e4 | 937 | { |
a02bfd3c | 938 | if (ide_dma_iobase(hwif, base, num_ports)) |
1da177e4 LT |
939 | return; |
940 | ||
941 | if (ide_allocate_dma_engine(hwif)) { | |
942 | ide_release_dma(hwif); | |
943 | return; | |
944 | } | |
945 | ||
a02bfd3c BZ |
946 | hwif->dma_base = base; |
947 | ||
1da177e4 LT |
948 | if (!(hwif->dma_command)) |
949 | hwif->dma_command = hwif->dma_base; | |
950 | if (!(hwif->dma_vendor1)) | |
951 | hwif->dma_vendor1 = (hwif->dma_base + 1); | |
952 | if (!(hwif->dma_status)) | |
953 | hwif->dma_status = (hwif->dma_base + 2); | |
954 | if (!(hwif->dma_vendor3)) | |
955 | hwif->dma_vendor3 = (hwif->dma_base + 3); | |
956 | if (!(hwif->dma_prdtable)) | |
957 | hwif->dma_prdtable = (hwif->dma_base + 4); | |
958 | ||
15ce926a BZ |
959 | if (!hwif->dma_host_set) |
960 | hwif->dma_host_set = &ide_dma_host_set; | |
1da177e4 LT |
961 | if (!hwif->dma_setup) |
962 | hwif->dma_setup = &ide_dma_setup; | |
963 | if (!hwif->dma_exec_cmd) | |
964 | hwif->dma_exec_cmd = &ide_dma_exec_cmd; | |
965 | if (!hwif->dma_start) | |
966 | hwif->dma_start = &ide_dma_start; | |
967 | if (!hwif->ide_dma_end) | |
968 | hwif->ide_dma_end = &__ide_dma_end; | |
969 | if (!hwif->ide_dma_test_irq) | |
970 | hwif->ide_dma_test_irq = &__ide_dma_test_irq; | |
c283f5db SS |
971 | if (!hwif->dma_timeout) |
972 | hwif->dma_timeout = &ide_dma_timeout; | |
841d2a9b SS |
973 | if (!hwif->dma_lost_irq) |
974 | hwif->dma_lost_irq = &ide_dma_lost_irq; | |
1da177e4 LT |
975 | |
976 | if (hwif->chipset != ide_trm290) { | |
977 | u8 dma_stat = hwif->INB(hwif->dma_status); | |
978 | printk(", BIOS settings: %s:%s, %s:%s", | |
979 | hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio", | |
980 | hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio"); | |
981 | } | |
982 | printk("\n"); | |
1da177e4 LT |
983 | } |
984 | ||
985 | EXPORT_SYMBOL_GPL(ide_setup_dma); | |
986 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |