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99eeed47 MH |
1 | /* |
2 | * File: drivers/video/bfin-t350mcqb-fb.c | |
3 | * Based on: | |
4 | * Author: Michael Hennerich <hennerich@blackfin.uclinux.org> | |
5 | * | |
6 | * Created: | |
7 | * Description: Blackfin LCD Framebufer driver | |
8 | * | |
9 | * | |
10 | * Modified: | |
11 | * Copyright 2004-2007 Analog Devices Inc. | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | */ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/fb.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/types.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/device.h> | |
40 | #include <linux/backlight.h> | |
41 | #include <linux/lcd.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | #include <linux/platform_device.h> | |
44 | ||
45 | #include <asm/blackfin.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/dma-mapping.h> | |
48 | #include <asm/dma.h> | |
49 | #include <asm/portmux.h> | |
50 | #include <asm/gptimers.h> | |
51 | ||
52 | #define NO_BL_SUPPORT | |
53 | ||
54 | #define LCD_X_RES 320 /* Horizontal Resolution */ | |
55 | #define LCD_Y_RES 240 /* Vertical Resolution */ | |
56 | #define LCD_BPP 24 /* Bit Per Pixel */ | |
57 | ||
58 | #define DMA_BUS_SIZE 16 | |
59 | #define LCD_CLK (12*1000*1000) /* 12MHz */ | |
60 | ||
61 | #define CLOCKS_PER_PIX 3 | |
62 | ||
63 | /* | |
64 | * HS and VS timing parameters (all in number of PPI clk ticks) | |
65 | */ | |
66 | ||
67 | #define U_LINE 1 /* Blanking Lines */ | |
68 | ||
69 | #define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */ | |
70 | #define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */ | |
71 | #define H_PULSE 90 /* HS pulse width */ | |
72 | #define H_START 204 /* first valid pixel */ | |
73 | ||
74 | #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ | |
75 | #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */ | |
76 | #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ | |
77 | ||
78 | #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX) | |
79 | ||
80 | #define BFIN_LCD_NBR_PALETTE_ENTRIES 256 | |
81 | ||
82 | #define DRIVER_NAME "bfin-t350mcqb" | |
83 | static char driver_name[] = DRIVER_NAME; | |
84 | ||
85 | struct bfin_t350mcqbfb_info { | |
86 | struct fb_info *fb; | |
87 | struct device *dev; | |
88 | unsigned char *fb_buffer; /* RGB Buffer */ | |
89 | dma_addr_t dma_handle; | |
90 | int lq043_mmap; | |
91 | int lq043_open_cnt; | |
92 | int irq; | |
93 | spinlock_t lock; /* lock */ | |
7ef9861c | 94 | u32 pseudo_pal[16]; |
99eeed47 MH |
95 | }; |
96 | ||
97 | static int nocursor; | |
98 | module_param(nocursor, int, 0644); | |
99 | MODULE_PARM_DESC(nocursor, "cursor enable/disable"); | |
100 | ||
101 | #define PPI_TX_MODE 0x2 | |
102 | #define PPI_XFER_TYPE_11 0xC | |
103 | #define PPI_PORT_CFG_01 0x10 | |
104 | #define PPI_PACK_EN 0x80 | |
105 | #define PPI_POLS_1 0x8000 | |
106 | ||
107 | static void bfin_t350mcqb_config_ppi(struct bfin_t350mcqbfb_info *fbi) | |
108 | { | |
109 | bfin_write_PPI_DELAY(H_START); | |
110 | bfin_write_PPI_COUNT(H_ACTPIX-1); | |
111 | bfin_write_PPI_FRAME(V_LINES); | |
112 | ||
113 | bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */ | |
114 | PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ | |
115 | PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ | |
116 | PPI_PACK_EN | /* packing enabled PACK_EN */ | |
117 | PPI_POLS_1); /* faling edge syncs POLS */ | |
118 | } | |
119 | ||
120 | static inline void bfin_t350mcqb_disable_ppi(void) | |
121 | { | |
122 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); | |
123 | } | |
124 | ||
125 | static inline void bfin_t350mcqb_enable_ppi(void) | |
126 | { | |
127 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); | |
128 | } | |
129 | ||
130 | static void bfin_t350mcqb_start_timers(void) | |
131 | { | |
132 | unsigned long flags; | |
133 | ||
134 | local_irq_save(flags); | |
135 | enable_gptimers(TIMER1bit); | |
136 | enable_gptimers(TIMER0bit); | |
137 | local_irq_restore(flags); | |
138 | } | |
139 | ||
140 | static void bfin_t350mcqb_stop_timers(void) | |
141 | { | |
142 | disable_gptimers(TIMER0bit | TIMER1bit); | |
143 | ||
144 | set_gptimer_status(0, TIMER_STATUS_TRUN0 | TIMER_STATUS_TRUN1 | | |
145 | TIMER_STATUS_TIMIL0 | TIMER_STATUS_TIMIL1 | | |
146 | TIMER_STATUS_TOVF0 | TIMER_STATUS_TOVF1); | |
147 | ||
148 | } | |
149 | ||
150 | static void bfin_t350mcqb_init_timers(void) | |
151 | { | |
152 | ||
153 | bfin_t350mcqb_stop_timers(); | |
154 | ||
155 | set_gptimer_period(TIMER0_id, H_PERIOD); | |
156 | set_gptimer_pwidth(TIMER0_id, H_PULSE); | |
157 | set_gptimer_config(TIMER0_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | | |
158 | TIMER_TIN_SEL | TIMER_CLK_SEL| | |
159 | TIMER_EMU_RUN); | |
160 | ||
161 | set_gptimer_period(TIMER1_id, V_PERIOD); | |
162 | set_gptimer_pwidth(TIMER1_id, V_PULSE); | |
163 | set_gptimer_config(TIMER1_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | | |
164 | TIMER_TIN_SEL | TIMER_CLK_SEL | | |
165 | TIMER_EMU_RUN); | |
166 | ||
167 | } | |
168 | ||
169 | static void bfin_t350mcqb_config_dma(struct bfin_t350mcqbfb_info *fbi) | |
170 | { | |
171 | ||
172 | set_dma_config(CH_PPI, | |
173 | set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, | |
174 | INTR_DISABLE, DIMENSION_2D, | |
175 | DATA_SIZE_16, | |
176 | DMA_NOSYNC_KEEP_DMA_BUF)); | |
177 | set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); | |
178 | set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8); | |
179 | set_dma_y_count(CH_PPI, V_LINES); | |
180 | ||
181 | set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8); | |
182 | set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer); | |
183 | ||
184 | } | |
185 | ||
7ef9861c | 186 | static u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, |
99eeed47 MH |
187 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, |
188 | P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, | |
189 | P_PPI0_D6, P_PPI0_D7, 0}; | |
190 | ||
7ef9861c BW |
191 | static int bfin_t350mcqb_request_ports(int action) |
192 | { | |
99eeed47 MH |
193 | if (action) { |
194 | if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) { | |
195 | printk(KERN_ERR "Requesting Peripherals faild\n"); | |
196 | return -EFAULT; | |
197 | } | |
198 | } else | |
199 | peripheral_free_list(ppi0_req_8); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static int bfin_t350mcqb_fb_open(struct fb_info *info, int user) | |
205 | { | |
206 | struct bfin_t350mcqbfb_info *fbi = info->par; | |
207 | ||
208 | spin_lock(&fbi->lock); | |
209 | fbi->lq043_open_cnt++; | |
210 | ||
211 | if (fbi->lq043_open_cnt <= 1) { | |
212 | ||
213 | bfin_t350mcqb_disable_ppi(); | |
214 | SSYNC(); | |
215 | ||
216 | bfin_t350mcqb_config_dma(fbi); | |
217 | bfin_t350mcqb_config_ppi(fbi); | |
218 | bfin_t350mcqb_init_timers(); | |
219 | ||
220 | /* start dma */ | |
221 | enable_dma(CH_PPI); | |
222 | bfin_t350mcqb_enable_ppi(); | |
223 | bfin_t350mcqb_start_timers(); | |
224 | } | |
225 | ||
226 | spin_unlock(&fbi->lock); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int bfin_t350mcqb_fb_release(struct fb_info *info, int user) | |
232 | { | |
233 | struct bfin_t350mcqbfb_info *fbi = info->par; | |
234 | ||
235 | spin_lock(&fbi->lock); | |
236 | ||
237 | fbi->lq043_open_cnt--; | |
238 | fbi->lq043_mmap = 0; | |
239 | ||
240 | if (fbi->lq043_open_cnt <= 0) { | |
241 | bfin_t350mcqb_disable_ppi(); | |
242 | SSYNC(); | |
243 | disable_dma(CH_PPI); | |
244 | bfin_t350mcqb_stop_timers(); | |
245 | memset(fbi->fb_buffer, 0, info->fix.smem_len); | |
246 | } | |
247 | ||
248 | spin_unlock(&fbi->lock); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
253 | static int bfin_t350mcqb_fb_check_var(struct fb_var_screeninfo *var, | |
254 | struct fb_info *info) | |
255 | { | |
256 | ||
257 | if (var->bits_per_pixel != LCD_BPP) { | |
258 | pr_debug("%s: depth not supported: %u BPP\n", __FUNCTION__, | |
259 | var->bits_per_pixel); | |
260 | return -EINVAL; | |
261 | } | |
262 | ||
263 | if (info->var.xres != var->xres || info->var.yres != var->yres || | |
264 | info->var.xres_virtual != var->xres_virtual || | |
265 | info->var.yres_virtual != var->yres_virtual) { | |
266 | pr_debug("%s: Resolution not supported: X%u x Y%u \n", | |
267 | __FUNCTION__, var->xres, var->yres); | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | /* | |
272 | * Memory limit | |
273 | */ | |
274 | ||
275 | if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { | |
276 | pr_debug("%s: Memory Limit requested yres_virtual = %u\n", | |
277 | __FUNCTION__, var->yres_virtual); | |
278 | return -ENOMEM; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | static int bfin_t350mcqb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) | |
285 | { | |
286 | struct bfin_t350mcqbfb_info *fbi = info->par; | |
287 | ||
288 | if (fbi->lq043_mmap) | |
289 | return -1; | |
290 | ||
291 | spin_lock(&fbi->lock); | |
292 | fbi->lq043_mmap = 1; | |
293 | spin_unlock(&fbi->lock); | |
294 | ||
295 | vma->vm_start = (unsigned long)(fbi->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET); | |
296 | ||
297 | vma->vm_end = vma->vm_start + info->fix.smem_len; | |
298 | /* For those who don't understand how mmap works, go read | |
299 | * Documentation/nommu-mmap.txt. | |
300 | * For those that do, you will know that the VM_MAYSHARE flag | |
301 | * must be set in the vma->vm_flags structure on noMMU | |
302 | * Other flags can be set, and are documented in | |
303 | * include/linux/mm.h | |
304 | */ | |
363df399 | 305 | vma->vm_flags |= VM_MAYSHARE | VM_SHARED; |
99eeed47 MH |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | int bfin_t350mcqb_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
311 | { | |
312 | if (nocursor) | |
313 | return 0; | |
314 | else | |
315 | return -EINVAL; /* just to force soft_cursor() call */ | |
316 | } | |
317 | ||
318 | static int bfin_t350mcqb_fb_setcolreg(u_int regno, u_int red, u_int green, | |
319 | u_int blue, u_int transp, | |
320 | struct fb_info *info) | |
321 | { | |
322 | if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) | |
323 | return -EINVAL; | |
324 | ||
325 | if (info->var.grayscale) { | |
326 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
327 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | |
328 | } | |
329 | ||
330 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
331 | ||
332 | u32 value; | |
333 | /* Place color in the pseudopalette */ | |
334 | if (regno > 16) | |
335 | return -EINVAL; | |
336 | ||
337 | red >>= (16 - info->var.red.length); | |
338 | green >>= (16 - info->var.green.length); | |
339 | blue >>= (16 - info->var.blue.length); | |
340 | ||
341 | value = (red << info->var.red.offset) | | |
342 | (green << info->var.green.offset) | | |
343 | (blue << info->var.blue.offset); | |
344 | value &= 0xFFFFFF; | |
345 | ||
346 | ((u32 *) (info->pseudo_palette))[regno] = value; | |
347 | ||
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static struct fb_ops bfin_t350mcqb_fb_ops = { | |
354 | .owner = THIS_MODULE, | |
355 | .fb_open = bfin_t350mcqb_fb_open, | |
356 | .fb_release = bfin_t350mcqb_fb_release, | |
357 | .fb_check_var = bfin_t350mcqb_fb_check_var, | |
358 | .fb_fillrect = cfb_fillrect, | |
359 | .fb_copyarea = cfb_copyarea, | |
360 | .fb_imageblit = cfb_imageblit, | |
361 | .fb_mmap = bfin_t350mcqb_fb_mmap, | |
362 | .fb_cursor = bfin_t350mcqb_fb_cursor, | |
363 | .fb_setcolreg = bfin_t350mcqb_fb_setcolreg, | |
364 | }; | |
365 | ||
366 | #ifndef NO_BL_SUPPORT | |
367 | static int bl_get_brightness(struct backlight_device *bd) | |
368 | { | |
369 | return 0; | |
370 | } | |
371 | ||
372 | static struct backlight_ops bfin_lq043fb_bl_ops = { | |
373 | .get_brightness = bl_get_brightness, | |
374 | }; | |
375 | ||
376 | static struct backlight_device *bl_dev; | |
377 | ||
378 | static int bfin_lcd_get_power(struct lcd_device *dev) | |
379 | { | |
380 | return 0; | |
381 | } | |
382 | ||
383 | static int bfin_lcd_set_power(struct lcd_device *dev, int power) | |
384 | { | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static int bfin_lcd_get_contrast(struct lcd_device *dev) | |
389 | { | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast) | |
394 | { | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static int bfin_lcd_check_fb(struct fb_info *fi) | |
400 | { | |
401 | if (!fi || (fi == &bfin_t350mcqb_fb)) | |
402 | return 1; | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static struct lcd_ops bfin_lcd_ops = { | |
407 | .get_power = bfin_lcd_get_power, | |
408 | .set_power = bfin_lcd_set_power, | |
409 | .get_contrast = bfin_lcd_get_contrast, | |
410 | .set_contrast = bfin_lcd_set_contrast, | |
411 | .check_fb = bfin_lcd_check_fb, | |
412 | }; | |
413 | ||
414 | static struct lcd_device *lcd_dev; | |
415 | #endif | |
416 | ||
417 | static irqreturn_t bfin_t350mcqb_irq_error(int irq, void *dev_id) | |
418 | { | |
419 | /*struct bfin_t350mcqbfb_info *info = (struct bfin_t350mcqbfb_info *)dev_id;*/ | |
420 | ||
421 | u16 status = bfin_read_PPI_STATUS(); | |
422 | bfin_write_PPI_STATUS(0xFFFF); | |
423 | ||
424 | if (status) { | |
425 | bfin_t350mcqb_disable_ppi(); | |
426 | disable_dma(CH_PPI); | |
427 | ||
428 | /* start dma */ | |
429 | enable_dma(CH_PPI); | |
430 | bfin_t350mcqb_enable_ppi(); | |
431 | bfin_write_PPI_STATUS(0xFFFF); | |
432 | } | |
433 | ||
434 | return IRQ_HANDLED; | |
435 | } | |
436 | ||
437 | static int __init bfin_t350mcqb_probe(struct platform_device *pdev) | |
438 | { | |
439 | struct bfin_t350mcqbfb_info *info; | |
440 | struct fb_info *fbinfo; | |
441 | int ret; | |
442 | ||
443 | printk(KERN_INFO DRIVER_NAME ": %dx%d %d-bit RGB FrameBuffer initializing...\n", | |
444 | LCD_X_RES, LCD_Y_RES, LCD_BPP); | |
445 | ||
446 | if (request_dma(CH_PPI, "CH_PPI") < 0) { | |
447 | printk(KERN_ERR DRIVER_NAME | |
448 | ": couldn't request CH_PPI DMA\n"); | |
449 | ret = -EFAULT; | |
450 | goto out1; | |
451 | } | |
452 | ||
453 | fbinfo = | |
454 | framebuffer_alloc(sizeof(struct bfin_t350mcqbfb_info), &pdev->dev); | |
455 | if (!fbinfo) { | |
456 | ret = -ENOMEM; | |
457 | goto out2; | |
458 | } | |
459 | ||
460 | info = fbinfo->par; | |
461 | info->fb = fbinfo; | |
462 | info->dev = &pdev->dev; | |
463 | ||
464 | platform_set_drvdata(pdev, fbinfo); | |
465 | ||
466 | strcpy(fbinfo->fix.id, driver_name); | |
467 | ||
468 | fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; | |
469 | fbinfo->fix.type_aux = 0; | |
470 | fbinfo->fix.xpanstep = 0; | |
471 | fbinfo->fix.ypanstep = 0; | |
472 | fbinfo->fix.ywrapstep = 0; | |
473 | fbinfo->fix.accel = FB_ACCEL_NONE; | |
474 | fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; | |
475 | ||
476 | fbinfo->var.nonstd = 0; | |
477 | fbinfo->var.activate = FB_ACTIVATE_NOW; | |
478 | fbinfo->var.height = -1; | |
479 | fbinfo->var.width = -1; | |
480 | fbinfo->var.accel_flags = 0; | |
481 | fbinfo->var.vmode = FB_VMODE_NONINTERLACED; | |
482 | ||
483 | fbinfo->var.xres = LCD_X_RES; | |
484 | fbinfo->var.xres_virtual = LCD_X_RES; | |
485 | fbinfo->var.yres = LCD_Y_RES; | |
486 | fbinfo->var.yres_virtual = LCD_Y_RES; | |
487 | fbinfo->var.bits_per_pixel = LCD_BPP; | |
488 | ||
489 | fbinfo->var.red.offset = 0; | |
490 | fbinfo->var.green.offset = 8; | |
491 | fbinfo->var.blue.offset = 16; | |
492 | fbinfo->var.transp.offset = 0; | |
493 | fbinfo->var.red.length = 8; | |
494 | fbinfo->var.green.length = 8; | |
495 | fbinfo->var.blue.length = 8; | |
496 | fbinfo->var.transp.length = 0; | |
497 | fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8; | |
498 | ||
499 | fbinfo->fix.line_length = fbinfo->var.xres_virtual * | |
500 | fbinfo->var.bits_per_pixel / 8; | |
501 | ||
502 | ||
503 | fbinfo->fbops = &bfin_t350mcqb_fb_ops; | |
504 | fbinfo->flags = FBINFO_FLAG_DEFAULT; | |
505 | ||
506 | info->fb_buffer = | |
507 | dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle, | |
508 | GFP_KERNEL); | |
509 | ||
510 | if (NULL == info->fb_buffer) { | |
511 | printk(KERN_ERR DRIVER_NAME | |
512 | ": couldn't allocate dma buffer.\n"); | |
513 | ret = -ENOMEM; | |
514 | goto out3; | |
515 | } | |
516 | ||
517 | memset(info->fb_buffer, 0, fbinfo->fix.smem_len); | |
518 | ||
519 | fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET; | |
520 | fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET; | |
521 | ||
522 | fbinfo->fbops = &bfin_t350mcqb_fb_ops; | |
523 | ||
7ef9861c | 524 | fbinfo->pseudo_palette = &info->pseudo_pal; |
99eeed47 MH |
525 | |
526 | if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) | |
527 | < 0) { | |
528 | printk(KERN_ERR DRIVER_NAME | |
529 | "Fail to allocate colormap (%d entries)\n", | |
530 | BFIN_LCD_NBR_PALETTE_ENTRIES); | |
531 | ret = -EFAULT; | |
7ef9861c | 532 | goto out4; |
99eeed47 MH |
533 | } |
534 | ||
535 | if (bfin_t350mcqb_request_ports(1)) { | |
536 | printk(KERN_ERR DRIVER_NAME ": couldn't request gpio port.\n"); | |
537 | ret = -EFAULT; | |
538 | goto out6; | |
539 | } | |
540 | ||
541 | info->irq = platform_get_irq(pdev, 0); | |
542 | if (info->irq < 0) { | |
543 | ret = -EINVAL; | |
544 | goto out7; | |
545 | } | |
546 | ||
7ef9861c BW |
547 | ret = request_irq(info->irq, bfin_t350mcqb_irq_error, IRQF_DISABLED, |
548 | "PPI ERROR", info); | |
549 | if (ret < 0) { | |
99eeed47 MH |
550 | printk(KERN_ERR DRIVER_NAME |
551 | ": unable to request PPI ERROR IRQ\n"); | |
99eeed47 MH |
552 | goto out7; |
553 | } | |
554 | ||
555 | if (register_framebuffer(fbinfo) < 0) { | |
556 | printk(KERN_ERR DRIVER_NAME | |
557 | ": unable to register framebuffer.\n"); | |
558 | ret = -EINVAL; | |
559 | goto out8; | |
560 | } | |
561 | #ifndef NO_BL_SUPPORT | |
562 | bl_dev = | |
563 | backlight_device_register("bf52x-bl", NULL, NULL, | |
564 | &bfin_lq043fb_bl_ops); | |
565 | bl_dev->props.max_brightness = 255; | |
566 | ||
567 | lcd_dev = lcd_device_register(DRIVER_NAME, NULL, &bfin_lcd_ops); | |
568 | lcd_dev->props.max_contrast = 255, printk(KERN_INFO "Done.\n"); | |
569 | #endif | |
570 | ||
571 | return 0; | |
572 | ||
573 | out8: | |
574 | free_irq(info->irq, info); | |
575 | out7: | |
576 | bfin_t350mcqb_request_ports(0); | |
577 | out6: | |
578 | fb_dealloc_cmap(&fbinfo->cmap); | |
99eeed47 MH |
579 | out4: |
580 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, | |
581 | info->dma_handle); | |
582 | out3: | |
583 | framebuffer_release(fbinfo); | |
584 | out2: | |
585 | free_dma(CH_PPI); | |
586 | out1: | |
587 | platform_set_drvdata(pdev, NULL); | |
588 | ||
589 | return ret; | |
590 | } | |
591 | ||
592 | static int bfin_t350mcqb_remove(struct platform_device *pdev) | |
593 | { | |
594 | ||
595 | struct fb_info *fbinfo = platform_get_drvdata(pdev); | |
596 | struct bfin_t350mcqbfb_info *info = fbinfo->par; | |
597 | ||
7ef9861c BW |
598 | unregister_framebuffer(fbinfo); |
599 | ||
99eeed47 MH |
600 | free_dma(CH_PPI); |
601 | free_irq(info->irq, info); | |
602 | ||
603 | if (info->fb_buffer != NULL) | |
604 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, | |
605 | info->dma_handle); | |
606 | ||
99eeed47 MH |
607 | fb_dealloc_cmap(&fbinfo->cmap); |
608 | ||
609 | #ifndef NO_BL_SUPPORT | |
610 | lcd_device_unregister(lcd_dev); | |
611 | backlight_device_unregister(bl_dev); | |
612 | #endif | |
613 | ||
99eeed47 MH |
614 | bfin_t350mcqb_request_ports(0); |
615 | ||
7ef9861c BW |
616 | platform_set_drvdata(pdev, NULL); |
617 | framebuffer_release(fbinfo); | |
618 | ||
99eeed47 MH |
619 | printk(KERN_INFO DRIVER_NAME ": Unregister LCD driver.\n"); |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | #ifdef CONFIG_PM | |
625 | static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t state) | |
626 | { | |
627 | struct fb_info *fbinfo = platform_get_drvdata(pdev); | |
628 | struct bfin_t350mcqbfb_info *info = fbinfo->par; | |
629 | ||
630 | bfin_t350mcqb_disable_ppi(); | |
631 | disable_dma(CH_PPI); | |
632 | bfin_write_PPI_STATUS(0xFFFF); | |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | static int bfin_t350mcqb_resume(struct platform_device *pdev) | |
638 | { | |
639 | struct fb_info *fbinfo = platform_get_drvdata(pdev); | |
640 | struct bfin_t350mcqbfb_info *info = fbinfo->par; | |
641 | ||
642 | enable_dma(CH_PPI); | |
643 | bfin_t350mcqb_enable_ppi(); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | #else | |
648 | #define bfin_t350mcqb_suspend NULL | |
649 | #define bfin_t350mcqb_resume NULL | |
650 | #endif | |
651 | ||
652 | static struct platform_driver bfin_t350mcqb_driver = { | |
653 | .probe = bfin_t350mcqb_probe, | |
654 | .remove = bfin_t350mcqb_remove, | |
655 | .suspend = bfin_t350mcqb_suspend, | |
656 | .resume = bfin_t350mcqb_resume, | |
657 | .driver = { | |
658 | .name = DRIVER_NAME, | |
659 | .owner = THIS_MODULE, | |
660 | }, | |
661 | }; | |
662 | ||
663 | static int __devinit bfin_t350mcqb_driver_init(void) | |
664 | { | |
665 | return platform_driver_register(&bfin_t350mcqb_driver); | |
666 | } | |
667 | ||
668 | static void __exit bfin_t350mcqb_driver_cleanup(void) | |
669 | { | |
670 | platform_driver_unregister(&bfin_t350mcqb_driver); | |
671 | } | |
672 | ||
673 | MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); | |
674 | MODULE_LICENSE("GPL"); | |
675 | ||
676 | module_init(bfin_t350mcqb_driver_init); | |
677 | module_exit(bfin_t350mcqb_driver_cleanup); |