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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare 802.3an compliant PHY | |
3 | * Copyright 2007 Solarflare Communications Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
11 | #include <linux/seq_file.h> | |
12 | #include "efx.h" | |
13 | #include "gmii.h" | |
14 | #include "mdio_10g.h" | |
15 | #include "falcon.h" | |
16 | #include "phy.h" | |
17 | #include "falcon_hwdefs.h" | |
18 | #include "boards.h" | |
19 | #include "mac.h" | |
20 | ||
21 | /* We expect these MMDs to be in the package */ | |
22 | /* AN not here as mdio_check_mmds() requires STAT2 support */ | |
23 | #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \ | |
24 | MDIO_MMDREG_DEVS0_PCS | \ | |
25 | MDIO_MMDREG_DEVS0_PHYXS) | |
26 | ||
3273c2e8 BH |
27 | #define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
28 | (1 << LOOPBACK_PCS) | \ | |
29 | (1 << LOOPBACK_PMAPMD) | \ | |
30 | (1 << LOOPBACK_NETWORK)) | |
31 | ||
8ceee660 BH |
32 | /* We complain if we fail to see the link partner as 10G capable this many |
33 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
34 | */ | |
35 | #define MAX_BAD_LP_TRIES (5) | |
36 | ||
37 | /* Extended control register */ | |
38 | #define PMA_PMD_XCONTROL_REG 0xc000 | |
39 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 | |
40 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
41 | ||
42 | /* extended status register */ | |
43 | #define PMA_PMD_XSTATUS_REG 0xc001 | |
44 | #define PMA_PMD_XSTAT_FLP_LBN (12) | |
45 | ||
46 | /* LED control register */ | |
47 | #define PMA_PMD_LED_CTRL_REG (0xc007) | |
48 | #define PMA_PMA_LED_ACTIVITY_LBN (3) | |
49 | ||
50 | /* LED function override register */ | |
51 | #define PMA_PMD_LED_OVERR_REG (0xc009) | |
52 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ | |
53 | #define PMA_PMD_LED_LINK_LBN (0) | |
54 | #define PMA_PMD_LED_SPEED_LBN (2) | |
55 | #define PMA_PMD_LED_TX_LBN (4) | |
56 | #define PMA_PMD_LED_RX_LBN (6) | |
57 | /* Override settings */ | |
58 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
59 | #define PMA_PMD_LED_ON (1) | |
60 | #define PMA_PMD_LED_OFF (2) | |
61 | #define PMA_PMD_LED_FLASH (3) | |
62 | /* All LEDs under hardware control */ | |
63 | #define PMA_PMD_LED_FULL_AUTO (0) | |
64 | /* Green and Amber under hardware control, Red off */ | |
65 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | |
66 | ||
67 | ||
68 | /* Self test (BIST) control register */ | |
69 | #define PMA_PMD_BIST_CTRL_REG (0xc014) | |
70 | #define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */ | |
71 | #define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */ | |
72 | #define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */ | |
73 | /* Self test status register */ | |
74 | #define PMA_PMD_BIST_STAT_REG (0xc015) | |
75 | #define PMA_PMD_BIST_ENX_LBN (3) | |
76 | #define PMA_PMD_BIST_PMA_LBN (2) | |
77 | #define PMA_PMD_BIST_RXD_LBN (1) | |
78 | #define PMA_PMD_BIST_AFE_LBN (0) | |
79 | ||
3273c2e8 BH |
80 | /* Special Software reset register */ |
81 | #define PMA_PMD_EXT_CTRL_REG 49152 | |
82 | #define PMA_PMD_EXT_SSR_LBN 15 | |
83 | ||
8ceee660 BH |
84 | #define BIST_MAX_DELAY (1000) |
85 | #define BIST_POLL_DELAY (10) | |
86 | ||
87 | /* Misc register defines */ | |
88 | #define PCS_CLOCK_CTRL_REG 0xd801 | |
89 | #define PLL312_RST_N_LBN 2 | |
90 | ||
91 | #define PCS_SOFT_RST2_REG 0xd806 | |
92 | #define SERDES_RST_N_LBN 13 | |
93 | #define XGXS_RST_N_LBN 12 | |
94 | ||
95 | #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */ | |
96 | #define CLK312_EN_LBN 3 | |
97 | ||
3273c2e8 BH |
98 | /* PHYXS registers */ |
99 | #define PHYXS_TEST1 (49162) | |
100 | #define LOOPBACK_NEAR_LBN (8) | |
101 | #define LOOPBACK_NEAR_WIDTH (1) | |
102 | ||
8ceee660 BH |
103 | /* Boot status register */ |
104 | #define PCS_BOOT_STATUS_REG (0xd000) | |
105 | #define PCS_BOOT_FATAL_ERR_LBN (0) | |
106 | #define PCS_BOOT_PROGRESS_LBN (1) | |
107 | #define PCS_BOOT_PROGRESS_WIDTH (2) | |
108 | #define PCS_BOOT_COMPLETE_LBN (3) | |
109 | #define PCS_BOOT_MAX_DELAY (100) | |
110 | #define PCS_BOOT_POLL_DELAY (10) | |
111 | ||
112 | /* Time to wait between powering down the LNPGA and turning off the power | |
113 | * rails */ | |
114 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
115 | ||
116 | static int crc_error_reset_threshold = 100; | |
117 | module_param(crc_error_reset_threshold, int, 0644); | |
118 | MODULE_PARM_DESC(crc_error_reset_threshold, | |
119 | "Max number of CRC errors before XAUI reset"); | |
120 | ||
121 | struct tenxpress_phy_data { | |
122 | enum tenxpress_state state; | |
3273c2e8 | 123 | enum efx_loopback_mode loopback_mode; |
8ceee660 | 124 | atomic_t bad_crc_count; |
3273c2e8 | 125 | int tx_disabled; |
8ceee660 BH |
126 | int bad_lp_tries; |
127 | }; | |
128 | ||
129 | static int tenxpress_state_is(struct efx_nic *efx, int state) | |
130 | { | |
131 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
132 | return (phy_data != NULL) && (state == phy_data->state); | |
133 | } | |
134 | ||
135 | void tenxpress_set_state(struct efx_nic *efx, | |
136 | enum tenxpress_state state) | |
137 | { | |
138 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
139 | if (phy_data != NULL) | |
140 | phy_data->state = state; | |
141 | } | |
142 | ||
143 | void tenxpress_crc_err(struct efx_nic *efx) | |
144 | { | |
145 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
146 | if (phy_data != NULL) | |
147 | atomic_inc(&phy_data->bad_crc_count); | |
148 | } | |
149 | ||
150 | /* Check that the C166 has booted successfully */ | |
151 | static int tenxpress_phy_check(struct efx_nic *efx) | |
152 | { | |
153 | int phy_id = efx->mii.phy_id; | |
154 | int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY; | |
155 | int boot_stat; | |
156 | ||
157 | /* Wait for the boot to complete (or not) */ | |
158 | while (count) { | |
159 | boot_stat = mdio_clause45_read(efx, phy_id, | |
160 | MDIO_MMD_PCS, | |
161 | PCS_BOOT_STATUS_REG); | |
162 | if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN)) | |
163 | break; | |
164 | count--; | |
165 | udelay(PCS_BOOT_POLL_DELAY); | |
166 | } | |
167 | ||
168 | if (!count) { | |
169 | EFX_ERR(efx, "%s: PHY boot timed out. Last status " | |
170 | "%x\n", __func__, | |
171 | (boot_stat >> PCS_BOOT_PROGRESS_LBN) & | |
172 | ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1)); | |
173 | return -ETIMEDOUT; | |
174 | } | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static void tenxpress_reset_xaui(struct efx_nic *efx); | |
180 | ||
181 | static int tenxpress_init(struct efx_nic *efx) | |
182 | { | |
183 | int rc, reg; | |
184 | ||
185 | /* Turn on the clock */ | |
186 | reg = (1 << CLK312_EN_LBN); | |
187 | mdio_clause45_write(efx, efx->mii.phy_id, | |
188 | MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg); | |
189 | ||
190 | rc = tenxpress_phy_check(efx); | |
191 | if (rc < 0) | |
192 | return rc; | |
193 | ||
194 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ | |
195 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
196 | MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG); | |
197 | reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN); | |
198 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
199 | PMA_PMD_LED_CTRL_REG, reg); | |
200 | ||
201 | reg = PMA_PMD_LED_DEFAULT; | |
202 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
203 | PMA_PMD_LED_OVERR_REG, reg); | |
204 | ||
205 | return rc; | |
206 | } | |
207 | ||
208 | static int tenxpress_phy_init(struct efx_nic *efx) | |
209 | { | |
210 | struct tenxpress_phy_data *phy_data; | |
211 | int rc = 0; | |
212 | ||
213 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
9b7bfc4c BH |
214 | if (!phy_data) |
215 | return -ENOMEM; | |
8ceee660 BH |
216 | efx->phy_data = phy_data; |
217 | ||
218 | tenxpress_set_state(efx, TENXPRESS_STATUS_NORMAL); | |
219 | ||
75f2d3ea BH |
220 | if (!sfe4001_phy_flash_cfg) { |
221 | rc = mdio_clause45_wait_reset_mmds(efx, | |
222 | TENXPRESS_REQUIRED_DEVS); | |
223 | if (rc < 0) | |
224 | goto fail; | |
225 | } | |
8ceee660 BH |
226 | |
227 | rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); | |
228 | if (rc < 0) | |
229 | goto fail; | |
230 | ||
231 | rc = tenxpress_init(efx); | |
232 | if (rc < 0) | |
233 | goto fail; | |
234 | ||
235 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ | |
236 | ||
237 | /* Let XGXS and SerDes out of reset and resets 10XPress */ | |
238 | falcon_reset_xaui(efx); | |
239 | ||
240 | return 0; | |
241 | ||
242 | fail: | |
243 | kfree(efx->phy_data); | |
244 | efx->phy_data = NULL; | |
245 | return rc; | |
246 | } | |
247 | ||
3273c2e8 BH |
248 | static int tenxpress_special_reset(struct efx_nic *efx) |
249 | { | |
250 | int rc, reg; | |
251 | ||
252 | EFX_TRACE(efx, "%s\n", __func__); | |
253 | ||
254 | /* Initiate reset */ | |
255 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
256 | MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG); | |
257 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | |
258 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
259 | PMA_PMD_EXT_CTRL_REG, reg); | |
260 | ||
261 | msleep(200); | |
262 | ||
263 | /* Wait for the blocks to come out of reset */ | |
264 | rc = mdio_clause45_wait_reset_mmds(efx, | |
265 | TENXPRESS_REQUIRED_DEVS); | |
266 | if (rc < 0) | |
267 | return rc; | |
268 | ||
269 | /* Try and reconfigure the device */ | |
270 | rc = tenxpress_init(efx); | |
271 | if (rc < 0) | |
272 | return rc; | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
8ceee660 BH |
277 | static void tenxpress_set_bad_lp(struct efx_nic *efx, int bad_lp) |
278 | { | |
279 | struct tenxpress_phy_data *pd = efx->phy_data; | |
280 | int reg; | |
281 | ||
282 | /* Nothing to do if all is well and was previously so. */ | |
283 | if (!(bad_lp || pd->bad_lp_tries)) | |
284 | return; | |
285 | ||
286 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
287 | MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG); | |
288 | ||
289 | if (bad_lp) | |
290 | pd->bad_lp_tries++; | |
291 | else | |
292 | pd->bad_lp_tries = 0; | |
293 | ||
294 | if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
295 | pd->bad_lp_tries = 0; /* Restart count */ | |
296 | reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN); | |
297 | reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN); | |
298 | EFX_ERR(efx, "This NIC appears to be plugged into" | |
299 | " a port that is not 10GBASE-T capable.\n" | |
300 | " This PHY is 10GBASE-T ONLY, so no link can" | |
301 | " be established.\n"); | |
302 | } else { | |
303 | reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN); | |
304 | } | |
305 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
306 | PMA_PMD_LED_OVERR_REG, reg); | |
307 | } | |
308 | ||
309 | /* Check link status and return a boolean OK value. If the link is NOT | |
310 | * OK we have a quick rummage round to see if we appear to be plugged | |
311 | * into a non-10GBT port and if so warn the user that they won't get | |
312 | * link any time soon as we are 10GBT only, unless caller specified | |
313 | * not to do this check (it isn't useful in loopback) */ | |
314 | static int tenxpress_link_ok(struct efx_nic *efx, int check_lp) | |
315 | { | |
316 | int ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS); | |
317 | ||
318 | if (ok) { | |
319 | tenxpress_set_bad_lp(efx, 0); | |
320 | } else if (check_lp) { | |
321 | /* Are we plugged into the wrong sort of link? */ | |
322 | int bad_lp = 0; | |
323 | int phy_id = efx->mii.phy_id; | |
324 | int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | |
325 | MDIO_AN_STATUS); | |
326 | int xphy_stat = mdio_clause45_read(efx, phy_id, | |
327 | MDIO_MMD_PMAPMD, | |
328 | PMA_PMD_XSTATUS_REG); | |
329 | /* Are we plugged into anything that sends FLPs? If | |
330 | * not we can't distinguish between not being plugged | |
331 | * in and being plugged into a non-AN antique. The FLP | |
332 | * bit has the advantage of not clearing when autoneg | |
333 | * restarts. */ | |
334 | if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) { | |
335 | tenxpress_set_bad_lp(efx, 0); | |
336 | return ok; | |
337 | } | |
338 | ||
339 | /* If it can do 10GBT it must be XNP capable */ | |
340 | bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN)); | |
341 | if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) { | |
342 | bad_lp = !(mdio_clause45_read(efx, phy_id, | |
343 | MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) & | |
344 | (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN)); | |
345 | } | |
346 | tenxpress_set_bad_lp(efx, bad_lp); | |
347 | } | |
348 | return ok; | |
349 | } | |
350 | ||
3273c2e8 BH |
351 | static void tenxpress_phyxs_loopback(struct efx_nic *efx) |
352 | { | |
353 | int phy_id = efx->mii.phy_id; | |
354 | int ctrl1, ctrl2; | |
355 | ||
356 | ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS, | |
357 | PHYXS_TEST1); | |
358 | if (efx->loopback_mode == LOOPBACK_PHYXS) | |
359 | ctrl2 |= (1 << LOOPBACK_NEAR_LBN); | |
360 | else | |
361 | ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN); | |
362 | if (ctrl1 != ctrl2) | |
363 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS, | |
364 | PHYXS_TEST1, ctrl2); | |
365 | } | |
366 | ||
8ceee660 BH |
367 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
368 | { | |
3273c2e8 BH |
369 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
370 | int loop_change = LOOPBACK_OUT_OF(phy_data, efx, | |
371 | TENXPRESS_LOOPBACKS); | |
372 | ||
8ceee660 BH |
373 | if (!tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL)) |
374 | return; | |
375 | ||
3273c2e8 BH |
376 | /* When coming out of transmit disable, coming out of low power |
377 | * mode, or moving out of any PHY internal loopback mode, | |
378 | * perform a special software reset */ | |
379 | if ((phy_data->tx_disabled && !efx->tx_disabled) || | |
380 | loop_change) { | |
91ad757c | 381 | tenxpress_special_reset(efx); |
3273c2e8 BH |
382 | falcon_reset_xaui(efx); |
383 | } | |
384 | ||
385 | mdio_clause45_transmit_disable(efx); | |
386 | mdio_clause45_phy_reconfigure(efx); | |
387 | tenxpress_phyxs_loopback(efx); | |
388 | ||
389 | phy_data->tx_disabled = efx->tx_disabled; | |
390 | phy_data->loopback_mode = efx->loopback_mode; | |
8ceee660 BH |
391 | efx->link_up = tenxpress_link_ok(efx, 0); |
392 | efx->link_options = GM_LPA_10000FULL; | |
393 | } | |
394 | ||
395 | static void tenxpress_phy_clear_interrupt(struct efx_nic *efx) | |
396 | { | |
397 | /* Nothing done here - LASI interrupts aren't reliable so poll */ | |
398 | } | |
399 | ||
400 | ||
401 | /* Poll PHY for interrupt */ | |
402 | static int tenxpress_phy_check_hw(struct efx_nic *efx) | |
403 | { | |
404 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
405 | int phy_up = tenxpress_state_is(efx, TENXPRESS_STATUS_NORMAL); | |
406 | int link_ok; | |
407 | ||
408 | link_ok = phy_up && tenxpress_link_ok(efx, 1); | |
409 | ||
410 | if (link_ok != efx->link_up) | |
411 | falcon_xmac_sim_phy_event(efx); | |
412 | ||
413 | /* Nothing to check if we've already shut down the PHY */ | |
414 | if (!phy_up) | |
415 | return 0; | |
416 | ||
417 | if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) { | |
418 | EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n"); | |
419 | falcon_reset_xaui(efx); | |
420 | atomic_set(&phy_data->bad_crc_count, 0); | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
427 | { | |
428 | int reg; | |
429 | ||
430 | /* Power down the LNPGA */ | |
431 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
432 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
433 | PMA_PMD_XCONTROL_REG, reg); | |
434 | ||
435 | /* Waiting here ensures that the board fini, which can turn off the | |
436 | * power to the PHY, won't get run until the LNPGA powerdown has been | |
437 | * given long enough to complete. */ | |
438 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
439 | ||
440 | kfree(efx->phy_data); | |
441 | efx->phy_data = NULL; | |
442 | } | |
443 | ||
444 | ||
445 | /* Set the RX and TX LEDs and Link LED flashing. The other LEDs | |
446 | * (which probably aren't wired anyway) are left in AUTO mode */ | |
447 | void tenxpress_phy_blink(struct efx_nic *efx, int blink) | |
448 | { | |
449 | int reg; | |
450 | ||
451 | if (blink) | |
452 | reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) | | |
453 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) | | |
454 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN); | |
455 | else | |
456 | reg = PMA_PMD_LED_DEFAULT; | |
457 | ||
458 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
459 | PMA_PMD_LED_OVERR_REG, reg); | |
460 | } | |
461 | ||
462 | static void tenxpress_reset_xaui(struct efx_nic *efx) | |
463 | { | |
464 | int phy = efx->mii.phy_id; | |
465 | int clk_ctrl, test_select, soft_rst2; | |
466 | ||
467 | /* Real work is done on clock_ctrl other resets are thought to be | |
468 | * optional but make the reset more reliable | |
469 | */ | |
470 | ||
471 | /* Read */ | |
472 | clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | |
473 | PCS_CLOCK_CTRL_REG); | |
474 | test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | |
475 | PCS_TEST_SELECT_REG); | |
476 | soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | |
477 | PCS_SOFT_RST2_REG); | |
478 | ||
479 | /* Put in reset */ | |
480 | test_select &= ~(1 << CLK312_EN_LBN); | |
481 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
482 | PCS_TEST_SELECT_REG, test_select); | |
483 | ||
484 | soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN)); | |
485 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
486 | PCS_SOFT_RST2_REG, soft_rst2); | |
487 | ||
488 | clk_ctrl &= ~(1 << PLL312_RST_N_LBN); | |
489 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
490 | PCS_CLOCK_CTRL_REG, clk_ctrl); | |
491 | udelay(10); | |
492 | ||
493 | /* Remove reset */ | |
494 | clk_ctrl |= (1 << PLL312_RST_N_LBN); | |
495 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
496 | PCS_CLOCK_CTRL_REG, clk_ctrl); | |
497 | udelay(10); | |
498 | ||
499 | soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN)); | |
500 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
501 | PCS_SOFT_RST2_REG, soft_rst2); | |
502 | udelay(10); | |
503 | ||
504 | test_select |= (1 << CLK312_EN_LBN); | |
505 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | |
506 | PCS_TEST_SELECT_REG, test_select); | |
507 | udelay(10); | |
508 | } | |
509 | ||
510 | struct efx_phy_operations falcon_tenxpress_phy_ops = { | |
511 | .init = tenxpress_phy_init, | |
512 | .reconfigure = tenxpress_phy_reconfigure, | |
513 | .check_hw = tenxpress_phy_check_hw, | |
514 | .fini = tenxpress_phy_fini, | |
515 | .clear_interrupt = tenxpress_phy_clear_interrupt, | |
516 | .reset_xaui = tenxpress_reset_xaui, | |
517 | .mmds = TENXPRESS_REQUIRED_DEVS, | |
3273c2e8 | 518 | .loopbacks = TENXPRESS_LOOPBACKS, |
8ceee660 | 519 | }; |