Commit | Line | Data |
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f938d2c8 RR |
1 | /*P:010 |
2 | * A hypervisor allows multiple Operating Systems to run on a single machine. | |
3 | * To quote David Wheeler: "Any problem in computer science can be solved with | |
4 | * another layer of indirection." | |
5 | * | |
6 | * We keep things simple in two ways. First, we start with a normal Linux | |
7 | * kernel and insert a module (lg.ko) which allows us to run other Linux | |
8 | * kernels the same way we'd run processes. We call the first kernel the Host, | |
9 | * and the others the Guests. The program which sets up and configures Guests | |
10 | * (such as the example in Documentation/lguest/lguest.c) is called the | |
11 | * Launcher. | |
12 | * | |
a6bd8e13 RR |
13 | * Secondly, we only run specially modified Guests, not normal kernels: setting |
14 | * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows | |
15 | * how to be a Guest at boot time. This means that you can use the same kernel | |
16 | * you boot normally (ie. as a Host) as a Guest. | |
07ad157f | 17 | * |
f938d2c8 RR |
18 | * These Guests know that they cannot do privileged operations, such as disable |
19 | * interrupts, and that they have to ask the Host to do such things explicitly. | |
20 | * This file consists of all the replacements for such low-level native | |
21 | * hardware operations: these special Guest versions call the Host. | |
22 | * | |
a6bd8e13 RR |
23 | * So how does the kernel know it's a Guest? We'll see that later, but let's |
24 | * just say that we end up here where we replace the native functions various | |
25 | * "paravirt" structures with our Guest versions, then boot like normal. :*/ | |
f938d2c8 RR |
26 | |
27 | /* | |
07ad157f RR |
28 | * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation. |
29 | * | |
30 | * This program is free software; you can redistribute it and/or modify | |
31 | * it under the terms of the GNU General Public License as published by | |
32 | * the Free Software Foundation; either version 2 of the License, or | |
33 | * (at your option) any later version. | |
34 | * | |
35 | * This program is distributed in the hope that it will be useful, but | |
36 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
37 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
38 | * NON INFRINGEMENT. See the GNU General Public License for more | |
39 | * details. | |
40 | * | |
41 | * You should have received a copy of the GNU General Public License | |
42 | * along with this program; if not, write to the Free Software | |
43 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
44 | */ | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/start_kernel.h> | |
47 | #include <linux/string.h> | |
48 | #include <linux/console.h> | |
49 | #include <linux/screen_info.h> | |
50 | #include <linux/irq.h> | |
51 | #include <linux/interrupt.h> | |
d7e28ffe RR |
52 | #include <linux/clocksource.h> |
53 | #include <linux/clockchips.h> | |
07ad157f RR |
54 | #include <linux/lguest.h> |
55 | #include <linux/lguest_launcher.h> | |
19f1537b | 56 | #include <linux/virtio_console.h> |
4cfe6c3c | 57 | #include <linux/pm.h> |
7be42004 | 58 | #include <asm/apic.h> |
cbc34973 | 59 | #include <asm/lguest.h> |
07ad157f RR |
60 | #include <asm/paravirt.h> |
61 | #include <asm/param.h> | |
62 | #include <asm/page.h> | |
63 | #include <asm/pgtable.h> | |
64 | #include <asm/desc.h> | |
65 | #include <asm/setup.h> | |
66 | #include <asm/e820.h> | |
67 | #include <asm/mce.h> | |
68 | #include <asm/io.h> | |
625efab1 | 69 | #include <asm/i387.h> |
ec04b13f | 70 | #include <asm/reboot.h> /* for struct machine_ops */ |
07ad157f | 71 | |
b2b47c21 RR |
72 | /*G:010 Welcome to the Guest! |
73 | * | |
74 | * The Guest in our tale is a simple creature: identical to the Host but | |
75 | * behaving in simplified but equivalent ways. In particular, the Guest is the | |
76 | * same kernel as the Host (or at least, built from the same source code). :*/ | |
77 | ||
07ad157f RR |
78 | struct lguest_data lguest_data = { |
79 | .hcall_status = { [0 ... LHCALL_RING_SIZE-1] = 0xFF }, | |
80 | .noirq_start = (u32)lguest_noirq_start, | |
81 | .noirq_end = (u32)lguest_noirq_end, | |
47436aa4 | 82 | .kernel_address = PAGE_OFFSET, |
07ad157f | 83 | .blocked_interrupts = { 1 }, /* Block timer interrupts */ |
c18acd73 | 84 | .syscall_vec = SYSCALL_VECTOR, |
07ad157f | 85 | }; |
07ad157f | 86 | |
633872b9 | 87 | /*G:037 async_hcall() is pretty simple: I'm quite proud of it really. We have a |
b2b47c21 RR |
88 | * ring buffer of stored hypercalls which the Host will run though next time we |
89 | * do a normal hypercall. Each entry in the ring has 4 slots for the hypercall | |
90 | * arguments, and a "hcall_status" word which is 0 if the call is ready to go, | |
91 | * and 255 once the Host has finished with it. | |
92 | * | |
93 | * If we come around to a slot which hasn't been finished, then the table is | |
94 | * full and we just make the hypercall directly. This has the nice side | |
95 | * effect of causing the Host to run all the stored calls in the ring buffer | |
96 | * which empties it for next time! */ | |
9b56fdb4 AB |
97 | static void async_hcall(unsigned long call, unsigned long arg1, |
98 | unsigned long arg2, unsigned long arg3) | |
07ad157f RR |
99 | { |
100 | /* Note: This code assumes we're uniprocessor. */ | |
101 | static unsigned int next_call; | |
102 | unsigned long flags; | |
103 | ||
b2b47c21 RR |
104 | /* Disable interrupts if not already disabled: we don't want an |
105 | * interrupt handler making a hypercall while we're already doing | |
106 | * one! */ | |
07ad157f RR |
107 | local_irq_save(flags); |
108 | if (lguest_data.hcall_status[next_call] != 0xFF) { | |
109 | /* Table full, so do normal hcall which will flush table. */ | |
110 | hcall(call, arg1, arg2, arg3); | |
111 | } else { | |
b410e7b1 JS |
112 | lguest_data.hcalls[next_call].arg0 = call; |
113 | lguest_data.hcalls[next_call].arg1 = arg1; | |
114 | lguest_data.hcalls[next_call].arg2 = arg2; | |
115 | lguest_data.hcalls[next_call].arg3 = arg3; | |
b2b47c21 | 116 | /* Arguments must all be written before we mark it to go */ |
07ad157f RR |
117 | wmb(); |
118 | lguest_data.hcall_status[next_call] = 0; | |
119 | if (++next_call == LHCALL_RING_SIZE) | |
120 | next_call = 0; | |
121 | } | |
122 | local_irq_restore(flags); | |
123 | } | |
9b56fdb4 | 124 | |
633872b9 RR |
125 | /*G:035 Notice the lazy_hcall() above, rather than hcall(). This is our first |
126 | * real optimization trick! | |
127 | * | |
128 | * When lazy_mode is set, it means we're allowed to defer all hypercalls and do | |
129 | * them as a batch when lazy_mode is eventually turned off. Because hypercalls | |
130 | * are reasonably expensive, batching them up makes sense. For example, a | |
131 | * large munmap might update dozens of page table entries: that code calls | |
132 | * paravirt_enter_lazy_mmu(), does the dozen updates, then calls | |
133 | * lguest_leave_lazy_mode(). | |
134 | * | |
135 | * So, when we're in lazy mode, we call async_hcall() to store the call for | |
a6bd8e13 | 136 | * future processing: */ |
9b56fdb4 AB |
137 | static void lazy_hcall(unsigned long call, |
138 | unsigned long arg1, | |
139 | unsigned long arg2, | |
140 | unsigned long arg3) | |
141 | { | |
142 | if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) | |
143 | hcall(call, arg1, arg2, arg3); | |
144 | else | |
145 | async_hcall(call, arg1, arg2, arg3); | |
146 | } | |
633872b9 RR |
147 | |
148 | /* When lazy mode is turned off reset the per-cpu lazy mode variable and then | |
a6bd8e13 | 149 | * issue the do-nothing hypercall to flush any stored calls. */ |
633872b9 RR |
150 | static void lguest_leave_lazy_mode(void) |
151 | { | |
152 | paravirt_leave_lazy(paravirt_get_lazy_mode()); | |
153 | hcall(LHCALL_FLUSH_ASYNC, 0, 0, 0); | |
154 | } | |
07ad157f | 155 | |
b2b47c21 | 156 | /*G:033 |
e1e72965 RR |
157 | * After that diversion we return to our first native-instruction |
158 | * replacements: four functions for interrupt control. | |
b2b47c21 RR |
159 | * |
160 | * The simplest way of implementing these would be to have "turn interrupts | |
161 | * off" and "turn interrupts on" hypercalls. Unfortunately, this is too slow: | |
162 | * these are by far the most commonly called functions of those we override. | |
163 | * | |
164 | * So instead we keep an "irq_enabled" field inside our "struct lguest_data", | |
165 | * which the Guest can update with a single instruction. The Host knows to | |
a6bd8e13 | 166 | * check there before it tries to deliver an interrupt. |
b2b47c21 RR |
167 | */ |
168 | ||
65ea5b03 PA |
169 | /* save_flags() is expected to return the processor state (ie. "flags"). The |
170 | * flags word contains all kind of stuff, but in practice Linux only cares | |
b2b47c21 | 171 | * about the interrupt flag. Our "save_flags()" just returns that. */ |
07ad157f RR |
172 | static unsigned long save_fl(void) |
173 | { | |
174 | return lguest_data.irq_enabled; | |
175 | } | |
176 | ||
e1e72965 | 177 | /* restore_flags() just sets the flags back to the value given. */ |
07ad157f RR |
178 | static void restore_fl(unsigned long flags) |
179 | { | |
07ad157f RR |
180 | lguest_data.irq_enabled = flags; |
181 | } | |
182 | ||
b2b47c21 | 183 | /* Interrupts go off... */ |
07ad157f RR |
184 | static void irq_disable(void) |
185 | { | |
186 | lguest_data.irq_enabled = 0; | |
187 | } | |
188 | ||
b2b47c21 | 189 | /* Interrupts go on... */ |
07ad157f RR |
190 | static void irq_enable(void) |
191 | { | |
07ad157f RR |
192 | lguest_data.irq_enabled = X86_EFLAGS_IF; |
193 | } | |
f56a384e RR |
194 | /*:*/ |
195 | /*M:003 Note that we don't check for outstanding interrupts when we re-enable | |
196 | * them (or when we unmask an interrupt). This seems to work for the moment, | |
197 | * since interrupts are rare and we'll just get the interrupt on the next timer | |
a6bd8e13 | 198 | * tick, but now we can run with CONFIG_NO_HZ, we should revisit this. One way |
f56a384e RR |
199 | * would be to put the "irq_enabled" field in a page by itself, and have the |
200 | * Host write-protect it when an interrupt comes in when irqs are disabled. | |
a6bd8e13 RR |
201 | * There will then be a page fault as soon as interrupts are re-enabled. |
202 | * | |
203 | * A better method is to implement soft interrupt disable generally for x86: | |
204 | * instead of disabling interrupts, we set a flag. If an interrupt does come | |
205 | * in, we then disable them for real. This is uncommon, so we could simply use | |
206 | * a hypercall for interrupt control and not worry about efficiency. :*/ | |
07ad157f | 207 | |
b2b47c21 RR |
208 | /*G:034 |
209 | * The Interrupt Descriptor Table (IDT). | |
210 | * | |
211 | * The IDT tells the processor what to do when an interrupt comes in. Each | |
212 | * entry in the table is a 64-bit descriptor: this holds the privilege level, | |
213 | * address of the handler, and... well, who cares? The Guest just asks the | |
214 | * Host to make the change anyway, because the Host controls the real IDT. | |
215 | */ | |
8d947344 GOC |
216 | static void lguest_write_idt_entry(gate_desc *dt, |
217 | int entrynum, const gate_desc *g) | |
07ad157f | 218 | { |
a6bd8e13 RR |
219 | /* The gate_desc structure is 8 bytes long: we hand it to the Host in |
220 | * two 32-bit chunks. The whole 32-bit kernel used to hand descriptors | |
221 | * around like this; typesafety wasn't a big concern in Linux's early | |
222 | * years. */ | |
8d947344 | 223 | u32 *desc = (u32 *)g; |
b2b47c21 | 224 | /* Keep the local copy up to date. */ |
8d947344 | 225 | native_write_idt_entry(dt, entrynum, g); |
b2b47c21 | 226 | /* Tell Host about this new entry. */ |
8d947344 | 227 | hcall(LHCALL_LOAD_IDT_ENTRY, entrynum, desc[0], desc[1]); |
07ad157f RR |
228 | } |
229 | ||
b2b47c21 RR |
230 | /* Changing to a different IDT is very rare: we keep the IDT up-to-date every |
231 | * time it is written, so we can simply loop through all entries and tell the | |
232 | * Host about them. */ | |
6b68f01b | 233 | static void lguest_load_idt(const struct desc_ptr *desc) |
07ad157f RR |
234 | { |
235 | unsigned int i; | |
236 | struct desc_struct *idt = (void *)desc->address; | |
237 | ||
238 | for (i = 0; i < (desc->size+1)/8; i++) | |
239 | hcall(LHCALL_LOAD_IDT_ENTRY, i, idt[i].a, idt[i].b); | |
240 | } | |
241 | ||
b2b47c21 RR |
242 | /* |
243 | * The Global Descriptor Table. | |
244 | * | |
245 | * The Intel architecture defines another table, called the Global Descriptor | |
246 | * Table (GDT). You tell the CPU where it is (and its size) using the "lgdt" | |
247 | * instruction, and then several other instructions refer to entries in the | |
248 | * table. There are three entries which the Switcher needs, so the Host simply | |
249 | * controls the entire thing and the Guest asks it to make changes using the | |
250 | * LOAD_GDT hypercall. | |
251 | * | |
252 | * This is the opposite of the IDT code where we have a LOAD_IDT_ENTRY | |
253 | * hypercall and use that repeatedly to load a new IDT. I don't think it | |
a6bd8e13 RR |
254 | * really matters, but wouldn't it be nice if they were the same? Wouldn't |
255 | * it be even better if you were the one to send the patch to fix it? | |
b2b47c21 | 256 | */ |
6b68f01b | 257 | static void lguest_load_gdt(const struct desc_ptr *desc) |
07ad157f RR |
258 | { |
259 | BUG_ON((desc->size+1)/8 != GDT_ENTRIES); | |
260 | hcall(LHCALL_LOAD_GDT, __pa(desc->address), GDT_ENTRIES, 0); | |
261 | } | |
262 | ||
b2b47c21 RR |
263 | /* For a single GDT entry which changes, we do the lazy thing: alter our GDT, |
264 | * then tell the Host to reload the entire thing. This operation is so rare | |
265 | * that this naive implementation is reasonable. */ | |
014b15be GOC |
266 | static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum, |
267 | const void *desc, int type) | |
07ad157f | 268 | { |
014b15be | 269 | native_write_gdt_entry(dt, entrynum, desc, type); |
07ad157f RR |
270 | hcall(LHCALL_LOAD_GDT, __pa(dt), GDT_ENTRIES, 0); |
271 | } | |
272 | ||
b2b47c21 RR |
273 | /* OK, I lied. There are three "thread local storage" GDT entries which change |
274 | * on every context switch (these three entries are how glibc implements | |
275 | * __thread variables). So we have a hypercall specifically for this case. */ | |
07ad157f RR |
276 | static void lguest_load_tls(struct thread_struct *t, unsigned int cpu) |
277 | { | |
0d027c01 RR |
278 | /* There's one problem which normal hardware doesn't have: the Host |
279 | * can't handle us removing entries we're currently using. So we clear | |
280 | * the GS register here: if it's needed it'll be reloaded anyway. */ | |
281 | loadsegment(gs, 0); | |
07ad157f RR |
282 | lazy_hcall(LHCALL_LOAD_TLS, __pa(&t->tls_array), cpu, 0); |
283 | } | |
284 | ||
b2b47c21 | 285 | /*G:038 That's enough excitement for now, back to ploughing through each of |
93b1eab3 | 286 | * the different pv_ops structures (we're about 1/3 of the way through). |
b2b47c21 RR |
287 | * |
288 | * This is the Local Descriptor Table, another weird Intel thingy. Linux only | |
289 | * uses this for some strange applications like Wine. We don't do anything | |
290 | * here, so they'll get an informative and friendly Segmentation Fault. */ | |
07ad157f RR |
291 | static void lguest_set_ldt(const void *addr, unsigned entries) |
292 | { | |
293 | } | |
294 | ||
b2b47c21 RR |
295 | /* This loads a GDT entry into the "Task Register": that entry points to a |
296 | * structure called the Task State Segment. Some comments scattered though the | |
297 | * kernel code indicate that this used for task switching in ages past, along | |
298 | * with blood sacrifice and astrology. | |
299 | * | |
300 | * Now there's nothing interesting in here that we don't get told elsewhere. | |
301 | * But the native version uses the "ltr" instruction, which makes the Host | |
302 | * complain to the Guest about a Segmentation Fault and it'll oops. So we | |
303 | * override the native version with a do-nothing version. */ | |
07ad157f RR |
304 | static void lguest_load_tr_desc(void) |
305 | { | |
306 | } | |
307 | ||
b2b47c21 RR |
308 | /* The "cpuid" instruction is a way of querying both the CPU identity |
309 | * (manufacturer, model, etc) and its features. It was introduced before the | |
a6bd8e13 RR |
310 | * Pentium in 1993 and keeps getting extended by both Intel, AMD and others. |
311 | * As you might imagine, after a decade and a half this treatment, it is now a | |
312 | * giant ball of hair. Its entry in the current Intel manual runs to 28 pages. | |
b2b47c21 RR |
313 | * |
314 | * This instruction even it has its own Wikipedia entry. The Wikipedia entry | |
315 | * has been translated into 4 languages. I am not making this up! | |
316 | * | |
317 | * We could get funky here and identify ourselves as "GenuineLguest", but | |
318 | * instead we just use the real "cpuid" instruction. Then I pretty much turned | |
319 | * off feature bits until the Guest booted. (Don't say that: you'll damage | |
320 | * lguest sales!) Shut up, inner voice! (Hey, just pointing out that this is | |
321 | * hardly future proof.) Noone's listening! They don't like you anyway, | |
322 | * parenthetic weirdo! | |
323 | * | |
324 | * Replacing the cpuid so we can turn features off is great for the kernel, but | |
325 | * anyone (including userspace) can just use the raw "cpuid" instruction and | |
326 | * the Host won't even notice since it isn't privileged. So we try not to get | |
327 | * too worked up about it. */ | |
65ea5b03 PA |
328 | static void lguest_cpuid(unsigned int *ax, unsigned int *bx, |
329 | unsigned int *cx, unsigned int *dx) | |
07ad157f | 330 | { |
65ea5b03 | 331 | int function = *ax; |
07ad157f | 332 | |
65ea5b03 | 333 | native_cpuid(ax, bx, cx, dx); |
07ad157f RR |
334 | switch (function) { |
335 | case 1: /* Basic feature request. */ | |
336 | /* We only allow kernel to see SSE3, CMPXCHG16B and SSSE3 */ | |
65ea5b03 | 337 | *cx &= 0x00002201; |
3fabc55f RR |
338 | /* SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, TSC, FPU. */ |
339 | *dx &= 0x07808111; | |
b2b47c21 RR |
340 | /* The Host can do a nice optimization if it knows that the |
341 | * kernel mappings (addresses above 0xC0000000 or whatever | |
342 | * PAGE_OFFSET is set to) haven't changed. But Linux calls | |
343 | * flush_tlb_user() for both user and kernel mappings unless | |
344 | * the Page Global Enable (PGE) feature bit is set. */ | |
65ea5b03 | 345 | *dx |= 0x00002000; |
07ad157f RR |
346 | break; |
347 | case 0x80000000: | |
348 | /* Futureproof this a little: if they ask how much extended | |
b2b47c21 | 349 | * processor information there is, limit it to known fields. */ |
65ea5b03 PA |
350 | if (*ax > 0x80000008) |
351 | *ax = 0x80000008; | |
07ad157f RR |
352 | break; |
353 | } | |
354 | } | |
355 | ||
b2b47c21 RR |
356 | /* Intel has four control registers, imaginatively named cr0, cr2, cr3 and cr4. |
357 | * I assume there's a cr1, but it hasn't bothered us yet, so we'll not bother | |
358 | * it. The Host needs to know when the Guest wants to change them, so we have | |
359 | * a whole series of functions like read_cr0() and write_cr0(). | |
360 | * | |
e1e72965 | 361 | * We start with cr0. cr0 allows you to turn on and off all kinds of basic |
b2b47c21 RR |
362 | * features, but Linux only really cares about one: the horrifically-named Task |
363 | * Switched (TS) bit at bit 3 (ie. 8) | |
364 | * | |
365 | * What does the TS bit do? Well, it causes the CPU to trap (interrupt 7) if | |
366 | * the floating point unit is used. Which allows us to restore FPU state | |
367 | * lazily after a task switch, and Linux uses that gratefully, but wouldn't a | |
368 | * name like "FPUTRAP bit" be a little less cryptic? | |
369 | * | |
ad5173ff RR |
370 | * We store cr0 locally because the Host never changes it. The Guest sometimes |
371 | * wants to read it and we'd prefer not to bother the Host unnecessarily. */ | |
372 | static unsigned long current_cr0; | |
07ad157f RR |
373 | static void lguest_write_cr0(unsigned long val) |
374 | { | |
25c47bb3 | 375 | lazy_hcall(LHCALL_TS, val & X86_CR0_TS, 0, 0); |
07ad157f RR |
376 | current_cr0 = val; |
377 | } | |
378 | ||
379 | static unsigned long lguest_read_cr0(void) | |
380 | { | |
381 | return current_cr0; | |
382 | } | |
383 | ||
b2b47c21 RR |
384 | /* Intel provided a special instruction to clear the TS bit for people too cool |
385 | * to use write_cr0() to do it. This "clts" instruction is faster, because all | |
386 | * the vowels have been optimized out. */ | |
07ad157f RR |
387 | static void lguest_clts(void) |
388 | { | |
389 | lazy_hcall(LHCALL_TS, 0, 0, 0); | |
25c47bb3 | 390 | current_cr0 &= ~X86_CR0_TS; |
07ad157f RR |
391 | } |
392 | ||
e1e72965 | 393 | /* cr2 is the virtual address of the last page fault, which the Guest only ever |
b2b47c21 RR |
394 | * reads. The Host kindly writes this into our "struct lguest_data", so we |
395 | * just read it out of there. */ | |
07ad157f RR |
396 | static unsigned long lguest_read_cr2(void) |
397 | { | |
398 | return lguest_data.cr2; | |
399 | } | |
400 | ||
ad5173ff RR |
401 | /* See lguest_set_pte() below. */ |
402 | static bool cr3_changed = false; | |
403 | ||
e1e72965 | 404 | /* cr3 is the current toplevel pagetable page: the principle is the same as |
ad5173ff RR |
405 | * cr0. Keep a local copy, and tell the Host when it changes. The only |
406 | * difference is that our local copy is in lguest_data because the Host needs | |
407 | * to set it upon our initial hypercall. */ | |
07ad157f RR |
408 | static void lguest_write_cr3(unsigned long cr3) |
409 | { | |
ad5173ff | 410 | lguest_data.pgdir = cr3; |
07ad157f | 411 | lazy_hcall(LHCALL_NEW_PGTABLE, cr3, 0, 0); |
ad5173ff | 412 | cr3_changed = true; |
07ad157f RR |
413 | } |
414 | ||
415 | static unsigned long lguest_read_cr3(void) | |
416 | { | |
ad5173ff | 417 | return lguest_data.pgdir; |
07ad157f RR |
418 | } |
419 | ||
e1e72965 | 420 | /* cr4 is used to enable and disable PGE, but we don't care. */ |
07ad157f RR |
421 | static unsigned long lguest_read_cr4(void) |
422 | { | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static void lguest_write_cr4(unsigned long val) | |
427 | { | |
428 | } | |
429 | ||
b2b47c21 RR |
430 | /* |
431 | * Page Table Handling. | |
432 | * | |
433 | * Now would be a good time to take a rest and grab a coffee or similarly | |
434 | * relaxing stimulant. The easy parts are behind us, and the trek gradually | |
435 | * winds uphill from here. | |
436 | * | |
437 | * Quick refresher: memory is divided into "pages" of 4096 bytes each. The CPU | |
438 | * maps virtual addresses to physical addresses using "page tables". We could | |
439 | * use one huge index of 1 million entries: each address is 4 bytes, so that's | |
440 | * 1024 pages just to hold the page tables. But since most virtual addresses | |
e1e72965 | 441 | * are unused, we use a two level index which saves space. The cr3 register |
b2b47c21 RR |
442 | * contains the physical address of the top level "page directory" page, which |
443 | * contains physical addresses of up to 1024 second-level pages. Each of these | |
444 | * second level pages contains up to 1024 physical addresses of actual pages, | |
445 | * or Page Table Entries (PTEs). | |
446 | * | |
447 | * Here's a diagram, where arrows indicate physical addresses: | |
448 | * | |
e1e72965 | 449 | * cr3 ---> +---------+ |
b2b47c21 RR |
450 | * | --------->+---------+ |
451 | * | | | PADDR1 | | |
452 | * Top-level | | PADDR2 | | |
453 | * (PMD) page | | | | |
454 | * | | Lower-level | | |
455 | * | | (PTE) page | | |
456 | * | | | | | |
457 | * .... .... | |
458 | * | |
459 | * So to convert a virtual address to a physical address, we look up the top | |
460 | * level, which points us to the second level, which gives us the physical | |
461 | * address of that page. If the top level entry was not present, or the second | |
462 | * level entry was not present, then the virtual address is invalid (we | |
463 | * say "the page was not mapped"). | |
464 | * | |
465 | * Put another way, a 32-bit virtual address is divided up like so: | |
466 | * | |
467 | * 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | |
468 | * |<---- 10 bits ---->|<---- 10 bits ---->|<------ 12 bits ------>| | |
469 | * Index into top Index into second Offset within page | |
470 | * page directory page pagetable page | |
471 | * | |
472 | * The kernel spends a lot of time changing both the top-level page directory | |
473 | * and lower-level pagetable pages. The Guest doesn't know physical addresses, | |
474 | * so while it maintains these page tables exactly like normal, it also needs | |
475 | * to keep the Host informed whenever it makes a change: the Host will create | |
476 | * the real page tables based on the Guests'. | |
477 | */ | |
478 | ||
479 | /* The Guest calls this to set a second-level entry (pte), ie. to map a page | |
480 | * into a process' address space. We set the entry then tell the Host the | |
481 | * toplevel and address this corresponds to. The Guest uses one pagetable per | |
482 | * process, so we need to tell the Host which one we're changing (mm->pgd). */ | |
07ad157f RR |
483 | static void lguest_set_pte_at(struct mm_struct *mm, unsigned long addr, |
484 | pte_t *ptep, pte_t pteval) | |
485 | { | |
486 | *ptep = pteval; | |
487 | lazy_hcall(LHCALL_SET_PTE, __pa(mm->pgd), addr, pteval.pte_low); | |
488 | } | |
489 | ||
b2b47c21 RR |
490 | /* The Guest calls this to set a top-level entry. Again, we set the entry then |
491 | * tell the Host which top-level page we changed, and the index of the entry we | |
492 | * changed. */ | |
07ad157f RR |
493 | static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval) |
494 | { | |
495 | *pmdp = pmdval; | |
496 | lazy_hcall(LHCALL_SET_PMD, __pa(pmdp)&PAGE_MASK, | |
4357bd94 | 497 | (__pa(pmdp)&(PAGE_SIZE-1))/4, 0); |
07ad157f RR |
498 | } |
499 | ||
b2b47c21 RR |
500 | /* There are a couple of legacy places where the kernel sets a PTE, but we |
501 | * don't know the top level any more. This is useless for us, since we don't | |
502 | * know which pagetable is changing or what address, so we just tell the Host | |
503 | * to forget all of them. Fortunately, this is very rare. | |
504 | * | |
505 | * ... except in early boot when the kernel sets up the initial pagetables, | |
ad5173ff RR |
506 | * which makes booting astonishingly slow: 1.83 seconds! So we don't even tell |
507 | * the Host anything changed until we've done the first page table switch, | |
508 | * which brings boot back to 0.25 seconds. */ | |
07ad157f RR |
509 | static void lguest_set_pte(pte_t *ptep, pte_t pteval) |
510 | { | |
511 | *ptep = pteval; | |
ad5173ff | 512 | if (cr3_changed) |
07ad157f RR |
513 | lazy_hcall(LHCALL_FLUSH_TLB, 1, 0, 0); |
514 | } | |
515 | ||
93b1eab3 | 516 | /* Unfortunately for Lguest, the pv_mmu_ops for page tables were based on |
b2b47c21 RR |
517 | * native page table operations. On native hardware you can set a new page |
518 | * table entry whenever you want, but if you want to remove one you have to do | |
519 | * a TLB flush (a TLB is a little cache of page table entries kept by the CPU). | |
520 | * | |
521 | * So the lguest_set_pte_at() and lguest_set_pmd() functions above are only | |
522 | * called when a valid entry is written, not when it's removed (ie. marked not | |
523 | * present). Instead, this is where we come when the Guest wants to remove a | |
524 | * page table entry: we tell the Host to set that entry to 0 (ie. the present | |
525 | * bit is zero). */ | |
07ad157f RR |
526 | static void lguest_flush_tlb_single(unsigned long addr) |
527 | { | |
b2b47c21 | 528 | /* Simply set it to zero: if it was not, it will fault back in. */ |
ad5173ff | 529 | lazy_hcall(LHCALL_SET_PTE, lguest_data.pgdir, addr, 0); |
07ad157f RR |
530 | } |
531 | ||
b2b47c21 RR |
532 | /* This is what happens after the Guest has removed a large number of entries. |
533 | * This tells the Host that any of the page table entries for userspace might | |
534 | * have changed, ie. virtual addresses below PAGE_OFFSET. */ | |
07ad157f RR |
535 | static void lguest_flush_tlb_user(void) |
536 | { | |
537 | lazy_hcall(LHCALL_FLUSH_TLB, 0, 0, 0); | |
538 | } | |
539 | ||
b2b47c21 RR |
540 | /* This is called when the kernel page tables have changed. That's not very |
541 | * common (unless the Guest is using highmem, which makes the Guest extremely | |
542 | * slow), so it's worth separating this from the user flushing above. */ | |
07ad157f RR |
543 | static void lguest_flush_tlb_kernel(void) |
544 | { | |
545 | lazy_hcall(LHCALL_FLUSH_TLB, 1, 0, 0); | |
546 | } | |
547 | ||
b2b47c21 RR |
548 | /* |
549 | * The Unadvanced Programmable Interrupt Controller. | |
550 | * | |
551 | * This is an attempt to implement the simplest possible interrupt controller. | |
552 | * I spent some time looking though routines like set_irq_chip_and_handler, | |
553 | * set_irq_chip_and_handler_name, set_irq_chip_data and set_phasers_to_stun and | |
554 | * I *think* this is as simple as it gets. | |
555 | * | |
556 | * We can tell the Host what interrupts we want blocked ready for using the | |
557 | * lguest_data.interrupts bitmap, so disabling (aka "masking") them is as | |
558 | * simple as setting a bit. We don't actually "ack" interrupts as such, we | |
559 | * just mask and unmask them. I wonder if we should be cleverer? | |
560 | */ | |
07ad157f RR |
561 | static void disable_lguest_irq(unsigned int irq) |
562 | { | |
563 | set_bit(irq, lguest_data.blocked_interrupts); | |
564 | } | |
565 | ||
566 | static void enable_lguest_irq(unsigned int irq) | |
567 | { | |
568 | clear_bit(irq, lguest_data.blocked_interrupts); | |
07ad157f RR |
569 | } |
570 | ||
b2b47c21 | 571 | /* This structure describes the lguest IRQ controller. */ |
07ad157f RR |
572 | static struct irq_chip lguest_irq_controller = { |
573 | .name = "lguest", | |
574 | .mask = disable_lguest_irq, | |
575 | .mask_ack = disable_lguest_irq, | |
576 | .unmask = enable_lguest_irq, | |
577 | }; | |
578 | ||
b2b47c21 RR |
579 | /* This sets up the Interrupt Descriptor Table (IDT) entry for each hardware |
580 | * interrupt (except 128, which is used for system calls), and then tells the | |
581 | * Linux infrastructure that each interrupt is controlled by our level-based | |
582 | * lguest interrupt controller. */ | |
07ad157f RR |
583 | static void __init lguest_init_IRQ(void) |
584 | { | |
585 | unsigned int i; | |
586 | ||
587 | for (i = 0; i < LGUEST_IRQS; i++) { | |
588 | int vector = FIRST_EXTERNAL_VECTOR + i; | |
526e5ab2 RR |
589 | /* Some systems map "vectors" to interrupts weirdly. Lguest has |
590 | * a straightforward 1 to 1 mapping, so force that here. */ | |
591 | __get_cpu_var(vector_irq)[vector] = i; | |
07ad157f | 592 | if (vector != SYSCALL_VECTOR) { |
4687518c PA |
593 | set_intr_gate(vector, |
594 | interrupt[vector-FIRST_EXTERNAL_VECTOR]); | |
a16ffe93 RR |
595 | set_irq_chip_and_handler_name(i, &lguest_irq_controller, |
596 | handle_level_irq, | |
597 | "level"); | |
07ad157f RR |
598 | } |
599 | } | |
b2b47c21 RR |
600 | /* This call is required to set up for 4k stacks, where we have |
601 | * separate stacks for hard and soft interrupts. */ | |
07ad157f RR |
602 | irq_ctx_init(smp_processor_id()); |
603 | } | |
604 | ||
b2b47c21 RR |
605 | /* |
606 | * Time. | |
607 | * | |
608 | * It would be far better for everyone if the Guest had its own clock, but | |
6c8dca5d | 609 | * until then the Host gives us the time on every interrupt. |
b2b47c21 | 610 | */ |
07ad157f RR |
611 | static unsigned long lguest_get_wallclock(void) |
612 | { | |
6c8dca5d | 613 | return lguest_data.time.tv_sec; |
07ad157f RR |
614 | } |
615 | ||
a6bd8e13 RR |
616 | /* The TSC is an Intel thing called the Time Stamp Counter. The Host tells us |
617 | * what speed it runs at, or 0 if it's unusable as a reliable clock source. | |
618 | * This matches what we want here: if we return 0 from this function, the x86 | |
619 | * TSC clock will give up and not register itself. */ | |
e93ef949 | 620 | static unsigned long lguest_tsc_khz(void) |
3fabc55f RR |
621 | { |
622 | return lguest_data.tsc_khz; | |
623 | } | |
624 | ||
a6bd8e13 RR |
625 | /* If we can't use the TSC, the kernel falls back to our lower-priority |
626 | * "lguest_clock", where we read the time value given to us by the Host. */ | |
d7e28ffe RR |
627 | static cycle_t lguest_clock_read(void) |
628 | { | |
6c8dca5d RR |
629 | unsigned long sec, nsec; |
630 | ||
3fabc55f RR |
631 | /* Since the time is in two parts (seconds and nanoseconds), we risk |
632 | * reading it just as it's changing from 99 & 0.999999999 to 100 and 0, | |
633 | * and getting 99 and 0. As Linux tends to come apart under the stress | |
634 | * of time travel, we must be careful: */ | |
6c8dca5d RR |
635 | do { |
636 | /* First we read the seconds part. */ | |
637 | sec = lguest_data.time.tv_sec; | |
638 | /* This read memory barrier tells the compiler and the CPU that | |
639 | * this can't be reordered: we have to complete the above | |
640 | * before going on. */ | |
641 | rmb(); | |
642 | /* Now we read the nanoseconds part. */ | |
643 | nsec = lguest_data.time.tv_nsec; | |
644 | /* Make sure we've done that. */ | |
645 | rmb(); | |
646 | /* Now if the seconds part has changed, try again. */ | |
647 | } while (unlikely(lguest_data.time.tv_sec != sec)); | |
648 | ||
3fabc55f | 649 | /* Our lguest clock is in real nanoseconds. */ |
6c8dca5d | 650 | return sec*1000000000ULL + nsec; |
d7e28ffe RR |
651 | } |
652 | ||
3fabc55f | 653 | /* This is the fallback clocksource: lower priority than the TSC clocksource. */ |
d7e28ffe RR |
654 | static struct clocksource lguest_clock = { |
655 | .name = "lguest", | |
3fabc55f | 656 | .rating = 200, |
d7e28ffe | 657 | .read = lguest_clock_read, |
6c8dca5d | 658 | .mask = CLOCKSOURCE_MASK(64), |
37250097 RR |
659 | .mult = 1 << 22, |
660 | .shift = 22, | |
05aa026a | 661 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
d7e28ffe RR |
662 | }; |
663 | ||
664 | /* We also need a "struct clock_event_device": Linux asks us to set it to go | |
665 | * off some time in the future. Actually, James Morris figured all this out, I | |
666 | * just applied the patch. */ | |
667 | static int lguest_clockevent_set_next_event(unsigned long delta, | |
668 | struct clock_event_device *evt) | |
669 | { | |
a6bd8e13 RR |
670 | /* FIXME: I don't think this can ever happen, but James tells me he had |
671 | * to put this code in. Maybe we should remove it now. Anyone? */ | |
d7e28ffe RR |
672 | if (delta < LG_CLOCK_MIN_DELTA) { |
673 | if (printk_ratelimit()) | |
674 | printk(KERN_DEBUG "%s: small delta %lu ns\n", | |
77bf90ed | 675 | __func__, delta); |
d7e28ffe RR |
676 | return -ETIME; |
677 | } | |
a6bd8e13 RR |
678 | |
679 | /* Please wake us this far in the future. */ | |
d7e28ffe RR |
680 | hcall(LHCALL_SET_CLOCKEVENT, delta, 0, 0); |
681 | return 0; | |
682 | } | |
683 | ||
684 | static void lguest_clockevent_set_mode(enum clock_event_mode mode, | |
685 | struct clock_event_device *evt) | |
686 | { | |
687 | switch (mode) { | |
688 | case CLOCK_EVT_MODE_UNUSED: | |
689 | case CLOCK_EVT_MODE_SHUTDOWN: | |
690 | /* A 0 argument shuts the clock down. */ | |
691 | hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0); | |
692 | break; | |
693 | case CLOCK_EVT_MODE_ONESHOT: | |
694 | /* This is what we expect. */ | |
695 | break; | |
696 | case CLOCK_EVT_MODE_PERIODIC: | |
697 | BUG(); | |
18de5bc4 TG |
698 | case CLOCK_EVT_MODE_RESUME: |
699 | break; | |
d7e28ffe RR |
700 | } |
701 | } | |
702 | ||
703 | /* This describes our primitive timer chip. */ | |
704 | static struct clock_event_device lguest_clockevent = { | |
705 | .name = "lguest", | |
706 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
707 | .set_next_event = lguest_clockevent_set_next_event, | |
708 | .set_mode = lguest_clockevent_set_mode, | |
709 | .rating = INT_MAX, | |
710 | .mult = 1, | |
711 | .shift = 0, | |
712 | .min_delta_ns = LG_CLOCK_MIN_DELTA, | |
713 | .max_delta_ns = LG_CLOCK_MAX_DELTA, | |
714 | }; | |
715 | ||
716 | /* This is the Guest timer interrupt handler (hardware interrupt 0). We just | |
717 | * call the clockevent infrastructure and it does whatever needs doing. */ | |
07ad157f RR |
718 | static void lguest_time_irq(unsigned int irq, struct irq_desc *desc) |
719 | { | |
d7e28ffe RR |
720 | unsigned long flags; |
721 | ||
722 | /* Don't interrupt us while this is running. */ | |
723 | local_irq_save(flags); | |
724 | lguest_clockevent.event_handler(&lguest_clockevent); | |
725 | local_irq_restore(flags); | |
07ad157f RR |
726 | } |
727 | ||
b2b47c21 RR |
728 | /* At some point in the boot process, we get asked to set up our timing |
729 | * infrastructure. The kernel doesn't expect timer interrupts before this, but | |
730 | * we cleverly initialized the "blocked_interrupts" field of "struct | |
731 | * lguest_data" so that timer interrupts were blocked until now. */ | |
07ad157f RR |
732 | static void lguest_time_init(void) |
733 | { | |
b2b47c21 | 734 | /* Set up the timer interrupt (0) to go to our simple timer routine */ |
07ad157f | 735 | set_irq_handler(0, lguest_time_irq); |
07ad157f | 736 | |
d7e28ffe RR |
737 | clocksource_register(&lguest_clock); |
738 | ||
b2b47c21 RR |
739 | /* We can't set cpumask in the initializer: damn C limitations! Set it |
740 | * here and register our timer device. */ | |
320ab2b0 | 741 | lguest_clockevent.cpumask = cpumask_of(0); |
d7e28ffe RR |
742 | clockevents_register_device(&lguest_clockevent); |
743 | ||
b2b47c21 | 744 | /* Finally, we unblock the timer interrupt. */ |
d7e28ffe | 745 | enable_lguest_irq(0); |
07ad157f RR |
746 | } |
747 | ||
b2b47c21 RR |
748 | /* |
749 | * Miscellaneous bits and pieces. | |
750 | * | |
751 | * Here is an oddball collection of functions which the Guest needs for things | |
752 | * to work. They're pretty simple. | |
753 | */ | |
754 | ||
e1e72965 | 755 | /* The Guest needs to tell the Host what stack it expects traps to use. For |
b2b47c21 RR |
756 | * native hardware, this is part of the Task State Segment mentioned above in |
757 | * lguest_load_tr_desc(), but to help hypervisors there's this special call. | |
758 | * | |
759 | * We tell the Host the segment we want to use (__KERNEL_DS is the kernel data | |
760 | * segment), the privilege level (we're privilege level 1, the Host is 0 and | |
761 | * will not tolerate us trying to use that), the stack pointer, and the number | |
762 | * of pages in the stack. */ | |
faca6227 | 763 | static void lguest_load_sp0(struct tss_struct *tss, |
a6bd8e13 | 764 | struct thread_struct *thread) |
07ad157f | 765 | { |
faca6227 | 766 | lazy_hcall(LHCALL_SET_STACK, __KERNEL_DS|0x1, thread->sp0, |
07ad157f RR |
767 | THREAD_SIZE/PAGE_SIZE); |
768 | } | |
769 | ||
b2b47c21 | 770 | /* Let's just say, I wouldn't do debugging under a Guest. */ |
07ad157f RR |
771 | static void lguest_set_debugreg(int regno, unsigned long value) |
772 | { | |
773 | /* FIXME: Implement */ | |
774 | } | |
775 | ||
b2b47c21 RR |
776 | /* There are times when the kernel wants to make sure that no memory writes are |
777 | * caught in the cache (that they've all reached real hardware devices). This | |
778 | * doesn't matter for the Guest which has virtual hardware. | |
779 | * | |
780 | * On the Pentium 4 and above, cpuid() indicates that the Cache Line Flush | |
781 | * (clflush) instruction is available and the kernel uses that. Otherwise, it | |
782 | * uses the older "Write Back and Invalidate Cache" (wbinvd) instruction. | |
783 | * Unlike clflush, wbinvd can only be run at privilege level 0. So we can | |
784 | * ignore clflush, but replace wbinvd. | |
785 | */ | |
07ad157f RR |
786 | static void lguest_wbinvd(void) |
787 | { | |
788 | } | |
789 | ||
b2b47c21 RR |
790 | /* If the Guest expects to have an Advanced Programmable Interrupt Controller, |
791 | * we play dumb by ignoring writes and returning 0 for reads. So it's no | |
792 | * longer Programmable nor Controlling anything, and I don't think 8 lines of | |
793 | * code qualifies for Advanced. It will also never interrupt anything. It | |
794 | * does, however, allow us to get through the Linux boot code. */ | |
07ad157f | 795 | #ifdef CONFIG_X86_LOCAL_APIC |
ad66dd34 | 796 | static void lguest_apic_write(u32 reg, u32 v) |
07ad157f RR |
797 | { |
798 | } | |
799 | ||
ad66dd34 | 800 | static u32 lguest_apic_read(u32 reg) |
07ad157f RR |
801 | { |
802 | return 0; | |
803 | } | |
511d9d34 SS |
804 | |
805 | static u64 lguest_apic_icr_read(void) | |
806 | { | |
807 | return 0; | |
808 | } | |
809 | ||
810 | static void lguest_apic_icr_write(u32 low, u32 id) | |
811 | { | |
812 | /* Warn to see if there's any stray references */ | |
813 | WARN_ON(1); | |
814 | } | |
815 | ||
816 | static void lguest_apic_wait_icr_idle(void) | |
817 | { | |
818 | return; | |
819 | } | |
820 | ||
821 | static u32 lguest_apic_safe_wait_icr_idle(void) | |
822 | { | |
823 | return 0; | |
824 | } | |
825 | ||
826 | static struct apic_ops lguest_basic_apic_ops = { | |
827 | .read = lguest_apic_read, | |
828 | .write = lguest_apic_write, | |
511d9d34 SS |
829 | .icr_read = lguest_apic_icr_read, |
830 | .icr_write = lguest_apic_icr_write, | |
831 | .wait_icr_idle = lguest_apic_wait_icr_idle, | |
832 | .safe_wait_icr_idle = lguest_apic_safe_wait_icr_idle, | |
833 | }; | |
07ad157f RR |
834 | #endif |
835 | ||
b2b47c21 | 836 | /* STOP! Until an interrupt comes in. */ |
07ad157f RR |
837 | static void lguest_safe_halt(void) |
838 | { | |
839 | hcall(LHCALL_HALT, 0, 0, 0); | |
840 | } | |
841 | ||
a6bd8e13 RR |
842 | /* The SHUTDOWN hypercall takes a string to describe what's happening, and |
843 | * an argument which says whether this to restart (reboot) the Guest or not. | |
b2b47c21 RR |
844 | * |
845 | * Note that the Host always prefers that the Guest speak in physical addresses | |
846 | * rather than virtual addresses, so we use __pa() here. */ | |
07ad157f RR |
847 | static void lguest_power_off(void) |
848 | { | |
ec04b13f | 849 | hcall(LHCALL_SHUTDOWN, __pa("Power down"), LGUEST_SHUTDOWN_POWEROFF, 0); |
07ad157f RR |
850 | } |
851 | ||
b2b47c21 RR |
852 | /* |
853 | * Panicing. | |
854 | * | |
855 | * Don't. But if you did, this is what happens. | |
856 | */ | |
07ad157f RR |
857 | static int lguest_panic(struct notifier_block *nb, unsigned long l, void *p) |
858 | { | |
ec04b13f | 859 | hcall(LHCALL_SHUTDOWN, __pa(p), LGUEST_SHUTDOWN_POWEROFF, 0); |
b2b47c21 | 860 | /* The hcall won't return, but to keep gcc happy, we're "done". */ |
07ad157f RR |
861 | return NOTIFY_DONE; |
862 | } | |
863 | ||
864 | static struct notifier_block paniced = { | |
865 | .notifier_call = lguest_panic | |
866 | }; | |
867 | ||
b2b47c21 | 868 | /* Setting up memory is fairly easy. */ |
07ad157f RR |
869 | static __init char *lguest_memory_setup(void) |
870 | { | |
a6bd8e13 RR |
871 | /* We do this here and not earlier because lockcheck used to barf if we |
872 | * did it before start_kernel(). I think we fixed that, so it'd be | |
873 | * nice to move it back to lguest_init. Patch welcome... */ | |
07ad157f RR |
874 | atomic_notifier_chain_register(&panic_notifier_list, &paniced); |
875 | ||
b2b47c21 RR |
876 | /* The Linux bootloader header contains an "e820" memory map: the |
877 | * Launcher populated the first entry with our memory limit. */ | |
d0be6bde | 878 | e820_add_region(boot_params.e820_map[0].addr, |
30c82645 PA |
879 | boot_params.e820_map[0].size, |
880 | boot_params.e820_map[0].type); | |
b2b47c21 RR |
881 | |
882 | /* This string is for the boot messages. */ | |
07ad157f RR |
883 | return "LGUEST"; |
884 | } | |
885 | ||
e1e72965 RR |
886 | /* We will eventually use the virtio console device to produce console output, |
887 | * but before that is set up we use LHCALL_NOTIFY on normal memory to produce | |
888 | * console output. */ | |
19f1537b RR |
889 | static __init int early_put_chars(u32 vtermno, const char *buf, int count) |
890 | { | |
891 | char scratch[17]; | |
892 | unsigned int len = count; | |
893 | ||
e1e72965 RR |
894 | /* We use a nul-terminated string, so we have to make a copy. Icky, |
895 | * huh? */ | |
19f1537b RR |
896 | if (len > sizeof(scratch) - 1) |
897 | len = sizeof(scratch) - 1; | |
898 | scratch[len] = '\0'; | |
899 | memcpy(scratch, buf, len); | |
900 | hcall(LHCALL_NOTIFY, __pa(scratch), 0, 0); | |
901 | ||
902 | /* This routine returns the number of bytes actually written. */ | |
903 | return len; | |
904 | } | |
905 | ||
a6bd8e13 RR |
906 | /* Rebooting also tells the Host we're finished, but the RESTART flag tells the |
907 | * Launcher to reboot us. */ | |
908 | static void lguest_restart(char *reason) | |
909 | { | |
910 | hcall(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART, 0); | |
911 | } | |
912 | ||
b2b47c21 RR |
913 | /*G:050 |
914 | * Patching (Powerfully Placating Performance Pedants) | |
915 | * | |
a6bd8e13 RR |
916 | * We have already seen that pv_ops structures let us replace simple native |
917 | * instructions with calls to the appropriate back end all throughout the | |
918 | * kernel. This allows the same kernel to run as a Guest and as a native | |
b2b47c21 RR |
919 | * kernel, but it's slow because of all the indirect branches. |
920 | * | |
921 | * Remember that David Wheeler quote about "Any problem in computer science can | |
922 | * be solved with another layer of indirection"? The rest of that quote is | |
923 | * "... But that usually will create another problem." This is the first of | |
924 | * those problems. | |
925 | * | |
926 | * Our current solution is to allow the paravirt back end to optionally patch | |
927 | * over the indirect calls to replace them with something more efficient. We | |
928 | * patch the four most commonly called functions: disable interrupts, enable | |
e1e72965 | 929 | * interrupts, restore interrupts and save interrupts. We usually have 6 or 10 |
b2b47c21 RR |
930 | * bytes to patch into: the Guest versions of these operations are small enough |
931 | * that we can fit comfortably. | |
932 | * | |
933 | * First we need assembly templates of each of the patchable Guest operations, | |
72410af9 | 934 | * and these are in i386_head.S. */ |
b2b47c21 RR |
935 | |
936 | /*G:060 We construct a table from the assembler templates: */ | |
07ad157f RR |
937 | static const struct lguest_insns |
938 | { | |
939 | const char *start, *end; | |
940 | } lguest_insns[] = { | |
93b1eab3 JF |
941 | [PARAVIRT_PATCH(pv_irq_ops.irq_disable)] = { lgstart_cli, lgend_cli }, |
942 | [PARAVIRT_PATCH(pv_irq_ops.irq_enable)] = { lgstart_sti, lgend_sti }, | |
943 | [PARAVIRT_PATCH(pv_irq_ops.restore_fl)] = { lgstart_popf, lgend_popf }, | |
944 | [PARAVIRT_PATCH(pv_irq_ops.save_fl)] = { lgstart_pushf, lgend_pushf }, | |
07ad157f | 945 | }; |
b2b47c21 RR |
946 | |
947 | /* Now our patch routine is fairly simple (based on the native one in | |
948 | * paravirt.c). If we have a replacement, we copy it in and return how much of | |
949 | * the available space we used. */ | |
ab144f5e AK |
950 | static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf, |
951 | unsigned long addr, unsigned len) | |
07ad157f RR |
952 | { |
953 | unsigned int insn_len; | |
954 | ||
b2b47c21 | 955 | /* Don't do anything special if we don't have a replacement */ |
07ad157f | 956 | if (type >= ARRAY_SIZE(lguest_insns) || !lguest_insns[type].start) |
ab144f5e | 957 | return paravirt_patch_default(type, clobber, ibuf, addr, len); |
07ad157f RR |
958 | |
959 | insn_len = lguest_insns[type].end - lguest_insns[type].start; | |
960 | ||
b2b47c21 RR |
961 | /* Similarly if we can't fit replacement (shouldn't happen, but let's |
962 | * be thorough). */ | |
07ad157f | 963 | if (len < insn_len) |
ab144f5e | 964 | return paravirt_patch_default(type, clobber, ibuf, addr, len); |
07ad157f | 965 | |
b2b47c21 | 966 | /* Copy in our instructions. */ |
ab144f5e | 967 | memcpy(ibuf, lguest_insns[type].start, insn_len); |
07ad157f RR |
968 | return insn_len; |
969 | } | |
970 | ||
a6bd8e13 RR |
971 | /*G:030 Once we get to lguest_init(), we know we're a Guest. The various |
972 | * pv_ops structures in the kernel provide points for (almost) every routine we | |
973 | * have to override to avoid privileged instructions. */ | |
814a0e5c | 974 | __init void lguest_init(void) |
07ad157f | 975 | { |
b2b47c21 RR |
976 | /* We're under lguest, paravirt is enabled, and we're running at |
977 | * privilege level 1, not 0 as normal. */ | |
93b1eab3 JF |
978 | pv_info.name = "lguest"; |
979 | pv_info.paravirt_enabled = 1; | |
980 | pv_info.kernel_rpl = 1; | |
07ad157f | 981 | |
b2b47c21 RR |
982 | /* We set up all the lguest overrides for sensitive operations. These |
983 | * are detailed with the operations themselves. */ | |
93b1eab3 JF |
984 | |
985 | /* interrupt-related operations */ | |
986 | pv_irq_ops.init_IRQ = lguest_init_IRQ; | |
987 | pv_irq_ops.save_fl = save_fl; | |
988 | pv_irq_ops.restore_fl = restore_fl; | |
989 | pv_irq_ops.irq_disable = irq_disable; | |
990 | pv_irq_ops.irq_enable = irq_enable; | |
991 | pv_irq_ops.safe_halt = lguest_safe_halt; | |
992 | ||
993 | /* init-time operations */ | |
994 | pv_init_ops.memory_setup = lguest_memory_setup; | |
995 | pv_init_ops.patch = lguest_patch; | |
996 | ||
997 | /* Intercepts of various cpu instructions */ | |
998 | pv_cpu_ops.load_gdt = lguest_load_gdt; | |
999 | pv_cpu_ops.cpuid = lguest_cpuid; | |
1000 | pv_cpu_ops.load_idt = lguest_load_idt; | |
1001 | pv_cpu_ops.iret = lguest_iret; | |
faca6227 | 1002 | pv_cpu_ops.load_sp0 = lguest_load_sp0; |
93b1eab3 JF |
1003 | pv_cpu_ops.load_tr_desc = lguest_load_tr_desc; |
1004 | pv_cpu_ops.set_ldt = lguest_set_ldt; | |
1005 | pv_cpu_ops.load_tls = lguest_load_tls; | |
1006 | pv_cpu_ops.set_debugreg = lguest_set_debugreg; | |
1007 | pv_cpu_ops.clts = lguest_clts; | |
1008 | pv_cpu_ops.read_cr0 = lguest_read_cr0; | |
1009 | pv_cpu_ops.write_cr0 = lguest_write_cr0; | |
1010 | pv_cpu_ops.read_cr4 = lguest_read_cr4; | |
1011 | pv_cpu_ops.write_cr4 = lguest_write_cr4; | |
1012 | pv_cpu_ops.write_gdt_entry = lguest_write_gdt_entry; | |
1013 | pv_cpu_ops.write_idt_entry = lguest_write_idt_entry; | |
1014 | pv_cpu_ops.wbinvd = lguest_wbinvd; | |
8965c1c0 JF |
1015 | pv_cpu_ops.lazy_mode.enter = paravirt_enter_lazy_cpu; |
1016 | pv_cpu_ops.lazy_mode.leave = lguest_leave_lazy_mode; | |
93b1eab3 JF |
1017 | |
1018 | /* pagetable management */ | |
1019 | pv_mmu_ops.write_cr3 = lguest_write_cr3; | |
1020 | pv_mmu_ops.flush_tlb_user = lguest_flush_tlb_user; | |
1021 | pv_mmu_ops.flush_tlb_single = lguest_flush_tlb_single; | |
1022 | pv_mmu_ops.flush_tlb_kernel = lguest_flush_tlb_kernel; | |
1023 | pv_mmu_ops.set_pte = lguest_set_pte; | |
1024 | pv_mmu_ops.set_pte_at = lguest_set_pte_at; | |
1025 | pv_mmu_ops.set_pmd = lguest_set_pmd; | |
1026 | pv_mmu_ops.read_cr2 = lguest_read_cr2; | |
1027 | pv_mmu_ops.read_cr3 = lguest_read_cr3; | |
8965c1c0 JF |
1028 | pv_mmu_ops.lazy_mode.enter = paravirt_enter_lazy_mmu; |
1029 | pv_mmu_ops.lazy_mode.leave = lguest_leave_lazy_mode; | |
93b1eab3 | 1030 | |
07ad157f | 1031 | #ifdef CONFIG_X86_LOCAL_APIC |
93b1eab3 | 1032 | /* apic read/write intercepts */ |
511d9d34 | 1033 | apic_ops = &lguest_basic_apic_ops; |
07ad157f | 1034 | #endif |
93b1eab3 JF |
1035 | |
1036 | /* time operations */ | |
1037 | pv_time_ops.get_wallclock = lguest_get_wallclock; | |
1038 | pv_time_ops.time_init = lguest_time_init; | |
e93ef949 | 1039 | pv_time_ops.get_tsc_khz = lguest_tsc_khz; |
93b1eab3 | 1040 | |
b2b47c21 RR |
1041 | /* Now is a good time to look at the implementations of these functions |
1042 | * before returning to the rest of lguest_init(). */ | |
1043 | ||
1044 | /*G:070 Now we've seen all the paravirt_ops, we return to | |
1045 | * lguest_init() where the rest of the fairly chaotic boot setup | |
47436aa4 | 1046 | * occurs. */ |
07ad157f | 1047 | |
b2b47c21 RR |
1048 | /* The native boot code sets up initial page tables immediately after |
1049 | * the kernel itself, and sets init_pg_tables_end so they're not | |
1050 | * clobbered. The Launcher places our initial pagetables somewhere at | |
1051 | * the top of our physical memory, so we don't need extra space: set | |
1052 | * init_pg_tables_end to the end of the kernel. */ | |
f0d43100 | 1053 | init_pg_tables_start = __pa(pg0); |
07ad157f RR |
1054 | init_pg_tables_end = __pa(pg0); |
1055 | ||
5d006d8d RR |
1056 | /* As described in head_32.S, we map the first 128M of memory. */ |
1057 | max_pfn_mapped = (128*1024*1024) >> PAGE_SHIFT; | |
1058 | ||
b2b47c21 RR |
1059 | /* Load the %fs segment register (the per-cpu segment register) with |
1060 | * the normal data segment to get through booting. */ | |
07ad157f RR |
1061 | asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_DS) : "memory"); |
1062 | ||
a6bd8e13 RR |
1063 | /* The Host<->Guest Switcher lives at the top of our address space, and |
1064 | * the Host told us how big it is when we made LGUEST_INIT hypercall: | |
1065 | * it put the answer in lguest_data.reserve_mem */ | |
07ad157f RR |
1066 | reserve_top_address(lguest_data.reserve_mem); |
1067 | ||
b2b47c21 RR |
1068 | /* If we don't initialize the lock dependency checker now, it crashes |
1069 | * paravirt_disable_iospace. */ | |
07ad157f RR |
1070 | lockdep_init(); |
1071 | ||
b2b47c21 RR |
1072 | /* The IDE code spends about 3 seconds probing for disks: if we reserve |
1073 | * all the I/O ports up front it can't get them and so doesn't probe. | |
1074 | * Other device drivers are similar (but less severe). This cuts the | |
1075 | * kernel boot time on my machine from 4.1 seconds to 0.45 seconds. */ | |
07ad157f RR |
1076 | paravirt_disable_iospace(); |
1077 | ||
b2b47c21 RR |
1078 | /* This is messy CPU setup stuff which the native boot code does before |
1079 | * start_kernel, so we have to do, too: */ | |
07ad157f RR |
1080 | cpu_detect(&new_cpu_data); |
1081 | /* head.S usually sets up the first capability word, so do it here. */ | |
1082 | new_cpu_data.x86_capability[0] = cpuid_edx(1); | |
1083 | ||
1084 | /* Math is always hard! */ | |
1085 | new_cpu_data.hard_math = 1; | |
1086 | ||
a6bd8e13 | 1087 | /* We don't have features. We have puppies! Puppies! */ |
07ad157f RR |
1088 | #ifdef CONFIG_X86_MCE |
1089 | mce_disabled = 1; | |
1090 | #endif | |
07ad157f RR |
1091 | #ifdef CONFIG_ACPI |
1092 | acpi_disabled = 1; | |
1093 | acpi_ht = 0; | |
1094 | #endif | |
1095 | ||
72410af9 | 1096 | /* We set the preferred console to "hvc". This is the "hypervisor |
b2b47c21 RR |
1097 | * virtual console" driver written by the PowerPC people, which we also |
1098 | * adapted for lguest's use. */ | |
07ad157f RR |
1099 | add_preferred_console("hvc", 0, NULL); |
1100 | ||
19f1537b RR |
1101 | /* Register our very early console. */ |
1102 | virtio_cons_early_init(early_put_chars); | |
1103 | ||
b2b47c21 | 1104 | /* Last of all, we set the power management poweroff hook to point to |
a6bd8e13 RR |
1105 | * the Guest routine to power off, and the reboot hook to our restart |
1106 | * routine. */ | |
07ad157f | 1107 | pm_power_off = lguest_power_off; |
ec04b13f | 1108 | machine_ops.restart = lguest_restart; |
a6bd8e13 | 1109 | |
f0d43100 | 1110 | /* Now we're set up, call i386_start_kernel() in head32.c and we proceed |
b2b47c21 | 1111 | * to boot as normal. It never returns. */ |
f0d43100 | 1112 | i386_start_kernel(); |
07ad157f | 1113 | } |
b2b47c21 RR |
1114 | /* |
1115 | * This marks the end of stage II of our journey, The Guest. | |
1116 | * | |
e1e72965 RR |
1117 | * It is now time for us to explore the layer of virtual drivers and complete |
1118 | * our understanding of the Guest in "make Drivers". | |
b2b47c21 | 1119 | */ |