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37448f7d ES |
1 | /* |
2 | * drivers/net/ibm_emac/ibm_emac_mal.h | |
3 | * | |
4 | * Memory Access Layer (MAL) support | |
5 | * | |
6 | * Copyright (c) 2004, 2005 Zultys Technologies. | |
7 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | |
8 | * | |
9 | * Based on original work by | |
10 | * Armin Kuster <akuster@mvista.com> | |
11 | * Copyright 2002 MontaVista Softare Inc. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | * | |
18 | */ | |
19 | #ifndef __IBM_EMAC_MAL_H_ | |
20 | #define __IBM_EMAC_MAL_H_ | |
1da177e4 | 21 | |
37448f7d | 22 | #include <linux/init.h> |
1da177e4 | 23 | #include <linux/list.h> |
37448f7d | 24 | #include <linux/netdevice.h> |
1da177e4 | 25 | |
37448f7d | 26 | #include <asm/io.h> |
1be3770a | 27 | #include <asm/dcr.h> |
1da177e4 | 28 | |
37448f7d ES |
29 | /* |
30 | * These MAL "versions" probably aren't the real versions IBM uses for these | |
31 | * MAL cores, I assigned them just to make #ifdefs in this file nicer and | |
32 | * reflect the fact that 40x and 44x have slightly different MALs. --ebs | |
33 | */ | |
34 | #if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \ | |
1b195916 | 35 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H) |
37448f7d | 36 | #define MAL_VERSION 1 |
7ad8a89c ES |
37 | #elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ |
38 | defined(CONFIG_440SPE) | |
37448f7d ES |
39 | #define MAL_VERSION 2 |
40 | #else | |
41 | #error "Unknown SoC, please check chip manual and choose MAL 'version'" | |
42 | #endif | |
43 | ||
44 | /* MALx DCR registers */ | |
45 | #define MAL_CFG 0x00 | |
46 | #define MAL_CFG_SR 0x80000000 | |
47 | #define MAL_CFG_PLBB 0x00004000 | |
48 | #define MAL_CFG_OPBBL 0x00000080 | |
49 | #define MAL_CFG_EOPIE 0x00000004 | |
50 | #define MAL_CFG_LEA 0x00000002 | |
51 | #define MAL_CFG_SD 0x00000001 | |
52 | #if MAL_VERSION == 1 | |
53 | #define MAL_CFG_PLBP_MASK 0x00c00000 | |
54 | #define MAL_CFG_PLBP_10 0x00800000 | |
55 | #define MAL_CFG_GA 0x00200000 | |
56 | #define MAL_CFG_OA 0x00100000 | |
57 | #define MAL_CFG_PLBLE 0x00080000 | |
58 | #define MAL_CFG_PLBT_MASK 0x00078000 | |
59 | #define MAL_CFG_DEFAULT (MAL_CFG_PLBP_10 | MAL_CFG_PLBT_MASK) | |
60 | #elif MAL_VERSION == 2 | |
61 | #define MAL_CFG_RPP_MASK 0x00c00000 | |
62 | #define MAL_CFG_RPP_10 0x00800000 | |
63 | #define MAL_CFG_RMBS_MASK 0x00300000 | |
64 | #define MAL_CFG_WPP_MASK 0x000c0000 | |
65 | #define MAL_CFG_WPP_10 0x00080000 | |
66 | #define MAL_CFG_WMBS_MASK 0x00030000 | |
67 | #define MAL_CFG_PLBLE 0x00008000 | |
68 | #define MAL_CFG_DEFAULT (MAL_CFG_RMBS_MASK | MAL_CFG_WMBS_MASK | \ | |
69 | MAL_CFG_RPP_10 | MAL_CFG_WPP_10) | |
70 | #else | |
71 | #error "Unknown MAL version" | |
72 | #endif | |
73 | ||
74 | #define MAL_ESR 0x01 | |
75 | #define MAL_ESR_EVB 0x80000000 | |
76 | #define MAL_ESR_CIDT 0x40000000 | |
77 | #define MAL_ESR_CID_MASK 0x3e000000 | |
78 | #define MAL_ESR_CID_SHIFT 25 | |
79 | #define MAL_ESR_DE 0x00100000 | |
80 | #define MAL_ESR_OTE 0x00040000 | |
81 | #define MAL_ESR_OSE 0x00020000 | |
82 | #define MAL_ESR_PEIN 0x00010000 | |
83 | #define MAL_ESR_DEI 0x00000010 | |
84 | #define MAL_ESR_OTEI 0x00000004 | |
85 | #define MAL_ESR_OSEI 0x00000002 | |
86 | #define MAL_ESR_PBEI 0x00000001 | |
87 | #if MAL_VERSION == 1 | |
88 | #define MAL_ESR_ONE 0x00080000 | |
89 | #define MAL_ESR_ONEI 0x00000008 | |
90 | #elif MAL_VERSION == 2 | |
91 | #define MAL_ESR_PTE 0x00800000 | |
92 | #define MAL_ESR_PRE 0x00400000 | |
93 | #define MAL_ESR_PWE 0x00200000 | |
94 | #define MAL_ESR_PTEI 0x00000080 | |
95 | #define MAL_ESR_PREI 0x00000040 | |
96 | #define MAL_ESR_PWEI 0x00000020 | |
97 | #else | |
98 | #error "Unknown MAL version" | |
99 | #endif | |
100 | ||
101 | #define MAL_IER 0x02 | |
102 | #define MAL_IER_DE 0x00000010 | |
103 | #define MAL_IER_OTE 0x00000004 | |
104 | #define MAL_IER_OE 0x00000002 | |
105 | #define MAL_IER_PE 0x00000001 | |
106 | #if MAL_VERSION == 1 | |
107 | #define MAL_IER_NWE 0x00000008 | |
108 | #define MAL_IER_SOC_EVENTS MAL_IER_NWE | |
109 | #elif MAL_VERSION == 2 | |
110 | #define MAL_IER_PT 0x00000080 | |
111 | #define MAL_IER_PRE 0x00000040 | |
112 | #define MAL_IER_PWE 0x00000020 | |
113 | #define MAL_IER_SOC_EVENTS (MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE) | |
114 | #else | |
115 | #error "Unknown MAL version" | |
116 | #endif | |
117 | #define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_OTE | \ | |
118 | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE) | |
119 | ||
120 | #define MAL_TXCASR 0x04 | |
121 | #define MAL_TXCARR 0x05 | |
122 | #define MAL_TXEOBISR 0x06 | |
123 | #define MAL_TXDEIR 0x07 | |
124 | #define MAL_RXCASR 0x10 | |
125 | #define MAL_RXCARR 0x11 | |
126 | #define MAL_RXEOBISR 0x12 | |
127 | #define MAL_RXDEIR 0x13 | |
128 | #define MAL_TXCTPR(n) ((n) + 0x20) | |
129 | #define MAL_RXCTPR(n) ((n) + 0x40) | |
130 | #define MAL_RCBS(n) ((n) + 0x60) | |
131 | ||
132 | /* In reality MAL can handle TX buffers up to 4095 bytes long, | |
133 | * but this isn't a good round number :) --ebs | |
134 | */ | |
135 | #define MAL_MAX_TX_SIZE 4080 | |
136 | #define MAL_MAX_RX_SIZE 4080 | |
137 | ||
138 | static inline int mal_rx_size(int len) | |
139 | { | |
140 | len = (len + 0xf) & ~0xf; | |
141 | return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len; | |
142 | } | |
143 | ||
144 | static inline int mal_tx_chunks(int len) | |
145 | { | |
146 | return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE; | |
147 | } | |
148 | ||
149 | #define MAL_CHAN_MASK(n) (0x80000000 >> (n)) | |
1da177e4 LT |
150 | |
151 | /* MAL Buffer Descriptor structure */ | |
152 | struct mal_descriptor { | |
37448f7d ES |
153 | u16 ctrl; /* MAL / Commac status control bits */ |
154 | u16 data_len; /* Max length is 4K-1 (12 bits) */ | |
155 | u32 data_ptr; /* pointer to actual data buffer */ | |
156 | }; | |
1da177e4 LT |
157 | |
158 | /* the following defines are for the MadMAL status and control registers. */ | |
159 | /* MADMAL transmit and receive status/control bits */ | |
37448f7d ES |
160 | #define MAL_RX_CTRL_EMPTY 0x8000 |
161 | #define MAL_RX_CTRL_WRAP 0x4000 | |
162 | #define MAL_RX_CTRL_CM 0x2000 | |
163 | #define MAL_RX_CTRL_LAST 0x1000 | |
164 | #define MAL_RX_CTRL_FIRST 0x0800 | |
165 | #define MAL_RX_CTRL_INTR 0x0400 | |
166 | #define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST) | |
167 | #define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE) | |
168 | ||
169 | #define MAL_TX_CTRL_READY 0x8000 | |
170 | #define MAL_TX_CTRL_WRAP 0x4000 | |
171 | #define MAL_TX_CTRL_CM 0x2000 | |
172 | #define MAL_TX_CTRL_LAST 0x1000 | |
173 | #define MAL_TX_CTRL_INTR 0x0400 | |
1da177e4 LT |
174 | |
175 | struct mal_commac_ops { | |
37448f7d ES |
176 | void (*poll_tx) (void *dev); |
177 | int (*poll_rx) (void *dev, int budget); | |
178 | int (*peek_rx) (void *dev); | |
179 | void (*rxde) (void *dev); | |
1da177e4 LT |
180 | }; |
181 | ||
182 | struct mal_commac { | |
37448f7d ES |
183 | struct mal_commac_ops *ops; |
184 | void *dev; | |
185 | struct list_head poll_list; | |
186 | int rx_stopped; | |
187 | ||
188 | u32 tx_chan_mask; | |
189 | u32 rx_chan_mask; | |
190 | struct list_head list; | |
1da177e4 LT |
191 | }; |
192 | ||
193 | struct ibm_ocp_mal { | |
1be3770a | 194 | dcr_host_t dcrhost; |
1da177e4 | 195 | |
37448f7d | 196 | struct list_head poll_list; |
bfe13f54 | 197 | struct napi_struct napi; |
1da177e4 | 198 | |
37448f7d ES |
199 | struct list_head list; |
200 | u32 tx_chan_mask; | |
201 | u32 rx_chan_mask; | |
1da177e4 | 202 | |
37448f7d ES |
203 | dma_addr_t bd_dma; |
204 | struct mal_descriptor *bd_virt; | |
1da177e4 | 205 | |
37448f7d ES |
206 | struct ocp_def *def; |
207 | }; | |
1da177e4 | 208 | |
37448f7d | 209 | static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg) |
1da177e4 | 210 | { |
83f34df4 | 211 | return dcr_read(mal->dcrhost, reg); |
1da177e4 LT |
212 | } |
213 | ||
37448f7d | 214 | static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val) |
1da177e4 | 215 | { |
83f34df4 | 216 | dcr_write(mal->dcrhost, reg, val); |
1da177e4 LT |
217 | } |
218 | ||
37448f7d ES |
219 | /* Register MAL devices */ |
220 | int mal_init(void) __init; | |
221 | void mal_exit(void) __exit; | |
1da177e4 | 222 | |
37448f7d ES |
223 | int mal_register_commac(struct ibm_ocp_mal *mal, |
224 | struct mal_commac *commac) __init; | |
0ec6d950 | 225 | void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac); |
37448f7d ES |
226 | int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size); |
227 | ||
228 | /* Returns BD ring offset for a particular channel | |
229 | (in 'struct mal_descriptor' elements) | |
230 | */ | |
231 | int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel); | |
232 | int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel); | |
233 | ||
234 | void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel); | |
235 | void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel); | |
236 | void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel); | |
237 | void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel); | |
1da177e4 | 238 | |
37448f7d ES |
239 | /* Add/remove EMAC to/from MAL polling list */ |
240 | void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac); | |
241 | void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac); | |
242 | ||
243 | /* Ethtool MAL registers */ | |
244 | struct ibm_mal_regs { | |
245 | u32 tx_count; | |
246 | u32 rx_count; | |
247 | ||
248 | u32 cfg; | |
249 | u32 esr; | |
250 | u32 ier; | |
251 | u32 tx_casr; | |
252 | u32 tx_carr; | |
253 | u32 tx_eobisr; | |
254 | u32 tx_deir; | |
255 | u32 rx_casr; | |
256 | u32 rx_carr; | |
257 | u32 rx_eobisr; | |
258 | u32 rx_deir; | |
259 | u32 tx_ctpr[32]; | |
260 | u32 rx_ctpr[32]; | |
261 | u32 rcbs[32]; | |
262 | }; | |
1da177e4 | 263 | |
37448f7d ES |
264 | int mal_get_regs_len(struct ibm_ocp_mal *mal); |
265 | void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf); | |
1da177e4 | 266 | |
37448f7d | 267 | #endif /* __IBM_EMAC_MAL_H_ */ |