Commit | Line | Data |
---|---|---|
47964174 IY |
1 | /* |
2 | * Dave DNET Ethernet Controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef _DNET_H | |
11 | #define _DNET_H | |
12 | ||
13 | #define DRV_NAME "dnet" | |
14 | #define DRV_VERSION "0.9.1" | |
15 | #define PFX DRV_NAME ": " | |
16 | ||
17 | /* Register access macros */ | |
18 | #define dnet_writel(port, value, reg) \ | |
19 | writel((value), (port)->regs + DNET_##reg) | |
20 | #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg) | |
21 | ||
22 | /* ALL DNET FIFO REGISTERS */ | |
23 | #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */ | |
24 | #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */ | |
25 | #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */ | |
26 | #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */ | |
27 | ||
28 | /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */ | |
29 | #define DNET_VERCAPS 0x100 /* VERCAPS */ | |
30 | #define DNET_INTR_SRC 0x104 /* INTR_SRC */ | |
31 | #define DNET_INTR_ENB 0x108 /* INTR_ENB */ | |
32 | #define DNET_RX_STATUS 0x10C /* RX_STATUS */ | |
33 | #define DNET_TX_STATUS 0x110 /* TX_STATUS */ | |
34 | #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */ | |
35 | #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */ | |
36 | #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */ | |
37 | #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */ | |
38 | #define DNET_SYS_CTL 0x124 /* SYS_CTL */ | |
39 | #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */ | |
40 | #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */ | |
41 | #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */ | |
42 | ||
43 | /* ALL DNET MAC REGISTERS */ | |
44 | #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */ | |
45 | #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */ | |
46 | ||
47 | /* ALL DNET RX STATISTICS COUNTERS */ | |
48 | #define DNET_RX_PKT_IGNR_CNT 0x300 | |
49 | #define DNET_RX_LEN_CHK_ERR_CNT 0x304 | |
50 | #define DNET_RX_LNG_FRM_CNT 0x308 | |
51 | #define DNET_RX_SHRT_FRM_CNT 0x30C | |
52 | #define DNET_RX_IPG_VIOL_CNT 0x310 | |
53 | #define DNET_RX_CRC_ERR_CNT 0x314 | |
54 | #define DNET_RX_OK_PKT_CNT 0x318 | |
55 | #define DNET_RX_CTL_FRM_CNT 0x31C | |
56 | #define DNET_RX_PAUSE_FRM_CNT 0x320 | |
57 | #define DNET_RX_MULTICAST_CNT 0x324 | |
58 | #define DNET_RX_BROADCAST_CNT 0x328 | |
59 | #define DNET_RX_VLAN_TAG_CNT 0x32C | |
60 | #define DNET_RX_PRE_SHRINK_CNT 0x330 | |
61 | #define DNET_RX_DRIB_NIB_CNT 0x334 | |
62 | #define DNET_RX_UNSUP_OPCD_CNT 0x338 | |
63 | #define DNET_RX_BYTE_CNT 0x33C | |
64 | ||
65 | /* DNET TX STATISTICS COUNTERS */ | |
66 | #define DNET_TX_UNICAST_CNT 0x400 | |
67 | #define DNET_TX_PAUSE_FRM_CNT 0x404 | |
68 | #define DNET_TX_MULTICAST_CNT 0x408 | |
69 | #define DNET_TX_BRDCAST_CNT 0x40C | |
70 | #define DNET_TX_VLAN_TAG_CNT 0x410 | |
71 | #define DNET_TX_BAD_FCS_CNT 0x414 | |
72 | #define DNET_TX_JUMBO_CNT 0x418 | |
73 | #define DNET_TX_BYTE_CNT 0x41C | |
74 | ||
75 | /* SOME INTERNAL MAC-CORE REGISTER */ | |
76 | #define DNET_INTERNAL_MODE_REG 0x0 | |
77 | #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 | |
78 | #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 | |
79 | #define DNET_INTERNAL_IGP_REG 0x8 | |
80 | #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa | |
81 | #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc | |
82 | #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe | |
83 | #define DNET_INTERNAL_TX_RX_STS_REG 0x12 | |
84 | #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 | |
85 | #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 | |
86 | ||
87 | #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) | |
88 | ||
89 | #define DNET_INTERNAL_WRITE (1 << 31) | |
90 | ||
91 | /* MAC-CORE REGISTER FIELDS */ | |
92 | ||
93 | /* MAC-CORE MODE REGISTER FIELDS */ | |
94 | #define DNET_INTERNAL_MODE_GBITEN (1 << 0) | |
95 | #define DNET_INTERNAL_MODE_FCEN (1 << 1) | |
96 | #define DNET_INTERNAL_MODE_RXEN (1 << 2) | |
97 | #define DNET_INTERNAL_MODE_TXEN (1 << 3) | |
98 | ||
99 | /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ | |
100 | #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) | |
101 | #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) | |
102 | #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) | |
103 | #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) | |
104 | #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) | |
105 | #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) | |
106 | #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) | |
107 | #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) | |
108 | #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) | |
109 | ||
110 | /* SYSTEM CONTROL REGISTER FIELDS */ | |
111 | #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) | |
112 | #define DNET_SYS_CTL_SENDPAUSE (1 << 2) | |
113 | #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) | |
114 | #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) | |
115 | ||
116 | /* TX STATUS REGISTER FIELDS */ | |
117 | #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) | |
118 | #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) | |
119 | ||
120 | /* INTERRUPT SOURCE REGISTER FIELDS */ | |
121 | #define DNET_INTR_SRC_TX_PKTSENT (1 << 0) | |
122 | #define DNET_INTR_SRC_TX_FIFOAF (1 << 1) | |
123 | #define DNET_INTR_SRC_TX_FIFOAE (1 << 2) | |
124 | #define DNET_INTR_SRC_TX_DISCFRM (1 << 3) | |
125 | #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) | |
126 | #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) | |
127 | #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) | |
128 | #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) | |
129 | #define DNET_INTR_SRC_TX_SUMMARY (1 << 16) | |
130 | #define DNET_INTR_SRC_RX_SUMMARY (1 << 17) | |
131 | #define DNET_INTR_SRC_PHY (1 << 19) | |
132 | ||
133 | /* INTERRUPT ENABLE REGISTER FIELDS */ | |
134 | #define DNET_INTR_ENB_TX_PKTSENT (1 << 0) | |
135 | #define DNET_INTR_ENB_TX_FIFOAF (1 << 1) | |
136 | #define DNET_INTR_ENB_TX_FIFOAE (1 << 2) | |
137 | #define DNET_INTR_ENB_TX_DISCFRM (1 << 3) | |
138 | #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) | |
139 | #define DNET_INTR_ENB_RX_PKTRDY (1 << 8) | |
140 | #define DNET_INTR_ENB_RX_FIFOAF (1 << 9) | |
141 | #define DNET_INTR_ENB_RX_FIFOERR (1 << 10) | |
142 | #define DNET_INTR_ENB_RX_ERROR (1 << 11) | |
143 | #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) | |
144 | #define DNET_INTR_ENB_RX_FIFOAE (1 << 13) | |
145 | #define DNET_INTR_ENB_TX_SUMMARY (1 << 16) | |
146 | #define DNET_INTR_ENB_RX_SUMMARY (1 << 17) | |
147 | #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) | |
148 | ||
149 | /* default values: | |
150 | * almost empty = less than one full sized ethernet frame (no jumbo) inside | |
151 | * the fifo almost full = can write less than one full sized ethernet frame | |
152 | * (no jumbo) inside the fifo | |
153 | */ | |
154 | #define DNET_CFG_TX_FIFO_FULL_THRES 25 | |
155 | #define DNET_CFG_RX_FIFO_FULL_THRES 20 | |
156 | ||
157 | /* | |
158 | * Capabilities. Used by the driver to know the capabilities that the ethernet | |
159 | * controller inside the FPGA have. | |
160 | */ | |
161 | ||
162 | #define DNET_HAS_MDIO (1 << 0) | |
163 | #define DNET_HAS_IRQ (1 << 1) | |
164 | #define DNET_HAS_GIGABIT (1 << 2) | |
165 | #define DNET_HAS_DMA (1 << 3) | |
166 | ||
167 | #define DNET_HAS_MII (1 << 4) /* or GMII */ | |
168 | #define DNET_HAS_RMII (1 << 5) /* or RGMII */ | |
169 | ||
170 | #define DNET_CAPS_MASK 0xFFFF | |
171 | ||
172 | #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */ | |
173 | #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ | |
174 | #define DNET_FIFO_TX_DATA_AE_TH 384 | |
175 | ||
176 | #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ | |
177 | ||
178 | /* | |
179 | * Hardware-collected statistics. | |
180 | */ | |
181 | struct dnet_stats { | |
182 | u32 rx_pkt_ignr; | |
183 | u32 rx_len_chk_err; | |
184 | u32 rx_lng_frm; | |
185 | u32 rx_shrt_frm; | |
186 | u32 rx_ipg_viol; | |
187 | u32 rx_crc_err; | |
188 | u32 rx_ok_pkt; | |
189 | u32 rx_ctl_frm; | |
190 | u32 rx_pause_frm; | |
191 | u32 rx_multicast; | |
192 | u32 rx_broadcast; | |
193 | u32 rx_vlan_tag; | |
194 | u32 rx_pre_shrink; | |
195 | u32 rx_drib_nib; | |
196 | u32 rx_unsup_opcd; | |
197 | u32 rx_byte; | |
198 | u32 tx_unicast; | |
199 | u32 tx_pause_frm; | |
200 | u32 tx_multicast; | |
201 | u32 tx_brdcast; | |
202 | u32 tx_vlan_tag; | |
203 | u32 tx_bad_fcs; | |
204 | u32 tx_jumbo; | |
205 | u32 tx_byte; | |
206 | }; | |
207 | ||
208 | struct dnet { | |
209 | void __iomem *regs; | |
210 | spinlock_t lock; | |
211 | struct platform_device *pdev; | |
212 | struct net_device *dev; | |
213 | struct dnet_stats hw_stats; | |
214 | unsigned int capabilities; /* read from FPGA */ | |
215 | struct napi_struct napi; | |
216 | ||
217 | /* PHY stuff */ | |
218 | struct mii_bus *mii_bus; | |
219 | struct phy_device *phy_dev; | |
220 | unsigned int link; | |
221 | unsigned int speed; | |
222 | unsigned int duplex; | |
223 | }; | |
224 | ||
225 | #endif /* _DNET_H */ |