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98658538 LY |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. | |
3 | * | |
4 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
5 | * Li Yang <leoli@freescale.com> | |
6 | * | |
7 | * Description: | |
8 | * QUICC Engine (QE) external definitions and structure. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | #ifndef _ASM_POWERPC_QE_H | |
16 | #define _ASM_POWERPC_QE_H | |
17 | #ifdef __KERNEL__ | |
18 | ||
19 | #include <asm/immap_qe.h> | |
20 | ||
21 | #define QE_NUM_OF_SNUM 28 | |
22 | #define QE_NUM_OF_BRGS 16 | |
23 | #define QE_NUM_OF_PORTS 1024 | |
24 | ||
25 | /* Memory partitions | |
26 | */ | |
27 | #define MEM_PART_SYSTEM 0 | |
28 | #define MEM_PART_SECONDARY 1 | |
29 | #define MEM_PART_MURAM 2 | |
30 | ||
31 | /* Export QE common operations */ | |
32 | extern void qe_reset(void); | |
33 | extern int par_io_init(struct device_node *np); | |
34 | extern int par_io_of_config(struct device_node *np); | |
364f8ffc AV |
35 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
36 | int assignment, int has_irq); | |
37 | extern int par_io_data_set(u8 port, u8 pin, u8 val); | |
98658538 LY |
38 | |
39 | /* QE internal API */ | |
40 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); | |
6b0b594b | 41 | void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); |
98658538 LY |
42 | int qe_get_snum(void); |
43 | void qe_put_snum(u8 snum); | |
4c35630c TT |
44 | unsigned long qe_muram_alloc(int size, int align); |
45 | int qe_muram_free(unsigned long offset); | |
46 | unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); | |
98658538 | 47 | void qe_muram_dump(void); |
4c35630c | 48 | void *qe_muram_addr(unsigned long offset); |
98658538 LY |
49 | |
50 | /* Buffer descriptors */ | |
51 | struct qe_bd { | |
6b0b594b TT |
52 | __be16 status; |
53 | __be16 length; | |
54 | __be32 buf; | |
98658538 LY |
55 | } __attribute__ ((packed)); |
56 | ||
57 | #define BD_STATUS_MASK 0xffff0000 | |
58 | #define BD_LENGTH_MASK 0x0000ffff | |
59 | ||
6b0b594b TT |
60 | #define BD_SC_EMPTY 0x8000 /* Receive is empty */ |
61 | #define BD_SC_READY 0x8000 /* Transmit is ready */ | |
62 | #define BD_SC_WRAP 0x2000 /* Last buffer descriptor */ | |
63 | #define BD_SC_INTRPT 0x1000 /* Interrupt on change */ | |
64 | #define BD_SC_LAST 0x0800 /* Last buffer in frame */ | |
65 | #define BD_SC_CM 0x0200 /* Continous mode */ | |
66 | #define BD_SC_ID 0x0100 /* Rec'd too many idles */ | |
67 | #define BD_SC_P 0x0100 /* xmt preamble */ | |
68 | #define BD_SC_BR 0x0020 /* Break received */ | |
69 | #define BD_SC_FR 0x0010 /* Framing error */ | |
70 | #define BD_SC_PR 0x0008 /* Parity error */ | |
71 | #define BD_SC_OV 0x0002 /* Overrun */ | |
72 | #define BD_SC_CD 0x0001 /* ?? */ | |
73 | ||
98658538 LY |
74 | /* Alignment */ |
75 | #define QE_INTR_TABLE_ALIGN 16 /* ??? */ | |
76 | #define QE_ALIGNMENT_OF_BD 8 | |
77 | #define QE_ALIGNMENT_OF_PRAM 64 | |
78 | ||
79 | /* RISC allocation */ | |
80 | enum qe_risc_allocation { | |
81 | QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ | |
82 | QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ | |
83 | QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose | |
84 | RISC 1 or RISC 2 */ | |
85 | }; | |
86 | ||
87 | /* QE extended filtering Table Lookup Key Size */ | |
88 | enum qe_fltr_tbl_lookup_key_size { | |
89 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
90 | = 0x3f, /* LookupKey parsed by the Generate LookupKey | |
91 | CMD is truncated to 8 bytes */ | |
92 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
93 | = 0x5f, /* LookupKey parsed by the Generate LookupKey | |
94 | CMD is truncated to 16 bytes */ | |
95 | }; | |
96 | ||
97 | /* QE FLTR extended filtering Largest External Table Lookup Key Size */ | |
98 | enum qe_fltr_largest_external_tbl_lookup_key_size { | |
99 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE | |
100 | = 0x0,/* not used */ | |
101 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
102 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ | |
103 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
104 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ | |
105 | }; | |
106 | ||
107 | /* structure representing QE parameter RAM */ | |
108 | struct qe_timer_tables { | |
109 | u16 tm_base; /* QE timer table base adr */ | |
110 | u16 tm_ptr; /* QE timer table pointer */ | |
111 | u16 r_tmr; /* QE timer mode register */ | |
112 | u16 r_tmv; /* QE timer valid register */ | |
113 | u32 tm_cmd; /* QE timer cmd register */ | |
114 | u32 tm_cnt; /* QE timer internal cnt */ | |
115 | } __attribute__ ((packed)); | |
116 | ||
117 | #define QE_FLTR_TAD_SIZE 8 | |
118 | ||
119 | /* QE extended filtering Termination Action Descriptor (TAD) */ | |
120 | struct qe_fltr_tad { | |
121 | u8 serialized[QE_FLTR_TAD_SIZE]; | |
122 | } __attribute__ ((packed)); | |
123 | ||
124 | /* Communication Direction */ | |
125 | enum comm_dir { | |
126 | COMM_DIR_NONE = 0, | |
127 | COMM_DIR_RX = 1, | |
128 | COMM_DIR_TX = 2, | |
129 | COMM_DIR_RX_AND_TX = 3 | |
130 | }; | |
131 | ||
132 | /* Clocks and BRGs */ | |
133 | enum qe_clock { | |
134 | QE_CLK_NONE = 0, | |
135 | QE_BRG1, /* Baud Rate Generator 1 */ | |
136 | QE_BRG2, /* Baud Rate Generator 2 */ | |
137 | QE_BRG3, /* Baud Rate Generator 3 */ | |
138 | QE_BRG4, /* Baud Rate Generator 4 */ | |
139 | QE_BRG5, /* Baud Rate Generator 5 */ | |
140 | QE_BRG6, /* Baud Rate Generator 6 */ | |
141 | QE_BRG7, /* Baud Rate Generator 7 */ | |
142 | QE_BRG8, /* Baud Rate Generator 8 */ | |
143 | QE_BRG9, /* Baud Rate Generator 9 */ | |
144 | QE_BRG10, /* Baud Rate Generator 10 */ | |
145 | QE_BRG11, /* Baud Rate Generator 11 */ | |
146 | QE_BRG12, /* Baud Rate Generator 12 */ | |
147 | QE_BRG13, /* Baud Rate Generator 13 */ | |
148 | QE_BRG14, /* Baud Rate Generator 14 */ | |
149 | QE_BRG15, /* Baud Rate Generator 15 */ | |
150 | QE_BRG16, /* Baud Rate Generator 16 */ | |
151 | QE_CLK1, /* Clock 1 */ | |
152 | QE_CLK2, /* Clock 2 */ | |
153 | QE_CLK3, /* Clock 3 */ | |
154 | QE_CLK4, /* Clock 4 */ | |
155 | QE_CLK5, /* Clock 5 */ | |
156 | QE_CLK6, /* Clock 6 */ | |
157 | QE_CLK7, /* Clock 7 */ | |
158 | QE_CLK8, /* Clock 8 */ | |
159 | QE_CLK9, /* Clock 9 */ | |
160 | QE_CLK10, /* Clock 10 */ | |
161 | QE_CLK11, /* Clock 11 */ | |
162 | QE_CLK12, /* Clock 12 */ | |
163 | QE_CLK13, /* Clock 13 */ | |
164 | QE_CLK14, /* Clock 14 */ | |
165 | QE_CLK15, /* Clock 15 */ | |
166 | QE_CLK16, /* Clock 16 */ | |
167 | QE_CLK17, /* Clock 17 */ | |
168 | QE_CLK18, /* Clock 18 */ | |
169 | QE_CLK19, /* Clock 19 */ | |
170 | QE_CLK20, /* Clock 20 */ | |
171 | QE_CLK21, /* Clock 21 */ | |
172 | QE_CLK22, /* Clock 22 */ | |
173 | QE_CLK23, /* Clock 23 */ | |
174 | QE_CLK24, /* Clock 24 */ | |
175 | QE_CLK_DUMMY, | |
176 | }; | |
177 | ||
178 | /* QE CMXUCR Registers. | |
179 | * There are two UCCs represented in each of the four CMXUCR registers. | |
180 | * These values are for the UCC in the LSBs | |
181 | */ | |
182 | #define QE_CMXUCR_MII_ENET_MNG 0x00007000 | |
183 | #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 | |
184 | #define QE_CMXUCR_GRANT 0x00008000 | |
185 | #define QE_CMXUCR_TSA 0x00004000 | |
186 | #define QE_CMXUCR_BKPT 0x00000100 | |
187 | #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F | |
188 | ||
189 | /* QE CMXGCR Registers. | |
190 | */ | |
191 | #define QE_CMXGCR_MII_ENET_MNG 0x00007000 | |
192 | #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 | |
193 | #define QE_CMXGCR_USBCS 0x0000000f | |
194 | ||
195 | /* QE CECR Commands. | |
196 | */ | |
197 | #define QE_CR_FLG 0x00010000 | |
198 | #define QE_RESET 0x80000000 | |
199 | #define QE_INIT_TX_RX 0x00000000 | |
200 | #define QE_INIT_RX 0x00000001 | |
201 | #define QE_INIT_TX 0x00000002 | |
202 | #define QE_ENTER_HUNT_MODE 0x00000003 | |
203 | #define QE_STOP_TX 0x00000004 | |
204 | #define QE_GRACEFUL_STOP_TX 0x00000005 | |
205 | #define QE_RESTART_TX 0x00000006 | |
206 | #define QE_CLOSE_RX_BD 0x00000007 | |
207 | #define QE_SWITCH_COMMAND 0x00000007 | |
208 | #define QE_SET_GROUP_ADDRESS 0x00000008 | |
209 | #define QE_START_IDMA 0x00000009 | |
210 | #define QE_MCC_STOP_RX 0x00000009 | |
211 | #define QE_ATM_TRANSMIT 0x0000000a | |
212 | #define QE_HPAC_CLEAR_ALL 0x0000000b | |
213 | #define QE_GRACEFUL_STOP_RX 0x0000001a | |
214 | #define QE_RESTART_RX 0x0000001b | |
215 | #define QE_HPAC_SET_PRIORITY 0x0000010b | |
216 | #define QE_HPAC_STOP_TX 0x0000020b | |
217 | #define QE_HPAC_STOP_RX 0x0000030b | |
218 | #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b | |
219 | #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b | |
220 | #define QE_HPAC_START_TX 0x0000060b | |
221 | #define QE_HPAC_START_RX 0x0000070b | |
222 | #define QE_USB_STOP_TX 0x0000000a | |
223 | #define QE_USB_RESTART_TX 0x0000000b | |
224 | #define QE_QMC_STOP_TX 0x0000000c | |
225 | #define QE_QMC_STOP_RX 0x0000000d | |
226 | #define QE_SS7_SU_FIL_RESET 0x0000000e | |
227 | /* jonathbr added from here down for 83xx */ | |
228 | #define QE_RESET_BCS 0x0000000a | |
229 | #define QE_MCC_INIT_TX_RX_16 0x00000003 | |
230 | #define QE_MCC_STOP_TX 0x00000004 | |
231 | #define QE_MCC_INIT_TX_1 0x00000005 | |
232 | #define QE_MCC_INIT_RX_1 0x00000006 | |
233 | #define QE_MCC_RESET 0x00000007 | |
234 | #define QE_SET_TIMER 0x00000008 | |
235 | #define QE_RANDOM_NUMBER 0x0000000c | |
236 | #define QE_ATM_MULTI_THREAD_INIT 0x00000011 | |
237 | #define QE_ASSIGN_PAGE 0x00000012 | |
238 | #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 | |
239 | #define QE_START_FLOW_CONTROL 0x00000014 | |
240 | #define QE_STOP_FLOW_CONTROL 0x00000015 | |
241 | #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 | |
242 | ||
243 | #define QE_ASSIGN_RISC 0x00000010 | |
244 | #define QE_CR_MCN_NORMAL_SHIFT 6 | |
245 | #define QE_CR_MCN_USB_SHIFT 4 | |
246 | #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 | |
247 | #define QE_CR_SNUM_SHIFT 17 | |
248 | ||
249 | /* QE CECR Sub Block - sub block of QE command. | |
250 | */ | |
251 | #define QE_CR_SUBBLOCK_INVALID 0x00000000 | |
252 | #define QE_CR_SUBBLOCK_USB 0x03200000 | |
253 | #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 | |
254 | #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 | |
255 | #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 | |
256 | #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 | |
257 | #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 | |
258 | #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 | |
259 | #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 | |
260 | #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 | |
261 | #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 | |
262 | #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 | |
263 | #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 | |
264 | #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 | |
265 | #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 | |
266 | #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 | |
267 | #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 | |
268 | #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 | |
269 | #define QE_CR_SUBBLOCK_MCC1 0x03800000 | |
270 | #define QE_CR_SUBBLOCK_MCC2 0x03a00000 | |
271 | #define QE_CR_SUBBLOCK_MCC3 0x03000000 | |
272 | #define QE_CR_SUBBLOCK_IDMA1 0x02800000 | |
273 | #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 | |
274 | #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 | |
275 | #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 | |
276 | #define QE_CR_SUBBLOCK_HPAC 0x01e00000 | |
277 | #define QE_CR_SUBBLOCK_SPI1 0x01400000 | |
278 | #define QE_CR_SUBBLOCK_SPI2 0x01600000 | |
279 | #define QE_CR_SUBBLOCK_RAND 0x01c00000 | |
280 | #define QE_CR_SUBBLOCK_TIMER 0x01e00000 | |
281 | #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 | |
282 | ||
283 | /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ | |
284 | #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ | |
285 | #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 | |
6b0b594b TT |
286 | #define QE_CR_PROTOCOL_QMC 0x02 |
287 | #define QE_CR_PROTOCOL_UART 0x04 | |
98658538 LY |
288 | #define QE_CR_PROTOCOL_ATM_POS 0x0A |
289 | #define QE_CR_PROTOCOL_ETHERNET 0x0C | |
290 | #define QE_CR_PROTOCOL_L2_SWITCH 0x0D | |
291 | ||
98658538 LY |
292 | /* BRG configuration register */ |
293 | #define QE_BRGC_ENABLE 0x00010000 | |
294 | #define QE_BRGC_DIVISOR_SHIFT 1 | |
295 | #define QE_BRGC_DIVISOR_MAX 0xFFF | |
296 | #define QE_BRGC_DIV16 1 | |
297 | ||
298 | /* QE Timers registers */ | |
299 | #define QE_GTCFR1_PCAS 0x80 | |
300 | #define QE_GTCFR1_STP2 0x20 | |
301 | #define QE_GTCFR1_RST2 0x10 | |
302 | #define QE_GTCFR1_GM2 0x08 | |
303 | #define QE_GTCFR1_GM1 0x04 | |
304 | #define QE_GTCFR1_STP1 0x02 | |
305 | #define QE_GTCFR1_RST1 0x01 | |
306 | ||
307 | /* SDMA registers */ | |
308 | #define QE_SDSR_BER1 0x02000000 | |
309 | #define QE_SDSR_BER2 0x01000000 | |
310 | ||
311 | #define QE_SDMR_GLB_1_MSK 0x80000000 | |
312 | #define QE_SDMR_ADR_SEL 0x20000000 | |
313 | #define QE_SDMR_BER1_MSK 0x02000000 | |
314 | #define QE_SDMR_BER2_MSK 0x01000000 | |
315 | #define QE_SDMR_EB1_MSK 0x00800000 | |
316 | #define QE_SDMR_ER1_MSK 0x00080000 | |
317 | #define QE_SDMR_ER2_MSK 0x00040000 | |
318 | #define QE_SDMR_CEN_MASK 0x0000E000 | |
319 | #define QE_SDMR_SBER_1 0x00000200 | |
320 | #define QE_SDMR_SBER_2 0x00000200 | |
321 | #define QE_SDMR_EB1_PR_MASK 0x000000C0 | |
322 | #define QE_SDMR_ER1_PR 0x00000008 | |
323 | ||
324 | #define QE_SDMR_CEN_SHIFT 13 | |
325 | #define QE_SDMR_EB1_PR_SHIFT 6 | |
326 | ||
327 | #define QE_SDTM_MSNUM_SHIFT 24 | |
328 | ||
329 | #define QE_SDEBCR_BA_MASK 0x01FFFFFF | |
330 | ||
331 | /* UPC */ | |
332 | #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ | |
333 | #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ | |
334 | #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ | |
335 | #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ | |
336 | #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ | |
337 | ||
6b0b594b | 338 | /* UCC GUEMR register */ |
98658538 | 339 | #define UCC_GUEMR_MODE_MASK_RX 0x02 |
98658538 | 340 | #define UCC_GUEMR_MODE_FAST_RX 0x02 |
98658538 | 341 | #define UCC_GUEMR_MODE_SLOW_RX 0x00 |
6b0b594b TT |
342 | #define UCC_GUEMR_MODE_MASK_TX 0x01 |
343 | #define UCC_GUEMR_MODE_FAST_TX 0x01 | |
98658538 | 344 | #define UCC_GUEMR_MODE_SLOW_TX 0x00 |
6b0b594b | 345 | #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) |
98658538 LY |
346 | #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but |
347 | must be set 1 */ | |
348 | ||
349 | /* structure representing UCC SLOW parameter RAM */ | |
350 | struct ucc_slow_pram { | |
6b0b594b TT |
351 | __be16 rbase; /* RX BD base address */ |
352 | __be16 tbase; /* TX BD base address */ | |
353 | u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ | |
354 | u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ | |
355 | __be16 mrblr; /* Rx buffer length */ | |
356 | __be32 rstate; /* Rx internal state */ | |
357 | __be32 rptr; /* Rx internal data pointer */ | |
358 | __be16 rbptr; /* rb BD Pointer */ | |
359 | __be16 rcount; /* Rx internal byte count */ | |
360 | __be32 rtemp; /* Rx temp */ | |
361 | __be32 tstate; /* Tx internal state */ | |
362 | __be32 tptr; /* Tx internal data pointer */ | |
363 | __be16 tbptr; /* Tx BD pointer */ | |
364 | __be16 tcount; /* Tx byte count */ | |
365 | __be32 ttemp; /* Tx temp */ | |
366 | __be32 rcrc; /* temp receive CRC */ | |
367 | __be32 tcrc; /* temp transmit CRC */ | |
98658538 LY |
368 | } __attribute__ ((packed)); |
369 | ||
370 | /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ | |
6b0b594b TT |
371 | #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 |
372 | #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 | |
98658538 LY |
373 | #define UCC_SLOW_GUMR_H_REVD 0x00002000 |
374 | #define UCC_SLOW_GUMR_H_TRX 0x00001000 | |
375 | #define UCC_SLOW_GUMR_H_TTX 0x00000800 | |
376 | #define UCC_SLOW_GUMR_H_CDP 0x00000400 | |
377 | #define UCC_SLOW_GUMR_H_CTSP 0x00000200 | |
378 | #define UCC_SLOW_GUMR_H_CDS 0x00000100 | |
379 | #define UCC_SLOW_GUMR_H_CTSS 0x00000080 | |
380 | #define UCC_SLOW_GUMR_H_TFL 0x00000040 | |
381 | #define UCC_SLOW_GUMR_H_RFW 0x00000020 | |
382 | #define UCC_SLOW_GUMR_H_TXSY 0x00000010 | |
383 | #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 | |
384 | #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 | |
385 | #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c | |
386 | #define UCC_SLOW_GUMR_H_RTSM 0x00000002 | |
387 | #define UCC_SLOW_GUMR_H_RSYN 0x00000001 | |
388 | ||
389 | #define UCC_SLOW_GUMR_L_TCI 0x10000000 | |
390 | #define UCC_SLOW_GUMR_L_RINV 0x02000000 | |
391 | #define UCC_SLOW_GUMR_L_TINV 0x01000000 | |
6b0b594b TT |
392 | #define UCC_SLOW_GUMR_L_TEND 0x00040000 |
393 | #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 | |
394 | #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 | |
395 | #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 | |
396 | #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 | |
397 | #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 | |
398 | #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 | |
399 | #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 | |
400 | #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 | |
401 | #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 | |
402 | #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 | |
403 | #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 | |
404 | #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 | |
405 | #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 | |
406 | #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 | |
407 | #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 | |
408 | #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 | |
409 | #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 | |
410 | #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 | |
411 | #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 | |
98658538 LY |
412 | #define UCC_SLOW_GUMR_L_ENR 0x00000020 |
413 | #define UCC_SLOW_GUMR_L_ENT 0x00000010 | |
6b0b594b TT |
414 | #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F |
415 | #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 | |
416 | #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 | |
417 | #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 | |
418 | #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 | |
98658538 LY |
419 | |
420 | /* General UCC FAST Mode Register */ | |
421 | #define UCC_FAST_GUMR_TCI 0x20000000 | |
422 | #define UCC_FAST_GUMR_TRX 0x10000000 | |
423 | #define UCC_FAST_GUMR_TTX 0x08000000 | |
424 | #define UCC_FAST_GUMR_CDP 0x04000000 | |
425 | #define UCC_FAST_GUMR_CTSP 0x02000000 | |
426 | #define UCC_FAST_GUMR_CDS 0x01000000 | |
427 | #define UCC_FAST_GUMR_CTSS 0x00800000 | |
428 | #define UCC_FAST_GUMR_TXSY 0x00020000 | |
429 | #define UCC_FAST_GUMR_RSYN 0x00010000 | |
430 | #define UCC_FAST_GUMR_RTSM 0x00002000 | |
431 | #define UCC_FAST_GUMR_REVD 0x00000400 | |
432 | #define UCC_FAST_GUMR_ENR 0x00000020 | |
433 | #define UCC_FAST_GUMR_ENT 0x00000010 | |
434 | ||
6b0b594b TT |
435 | /* UART Slow UCC Event Register (UCCE) */ |
436 | #define UCC_UART_UCCE_AB 0x0200 | |
437 | #define UCC_UART_UCCE_IDLE 0x0100 | |
438 | #define UCC_UART_UCCE_GRA 0x0080 | |
439 | #define UCC_UART_UCCE_BRKE 0x0040 | |
440 | #define UCC_UART_UCCE_BRKS 0x0020 | |
441 | #define UCC_UART_UCCE_CCR 0x0008 | |
442 | #define UCC_UART_UCCE_BSY 0x0004 | |
443 | #define UCC_UART_UCCE_TX 0x0002 | |
444 | #define UCC_UART_UCCE_RX 0x0001 | |
445 | ||
446 | /* HDLC Slow UCC Event Register (UCCE) */ | |
447 | #define UCC_HDLC_UCCE_GLR 0x1000 | |
448 | #define UCC_HDLC_UCCE_GLT 0x0800 | |
449 | #define UCC_HDLC_UCCE_IDLE 0x0100 | |
450 | #define UCC_HDLC_UCCE_BRKE 0x0040 | |
451 | #define UCC_HDLC_UCCE_BRKS 0x0020 | |
452 | #define UCC_HDLC_UCCE_TXE 0x0010 | |
453 | #define UCC_HDLC_UCCE_RXF 0x0008 | |
454 | #define UCC_HDLC_UCCE_BSY 0x0004 | |
455 | #define UCC_HDLC_UCCE_TXB 0x0002 | |
456 | #define UCC_HDLC_UCCE_RXB 0x0001 | |
457 | ||
458 | /* BISYNC Slow UCC Event Register (UCCE) */ | |
459 | #define UCC_BISYNC_UCCE_GRA 0x0080 | |
460 | #define UCC_BISYNC_UCCE_TXE 0x0010 | |
461 | #define UCC_BISYNC_UCCE_RCH 0x0008 | |
462 | #define UCC_BISYNC_UCCE_BSY 0x0004 | |
463 | #define UCC_BISYNC_UCCE_TXB 0x0002 | |
464 | #define UCC_BISYNC_UCCE_RXB 0x0001 | |
465 | ||
466 | /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ | |
467 | #define UCC_GETH_UCCE_MPD 0x80000000 | |
468 | #define UCC_GETH_UCCE_SCAR 0x40000000 | |
469 | #define UCC_GETH_UCCE_GRA 0x20000000 | |
470 | #define UCC_GETH_UCCE_CBPR 0x10000000 | |
471 | #define UCC_GETH_UCCE_BSY 0x08000000 | |
472 | #define UCC_GETH_UCCE_RXC 0x04000000 | |
473 | #define UCC_GETH_UCCE_TXC 0x02000000 | |
474 | #define UCC_GETH_UCCE_TXE 0x01000000 | |
475 | #define UCC_GETH_UCCE_TXB7 0x00800000 | |
476 | #define UCC_GETH_UCCE_TXB6 0x00400000 | |
477 | #define UCC_GETH_UCCE_TXB5 0x00200000 | |
478 | #define UCC_GETH_UCCE_TXB4 0x00100000 | |
479 | #define UCC_GETH_UCCE_TXB3 0x00080000 | |
480 | #define UCC_GETH_UCCE_TXB2 0x00040000 | |
481 | #define UCC_GETH_UCCE_TXB1 0x00020000 | |
482 | #define UCC_GETH_UCCE_TXB0 0x00010000 | |
483 | #define UCC_GETH_UCCE_RXB7 0x00008000 | |
484 | #define UCC_GETH_UCCE_RXB6 0x00004000 | |
485 | #define UCC_GETH_UCCE_RXB5 0x00002000 | |
486 | #define UCC_GETH_UCCE_RXB4 0x00001000 | |
487 | #define UCC_GETH_UCCE_RXB3 0x00000800 | |
488 | #define UCC_GETH_UCCE_RXB2 0x00000400 | |
489 | #define UCC_GETH_UCCE_RXB1 0x00000200 | |
490 | #define UCC_GETH_UCCE_RXB0 0x00000100 | |
491 | #define UCC_GETH_UCCE_RXF7 0x00000080 | |
492 | #define UCC_GETH_UCCE_RXF6 0x00000040 | |
493 | #define UCC_GETH_UCCE_RXF5 0x00000020 | |
494 | #define UCC_GETH_UCCE_RXF4 0x00000010 | |
495 | #define UCC_GETH_UCCE_RXF3 0x00000008 | |
496 | #define UCC_GETH_UCCE_RXF2 0x00000004 | |
497 | #define UCC_GETH_UCCE_RXF1 0x00000002 | |
498 | #define UCC_GETH_UCCE_RXF0 0x00000001 | |
499 | ||
500 | /* UPSMR, when used as a UART */ | |
501 | #define UCC_UART_UPSMR_FLC 0x8000 | |
502 | #define UCC_UART_UPSMR_SL 0x4000 | |
503 | #define UCC_UART_UPSMR_CL_MASK 0x3000 | |
504 | #define UCC_UART_UPSMR_CL_8 0x3000 | |
505 | #define UCC_UART_UPSMR_CL_7 0x2000 | |
506 | #define UCC_UART_UPSMR_CL_6 0x1000 | |
507 | #define UCC_UART_UPSMR_CL_5 0x0000 | |
508 | #define UCC_UART_UPSMR_UM_MASK 0x0c00 | |
509 | #define UCC_UART_UPSMR_UM_NORMAL 0x0000 | |
510 | #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 | |
511 | #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 | |
512 | #define UCC_UART_UPSMR_FRZ 0x0200 | |
513 | #define UCC_UART_UPSMR_RZS 0x0100 | |
514 | #define UCC_UART_UPSMR_SYN 0x0080 | |
515 | #define UCC_UART_UPSMR_DRT 0x0040 | |
516 | #define UCC_UART_UPSMR_PEN 0x0010 | |
517 | #define UCC_UART_UPSMR_RPM_MASK 0x000c | |
518 | #define UCC_UART_UPSMR_RPM_ODD 0x0000 | |
519 | #define UCC_UART_UPSMR_RPM_LOW 0x0004 | |
520 | #define UCC_UART_UPSMR_RPM_EVEN 0x0008 | |
521 | #define UCC_UART_UPSMR_RPM_HIGH 0x000C | |
522 | #define UCC_UART_UPSMR_TPM_MASK 0x0003 | |
523 | #define UCC_UART_UPSMR_TPM_ODD 0x0000 | |
524 | #define UCC_UART_UPSMR_TPM_LOW 0x0001 | |
525 | #define UCC_UART_UPSMR_TPM_EVEN 0x0002 | |
526 | #define UCC_UART_UPSMR_TPM_HIGH 0x0003 | |
98658538 LY |
527 | |
528 | /* UCC Transmit On Demand Register (UTODR) */ | |
529 | #define UCC_SLOW_TOD 0x8000 | |
530 | #define UCC_FAST_TOD 0x8000 | |
531 | ||
6b0b594b TT |
532 | /* UCC Bus Mode Register masks */ |
533 | /* Not to be confused with the Bundle Mode Register */ | |
534 | #define UCC_BMR_GBL 0x20 | |
535 | #define UCC_BMR_BO_BE 0x10 | |
536 | #define UCC_BMR_CETM 0x04 | |
537 | #define UCC_BMR_DTB 0x02 | |
538 | #define UCC_BMR_BDB 0x01 | |
539 | ||
98658538 LY |
540 | /* Function code masks */ |
541 | #define FC_GBL 0x20 | |
542 | #define FC_DTB_LCL 0x02 | |
543 | #define UCC_FAST_FUNCTION_CODE_GBL 0x20 | |
544 | #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 | |
545 | #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 | |
546 | ||
98658538 LY |
547 | #endif /* __KERNEL__ */ |
548 | #endif /* _ASM_POWERPC_QE_H */ |