Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 LT |
15 | * Author: MontaVista Software, Inc. |
16 | * ppopov@mvista.com or source@mvista.com | |
17 | * | |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
d791c2bd | 37 | #include <linux/dma-mapping.h> |
1da177e4 LT |
38 | #include <linux/module.h> |
39 | #include <linux/kernel.h> | |
1da177e4 LT |
40 | #include <linux/string.h> |
41 | #include <linux/timer.h> | |
42 | #include <linux/errno.h> | |
43 | #include <linux/in.h> | |
44 | #include <linux/ioport.h> | |
45 | #include <linux/bitops.h> | |
46 | #include <linux/slab.h> | |
47 | #include <linux/interrupt.h> | |
1da177e4 LT |
48 | #include <linux/init.h> |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/etherdevice.h> | |
51 | #include <linux/ethtool.h> | |
52 | #include <linux/mii.h> | |
53 | #include <linux/skbuff.h> | |
54 | #include <linux/delay.h> | |
8cd35da0 | 55 | #include <linux/crc32.h> |
0638dec0 | 56 | #include <linux/phy.h> |
25b31cb1 YY |
57 | |
58 | #include <asm/cpu.h> | |
1da177e4 LT |
59 | #include <asm/mipsregs.h> |
60 | #include <asm/irq.h> | |
61 | #include <asm/io.h> | |
62 | #include <asm/processor.h> | |
63 | ||
25b31cb1 YY |
64 | #include <au1000.h> |
65 | #include <prom.h> | |
66 | ||
1da177e4 LT |
67 | #include "au1000_eth.h" |
68 | ||
69 | #ifdef AU1000_ETH_DEBUG | |
70 | static int au1000_debug = 5; | |
71 | #else | |
72 | static int au1000_debug = 3; | |
73 | #endif | |
74 | ||
89be0501 | 75 | #define DRV_NAME "au1000_eth" |
d5b20697 | 76 | #define DRV_VERSION "1.6" |
1da177e4 LT |
77 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
78 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
79 | ||
80 | MODULE_AUTHOR(DRV_AUTHOR); | |
81 | MODULE_DESCRIPTION(DRV_DESC); | |
82 | MODULE_LICENSE("GPL"); | |
83 | ||
1da177e4 LT |
84 | /* |
85 | * Theory of operation | |
86 | * | |
6aa20a22 JG |
87 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
88 | * There are four receive and four transmit descriptors. These | |
89 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
90 | * hardware registers. |
91 | * | |
92 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 93 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
94 | * hardware registers, however, are still mapped at KSEG1 to |
95 | * make sure there's no out-of-order writes, and that all writes | |
96 | * complete immediately. | |
97 | */ | |
98 | ||
99 | /* These addresses are only used if yamon doesn't tell us what | |
100 | * the mac address is, and the mac address is not passed on the | |
101 | * command line. | |
102 | */ | |
6aa20a22 | 103 | static unsigned char au1000_mac_addr[6] __devinitdata = { |
1da177e4 LT |
104 | 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00 |
105 | }; | |
106 | ||
1da177e4 LT |
107 | struct au1000_private *au_macs[NUM_ETH_INTERFACES]; |
108 | ||
0638dec0 HVR |
109 | /* |
110 | * board-specific configurations | |
111 | * | |
112 | * PHY detection algorithm | |
113 | * | |
114 | * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is | |
115 | * autodetected: | |
116 | * | |
117 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
118 | * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is | |
119 | * defined) PHY address not already claimed by another netdev. | |
120 | * | |
121 | * If nothing was found that way when searching for the 2nd ethernet | |
122 | * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then | |
123 | * the first MII bus is searched as well for an unclaimed PHY; this is | |
124 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
125 | * bus. | |
126 | * | |
127 | * Finally, if no PHY is found, then the corresponding ethernet | |
128 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
129 | */ |
130 | ||
0638dec0 HVR |
131 | /* autodetection defaults */ |
132 | #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR | |
133 | #define AU1XXX_PHY1_SEARCH_ON_MAC0 | |
1da177e4 | 134 | |
0638dec0 HVR |
135 | /* static PHY setup |
136 | * | |
137 | * most boards PHY setup should be detectable properly with the | |
138 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
139 | * you have a switch attached, or want to use the PHY's interrupt | |
140 | * notification capabilities) you can provide a static PHY | |
141 | * configuration here | |
142 | * | |
143 | * IRQs may only be set, if a PHY address was configured | |
144 | * If a PHY address is given, also a bus id is required to be set | |
145 | * | |
146 | * ps: make sure the used irqs are configured properly in the board | |
147 | * specific irq-map | |
148 | */ | |
1da177e4 | 149 | |
0638dec0 HVR |
150 | #if defined(CONFIG_MIPS_BOSPORUS) |
151 | /* | |
152 | * Micrel/Kendin 5 port switch attached to MAC0, | |
153 | * MAC0 is associated with PHY address 5 (== WAN port) | |
154 | * MAC1 is not associated with any PHY, since it's connected directly | |
155 | * to the switch. | |
156 | * no interrupts are used | |
157 | */ | |
158 | # define AU1XXX_PHY_STATIC_CONFIG | |
1da177e4 | 159 | |
0638dec0 HVR |
160 | # define AU1XXX_PHY0_ADDR 5 |
161 | # define AU1XXX_PHY0_BUSID 0 | |
162 | # undef AU1XXX_PHY0_IRQ | |
1da177e4 | 163 | |
0638dec0 HVR |
164 | # undef AU1XXX_PHY1_ADDR |
165 | # undef AU1XXX_PHY1_BUSID | |
166 | # undef AU1XXX_PHY1_IRQ | |
1da177e4 LT |
167 | #endif |
168 | ||
0638dec0 HVR |
169 | #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0) |
170 | # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet | |
1da177e4 | 171 | #endif |
1da177e4 | 172 | |
5ef3041e FF |
173 | static void enable_mac(struct net_device *dev, int force_reset) |
174 | { | |
175 | unsigned long flags; | |
176 | struct au1000_private *aup = netdev_priv(dev); | |
177 | ||
178 | spin_lock_irqsave(&aup->lock, flags); | |
179 | ||
180 | if(force_reset || (!aup->mac_enabled)) { | |
181 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
182 | au_sync_delay(2); | |
183 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | |
184 | | MAC_EN_CLOCK_ENABLE); | |
185 | au_sync_delay(2); | |
186 | ||
187 | aup->mac_enabled = 1; | |
188 | } | |
189 | ||
190 | spin_unlock_irqrestore(&aup->lock, flags); | |
191 | } | |
192 | ||
0638dec0 HVR |
193 | /* |
194 | * MII operations | |
195 | */ | |
1210dde7 | 196 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 197 | { |
454d7c9b | 198 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
199 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
200 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
201 | u32 timedout = 20; |
202 | u32 mii_control; | |
203 | ||
1da177e4 LT |
204 | while (*mii_control_reg & MAC_MII_BUSY) { |
205 | mdelay(1); | |
206 | if (--timedout == 0) { | |
6aa20a22 | 207 | printk(KERN_ERR "%s: read_MII busy timeout!!\n", |
1da177e4 LT |
208 | dev->name); |
209 | return -1; | |
210 | } | |
211 | } | |
212 | ||
6aa20a22 | 213 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 214 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 LT |
215 | |
216 | *mii_control_reg = mii_control; | |
217 | ||
218 | timedout = 20; | |
219 | while (*mii_control_reg & MAC_MII_BUSY) { | |
220 | mdelay(1); | |
221 | if (--timedout == 0) { | |
6aa20a22 | 222 | printk(KERN_ERR "%s: mdio_read busy timeout!!\n", |
1da177e4 LT |
223 | dev->name); |
224 | return -1; | |
225 | } | |
226 | } | |
227 | return (int)*mii_data_reg; | |
228 | } | |
229 | ||
1210dde7 AB |
230 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
231 | int reg, u16 value) | |
1da177e4 | 232 | { |
454d7c9b | 233 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
234 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
235 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
236 | u32 timedout = 20; |
237 | u32 mii_control; | |
238 | ||
1da177e4 LT |
239 | while (*mii_control_reg & MAC_MII_BUSY) { |
240 | mdelay(1); | |
241 | if (--timedout == 0) { | |
6aa20a22 | 242 | printk(KERN_ERR "%s: mdio_write busy timeout!!\n", |
1da177e4 LT |
243 | dev->name); |
244 | return; | |
245 | } | |
246 | } | |
247 | ||
6aa20a22 | 248 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 249 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 LT |
250 | |
251 | *mii_data_reg = value; | |
252 | *mii_control_reg = mii_control; | |
253 | } | |
254 | ||
1210dde7 | 255 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
256 | { |
257 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
258 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */ | |
259 | struct net_device *const dev = bus->priv; | |
260 | ||
261 | enable_mac(dev, 0); /* make sure the MAC associated with this | |
262 | * mii_bus is enabled */ | |
1210dde7 | 263 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 264 | } |
1da177e4 | 265 | |
1210dde7 AB |
266 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
267 | u16 value) | |
1da177e4 | 268 | { |
0638dec0 | 269 | struct net_device *const dev = bus->priv; |
1da177e4 | 270 | |
0638dec0 HVR |
271 | enable_mac(dev, 0); /* make sure the MAC associated with this |
272 | * mii_bus is enabled */ | |
1210dde7 | 273 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 274 | return 0; |
1da177e4 LT |
275 | } |
276 | ||
1210dde7 | 277 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 278 | { |
0638dec0 | 279 | struct net_device *const dev = bus->priv; |
1da177e4 | 280 | |
0638dec0 HVR |
281 | enable_mac(dev, 0); /* make sure the MAC associated with this |
282 | * mii_bus is enabled */ | |
283 | return 0; | |
284 | } | |
1da177e4 | 285 | |
5ef3041e FF |
286 | static void hard_stop(struct net_device *dev) |
287 | { | |
288 | struct au1000_private *aup = netdev_priv(dev); | |
289 | ||
290 | if (au1000_debug > 4) | |
291 | printk(KERN_INFO "%s: hard stop\n", dev->name); | |
292 | ||
293 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
294 | au_sync_delay(10); | |
295 | } | |
296 | ||
297 | static void enable_rx_tx(struct net_device *dev) | |
298 | { | |
299 | struct au1000_private *aup = netdev_priv(dev); | |
300 | ||
301 | if (au1000_debug > 4) | |
302 | printk(KERN_INFO "%s: enable_rx_tx\n", dev->name); | |
303 | ||
304 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
305 | au_sync_delay(10); | |
306 | } | |
307 | ||
308 | static void | |
309 | au1000_adjust_link(struct net_device *dev) | |
310 | { | |
311 | struct au1000_private *aup = netdev_priv(dev); | |
312 | struct phy_device *phydev = aup->phy_dev; | |
313 | unsigned long flags; | |
314 | ||
315 | int status_change = 0; | |
316 | ||
317 | BUG_ON(!aup->phy_dev); | |
318 | ||
319 | spin_lock_irqsave(&aup->lock, flags); | |
320 | ||
321 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
322 | // speed changed | |
323 | ||
324 | switch(phydev->speed) { | |
325 | case SPEED_10: | |
326 | case SPEED_100: | |
327 | break; | |
328 | default: | |
329 | printk(KERN_WARNING | |
330 | "%s: Speed (%d) is not 10/100 ???\n", | |
331 | dev->name, phydev->speed); | |
332 | break; | |
333 | } | |
334 | ||
335 | aup->old_speed = phydev->speed; | |
336 | ||
337 | status_change = 1; | |
338 | } | |
339 | ||
340 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
341 | // duplex mode changed | |
342 | ||
343 | /* switching duplex mode requires to disable rx and tx! */ | |
344 | hard_stop(dev); | |
345 | ||
346 | if (DUPLEX_FULL == phydev->duplex) | |
347 | aup->mac->control = ((aup->mac->control | |
348 | | MAC_FULL_DUPLEX) | |
349 | & ~MAC_DISABLE_RX_OWN); | |
350 | else | |
351 | aup->mac->control = ((aup->mac->control | |
352 | & ~MAC_FULL_DUPLEX) | |
353 | | MAC_DISABLE_RX_OWN); | |
354 | au_sync_delay(1); | |
355 | ||
356 | enable_rx_tx(dev); | |
357 | aup->old_duplex = phydev->duplex; | |
358 | ||
359 | status_change = 1; | |
360 | } | |
361 | ||
362 | if(phydev->link != aup->old_link) { | |
363 | // link state changed | |
364 | ||
365 | if (!phydev->link) { | |
366 | /* link went down */ | |
367 | aup->old_speed = 0; | |
368 | aup->old_duplex = -1; | |
369 | } | |
370 | ||
371 | aup->old_link = phydev->link; | |
372 | status_change = 1; | |
373 | } | |
374 | ||
375 | spin_unlock_irqrestore(&aup->lock, flags); | |
376 | ||
377 | if (status_change) { | |
378 | if (phydev->link) | |
379 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
380 | dev->name, phydev->speed, | |
381 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); | |
382 | else | |
383 | printk(KERN_INFO "%s: link down\n", dev->name); | |
384 | } | |
385 | } | |
386 | ||
0638dec0 HVR |
387 | static int mii_probe (struct net_device *dev) |
388 | { | |
454d7c9b | 389 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
390 | struct phy_device *phydev = NULL; |
391 | ||
392 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
393 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
394 | ||
395 | if(aup->mac_id == 0) { /* get PHY0 */ | |
396 | # if defined(AU1XXX_PHY0_ADDR) | |
298cf9be | 397 | phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR]; |
0638dec0 HVR |
398 | # else |
399 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
400 | dev->name); | |
401 | return 0; | |
402 | # endif /* defined(AU1XXX_PHY0_ADDR) */ | |
403 | } else if (aup->mac_id == 1) { /* get PHY1 */ | |
404 | # if defined(AU1XXX_PHY1_ADDR) | |
298cf9be | 405 | phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR]; |
0638dec0 HVR |
406 | # else |
407 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
408 | dev->name); | |
409 | return 0; | |
410 | # endif /* defined(AU1XXX_PHY1_ADDR) */ | |
411 | } | |
412 | ||
413 | #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */ | |
414 | int phy_addr; | |
415 | ||
416 | /* find the first (lowest address) PHY on the current MAC's MII bus */ | |
417 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) | |
298cf9be LB |
418 | if (aup->mii_bus->phy_map[phy_addr]) { |
419 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
0638dec0 HVR |
420 | # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR) |
421 | break; /* break out with first one found */ | |
422 | # endif | |
1da177e4 | 423 | } |
1da177e4 | 424 | |
0638dec0 HVR |
425 | # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0) |
426 | /* try harder to find a PHY */ | |
427 | if (!phydev && (aup->mac_id == 1)) { | |
428 | /* no PHY found, maybe we have a dual PHY? */ | |
429 | printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, " | |
430 | "let's see if it's attached to MAC0...\n"); | |
431 | ||
432 | BUG_ON(!au_macs[0]); | |
433 | ||
434 | /* find the first (lowest address) non-attached PHY on | |
435 | * the MAC0 MII bus */ | |
436 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
437 | struct phy_device *const tmp_phydev = | |
298cf9be | 438 | au_macs[0]->mii_bus->phy_map[phy_addr]; |
0638dec0 HVR |
439 | |
440 | if (!tmp_phydev) | |
441 | continue; /* no PHY here... */ | |
442 | ||
443 | if (tmp_phydev->attached_dev) | |
444 | continue; /* already claimed by MAC0 */ | |
445 | ||
446 | phydev = tmp_phydev; | |
447 | break; /* found it */ | |
1da177e4 LT |
448 | } |
449 | } | |
0638dec0 | 450 | # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */ |
1da177e4 | 451 | |
0638dec0 HVR |
452 | #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */ |
453 | if (!phydev) { | |
454 | printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name); | |
1da177e4 LT |
455 | return -1; |
456 | } | |
457 | ||
0638dec0 | 458 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
459 | BUG_ON(phydev->attached_dev); |
460 | ||
db1d7bf7 KS |
461 | phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link, |
462 | 0, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
463 | |
464 | if (IS_ERR(phydev)) { | |
465 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
466 | return PTR_ERR(phydev); | |
467 | } | |
468 | ||
469 | /* mask with MAC supported features */ | |
470 | phydev->supported &= (SUPPORTED_10baseT_Half | |
471 | | SUPPORTED_10baseT_Full | |
472 | | SUPPORTED_100baseT_Half | |
473 | | SUPPORTED_100baseT_Full | |
474 | | SUPPORTED_Autoneg | |
475 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
476 | | SUPPORTED_MII | |
477 | | SUPPORTED_TP); | |
478 | ||
479 | phydev->advertising = phydev->supported; | |
480 | ||
481 | aup->old_link = 0; | |
482 | aup->old_speed = 0; | |
483 | aup->old_duplex = -1; | |
484 | aup->phy_dev = phydev; | |
485 | ||
486 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
db1d7bf7 KS |
487 | "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, |
488 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
1da177e4 LT |
489 | |
490 | return 0; | |
491 | } | |
492 | ||
493 | ||
494 | /* | |
495 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 496 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
497 | * both, receive and transmit operations. |
498 | */ | |
499 | static db_dest_t *GetFreeDB(struct au1000_private *aup) | |
500 | { | |
501 | db_dest_t *pDB; | |
502 | pDB = aup->pDBfree; | |
503 | ||
504 | if (pDB) { | |
505 | aup->pDBfree = pDB->pnext; | |
506 | } | |
507 | return pDB; | |
508 | } | |
509 | ||
510 | void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB) | |
511 | { | |
512 | db_dest_t *pDBfree = aup->pDBfree; | |
513 | if (pDBfree) | |
514 | pDBfree->pnext = pDB; | |
515 | aup->pDBfree = pDB; | |
516 | } | |
517 | ||
0638dec0 HVR |
518 | static void reset_mac_unlocked(struct net_device *dev) |
519 | { | |
454d7c9b | 520 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
521 | int i; |
522 | ||
523 | hard_stop(dev); | |
524 | ||
525 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
526 | au_sync_delay(2); | |
527 | *aup->enable = 0; | |
528 | au_sync_delay(2); | |
529 | ||
1da177e4 LT |
530 | aup->tx_full = 0; |
531 | for (i = 0; i < NUM_RX_DMA; i++) { | |
532 | /* reset control bits */ | |
533 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
534 | } | |
535 | for (i = 0; i < NUM_TX_DMA; i++) { | |
536 | /* reset control bits */ | |
537 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
538 | } | |
0638dec0 HVR |
539 | |
540 | aup->mac_enabled = 0; | |
541 | ||
1da177e4 LT |
542 | } |
543 | ||
0638dec0 HVR |
544 | static void reset_mac(struct net_device *dev) |
545 | { | |
454d7c9b | 546 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
547 | unsigned long flags; |
548 | ||
549 | if (au1000_debug > 4) | |
550 | printk(KERN_INFO "%s: reset mac, aup %x\n", | |
551 | dev->name, (unsigned)aup); | |
552 | ||
553 | spin_lock_irqsave(&aup->lock, flags); | |
554 | ||
555 | reset_mac_unlocked (dev); | |
556 | ||
557 | spin_unlock_irqrestore(&aup->lock, flags); | |
558 | } | |
1da177e4 | 559 | |
6aa20a22 | 560 | /* |
1da177e4 LT |
561 | * Setup the receive and transmit "rings". These pointers are the addresses |
562 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
563 | * these are not descriptors sitting in memory. | |
564 | */ | |
6aa20a22 | 565 | static void |
1da177e4 LT |
566 | setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
567 | { | |
568 | int i; | |
569 | ||
570 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 571 | aup->rx_dma_ring[i] = |
1da177e4 LT |
572 | (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i); |
573 | } | |
574 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 575 | aup->tx_dma_ring[i] = |
1da177e4 LT |
576 | (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i); |
577 | } | |
578 | } | |
579 | ||
580 | static struct { | |
1da177e4 LT |
581 | u32 base_addr; |
582 | u32 macen_addr; | |
583 | int irq; | |
584 | struct net_device *dev; | |
89be0501 SS |
585 | } iflist[2] = { |
586 | #ifdef CONFIG_SOC_AU1000 | |
587 | {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT}, | |
588 | {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT} | |
589 | #endif | |
590 | #ifdef CONFIG_SOC_AU1100 | |
591 | {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT} | |
592 | #endif | |
593 | #ifdef CONFIG_SOC_AU1500 | |
594 | {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT}, | |
595 | {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT} | |
596 | #endif | |
597 | #ifdef CONFIG_SOC_AU1550 | |
598 | {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT}, | |
599 | {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT} | |
600 | #endif | |
601 | }; | |
1da177e4 LT |
602 | |
603 | static int num_ifs; | |
604 | ||
0638dec0 HVR |
605 | /* |
606 | * ethtool operations | |
607 | */ | |
1da177e4 | 608 | |
0638dec0 | 609 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 610 | { |
454d7c9b | 611 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 612 | |
0638dec0 HVR |
613 | if (aup->phy_dev) |
614 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 615 | |
0638dec0 | 616 | return -EINVAL; |
1da177e4 LT |
617 | } |
618 | ||
0638dec0 | 619 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 620 | { |
454d7c9b | 621 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 622 | |
0638dec0 HVR |
623 | if (!capable(CAP_NET_ADMIN)) |
624 | return -EPERM; | |
1da177e4 | 625 | |
0638dec0 HVR |
626 | if (aup->phy_dev) |
627 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 628 | |
0638dec0 | 629 | return -EINVAL; |
1da177e4 LT |
630 | } |
631 | ||
632 | static void | |
633 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
634 | { | |
454d7c9b | 635 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
636 | |
637 | strcpy(info->driver, DRV_NAME); | |
638 | strcpy(info->version, DRV_VERSION); | |
639 | info->fw_version[0] = '\0'; | |
640 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
641 | info->regdump_len = 0; | |
642 | } | |
643 | ||
7282d491 | 644 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
645 | .get_settings = au1000_get_settings, |
646 | .set_settings = au1000_set_settings, | |
647 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 648 | .get_link = ethtool_op_get_link, |
1da177e4 LT |
649 | }; |
650 | ||
5ef3041e FF |
651 | |
652 | /* | |
653 | * Initialize the interface. | |
654 | * | |
655 | * When the device powers up, the clocks are disabled and the | |
656 | * mac is in reset state. When the interface is closed, we | |
657 | * do the same -- reset the device and disable the clocks to | |
658 | * conserve power. Thus, whenever au1000_init() is called, | |
659 | * the device should already be in reset state. | |
660 | */ | |
661 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 662 | { |
5ef3041e FF |
663 | struct au1000_private *aup = netdev_priv(dev); |
664 | unsigned long flags; | |
665 | int i; | |
666 | u32 control; | |
89be0501 | 667 | |
5ef3041e FF |
668 | if (au1000_debug > 4) |
669 | printk("%s: au1000_init\n", dev->name); | |
1da177e4 | 670 | |
5ef3041e FF |
671 | /* bring the device out of reset */ |
672 | enable_mac(dev, 1); | |
89be0501 | 673 | |
5ef3041e | 674 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 675 | |
5ef3041e FF |
676 | aup->mac->control = 0; |
677 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
678 | aup->tx_tail = aup->tx_head; | |
679 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 680 | |
5ef3041e FF |
681 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; |
682 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
683 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | |
684 | ||
685 | for (i = 0; i < NUM_RX_DMA; i++) { | |
686 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; | |
1da177e4 | 687 | } |
5ef3041e | 688 | au_sync(); |
1da177e4 | 689 | |
5ef3041e FF |
690 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
691 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
692 | control |= MAC_BIG_ENDIAN; | |
693 | #endif | |
694 | if (aup->phy_dev) { | |
695 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
696 | control |= MAC_FULL_DUPLEX; | |
697 | else | |
698 | control |= MAC_DISABLE_RX_OWN; | |
699 | } else { /* PHY-less op, assume full-duplex */ | |
700 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
701 | } |
702 | ||
5ef3041e FF |
703 | aup->mac->control = control; |
704 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | |
705 | au_sync(); | |
1da177e4 | 706 | |
5ef3041e FF |
707 | spin_unlock_irqrestore(&aup->lock, flags); |
708 | return 0; | |
709 | } | |
1da177e4 | 710 | |
5ef3041e FF |
711 | static inline void update_rx_stats(struct net_device *dev, u32 status) |
712 | { | |
713 | struct au1000_private *aup = netdev_priv(dev); | |
714 | struct net_device_stats *ps = &dev->stats; | |
1da177e4 | 715 | |
5ef3041e FF |
716 | ps->rx_packets++; |
717 | if (status & RX_MCAST_FRAME) | |
718 | ps->multicast++; | |
1da177e4 | 719 | |
5ef3041e FF |
720 | if (status & RX_ERROR) { |
721 | ps->rx_errors++; | |
722 | if (status & RX_MISSED_FRAME) | |
723 | ps->rx_missed_errors++; | |
724 | if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR)) | |
725 | ps->rx_length_errors++; | |
726 | if (status & RX_CRC_ERROR) | |
727 | ps->rx_crc_errors++; | |
728 | if (status & RX_COLL) | |
729 | ps->collisions++; | |
298cf9be | 730 | } |
5ef3041e FF |
731 | else |
732 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; | |
298cf9be | 733 | |
1da177e4 LT |
734 | } |
735 | ||
6aa20a22 | 736 | /* |
5ef3041e | 737 | * Au1000 receive routine. |
1da177e4 | 738 | */ |
5ef3041e | 739 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 740 | { |
454d7c9b | 741 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e FF |
742 | struct sk_buff *skb; |
743 | volatile rx_dma_t *prxd; | |
744 | u32 buff_stat, status; | |
745 | db_dest_t *pDB; | |
746 | u32 frmlen; | |
1da177e4 | 747 | |
5ef3041e FF |
748 | if (au1000_debug > 5) |
749 | printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head); | |
1da177e4 | 750 | |
5ef3041e FF |
751 | prxd = aup->rx_dma_ring[aup->rx_head]; |
752 | buff_stat = prxd->buff_stat; | |
753 | while (buff_stat & RX_T_DONE) { | |
754 | status = prxd->status; | |
755 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
756 | update_rx_stats(dev, status); | |
757 | if (!(status & RX_ERROR)) { | |
1da177e4 | 758 | |
5ef3041e FF |
759 | /* good frame */ |
760 | frmlen = (status & RX_FRAME_LEN_MASK); | |
761 | frmlen -= 4; /* Remove FCS */ | |
762 | skb = dev_alloc_skb(frmlen + 2); | |
763 | if (skb == NULL) { | |
764 | printk(KERN_ERR | |
765 | "%s: Memory squeeze, dropping packet.\n", | |
766 | dev->name); | |
767 | dev->stats.rx_dropped++; | |
768 | continue; | |
769 | } | |
770 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
771 | skb_copy_to_linear_data(skb, | |
772 | (unsigned char *)pDB->vaddr, frmlen); | |
773 | skb_put(skb, frmlen); | |
774 | skb->protocol = eth_type_trans(skb, dev); | |
775 | netif_rx(skb); /* pass the packet to upper layers */ | |
776 | } | |
777 | else { | |
778 | if (au1000_debug > 4) { | |
779 | if (status & RX_MISSED_FRAME) | |
780 | printk("rx miss\n"); | |
781 | if (status & RX_WDOG_TIMER) | |
782 | printk("rx wdog\n"); | |
783 | if (status & RX_RUNT) | |
784 | printk("rx runt\n"); | |
785 | if (status & RX_OVERLEN) | |
786 | printk("rx overlen\n"); | |
787 | if (status & RX_COLL) | |
788 | printk("rx coll\n"); | |
789 | if (status & RX_MII_ERROR) | |
790 | printk("rx mii error\n"); | |
791 | if (status & RX_CRC_ERROR) | |
792 | printk("rx crc error\n"); | |
793 | if (status & RX_LEN_ERROR) | |
794 | printk("rx len error\n"); | |
795 | if (status & RX_U_CNTRL_FRAME) | |
796 | printk("rx u control frame\n"); | |
797 | if (status & RX_MISSED_FRAME) | |
798 | printk("rx miss\n"); | |
799 | } | |
800 | } | |
801 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
802 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
803 | au_sync(); | |
1da177e4 | 804 | |
5ef3041e FF |
805 | /* next descriptor */ |
806 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
807 | buff_stat = prxd->buff_stat; | |
1da177e4 | 808 | } |
1da177e4 LT |
809 | return 0; |
810 | } | |
811 | ||
5ef3041e | 812 | static void update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 813 | { |
454d7c9b | 814 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 815 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 816 | |
5ef3041e FF |
817 | if (status & TX_FRAME_ABORTED) { |
818 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
819 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
820 | /* any other tx errors are only valid | |
821 | * in half duplex mode */ | |
822 | ps->tx_errors++; | |
823 | ps->tx_aborted_errors++; | |
824 | } | |
1da177e4 | 825 | } |
5ef3041e FF |
826 | else { |
827 | ps->tx_errors++; | |
828 | ps->tx_aborted_errors++; | |
829 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
830 | ps->tx_carrier_errors++; | |
831 | } | |
832 | } | |
833 | } | |
0638dec0 | 834 | |
5ef3041e FF |
835 | /* |
836 | * Called from the interrupt service routine to acknowledge | |
837 | * the TX DONE bits. This is a must if the irq is setup as | |
838 | * edge triggered. | |
839 | */ | |
840 | static void au1000_tx_ack(struct net_device *dev) | |
841 | { | |
842 | struct au1000_private *aup = netdev_priv(dev); | |
843 | volatile tx_dma_t *ptxd; | |
0638dec0 | 844 | |
5ef3041e | 845 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 846 | |
5ef3041e FF |
847 | while (ptxd->buff_stat & TX_T_DONE) { |
848 | update_tx_stats(dev, ptxd->status); | |
849 | ptxd->buff_stat &= ~TX_T_DONE; | |
850 | ptxd->len = 0; | |
851 | au_sync(); | |
0638dec0 | 852 | |
5ef3041e FF |
853 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
854 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 855 | |
5ef3041e FF |
856 | if (aup->tx_full) { |
857 | aup->tx_full = 0; | |
858 | netif_wake_queue(dev); | |
859 | } | |
1da177e4 | 860 | } |
5ef3041e | 861 | } |
1da177e4 | 862 | |
5ef3041e FF |
863 | /* |
864 | * Au1000 interrupt service routine. | |
865 | */ | |
866 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
867 | { | |
868 | struct net_device *dev = dev_id; | |
1da177e4 | 869 | |
5ef3041e FF |
870 | /* Handle RX interrupts first to minimize chance of overrun */ |
871 | ||
872 | au1000_rx(dev); | |
873 | au1000_tx_ack(dev); | |
874 | return IRQ_RETVAL(1); | |
1da177e4 LT |
875 | } |
876 | ||
877 | static int au1000_open(struct net_device *dev) | |
878 | { | |
879 | int retval; | |
454d7c9b | 880 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
881 | |
882 | if (au1000_debug > 4) | |
883 | printk("%s: open: dev=%p\n", dev->name, dev); | |
884 | ||
0638dec0 HVR |
885 | if ((retval = request_irq(dev->irq, &au1000_interrupt, 0, |
886 | dev->name, dev))) { | |
887 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
888 | dev->name, dev->irq); | |
889 | return retval; | |
890 | } | |
891 | ||
1da177e4 LT |
892 | if ((retval = au1000_init(dev))) { |
893 | printk(KERN_ERR "%s: error in au1000_init\n", dev->name); | |
894 | free_irq(dev->irq, dev); | |
895 | return retval; | |
896 | } | |
1da177e4 | 897 | |
0638dec0 HVR |
898 | if (aup->phy_dev) { |
899 | /* cause the PHY state machine to schedule a link state check */ | |
900 | aup->phy_dev->state = PHY_CHANGELINK; | |
901 | phy_start(aup->phy_dev); | |
1da177e4 LT |
902 | } |
903 | ||
0638dec0 | 904 | netif_start_queue(dev); |
1da177e4 LT |
905 | |
906 | if (au1000_debug > 4) | |
907 | printk("%s: open: Initialization done.\n", dev->name); | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | static int au1000_close(struct net_device *dev) | |
913 | { | |
0638dec0 | 914 | unsigned long flags; |
454d7c9b | 915 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 LT |
916 | |
917 | if (au1000_debug > 4) | |
918 | printk("%s: close: dev=%p\n", dev->name, dev); | |
919 | ||
0638dec0 HVR |
920 | if (aup->phy_dev) |
921 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
922 | |
923 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 HVR |
924 | |
925 | reset_mac_unlocked (dev); | |
926 | ||
1da177e4 LT |
927 | /* stop the device */ |
928 | netif_stop_queue(dev); | |
929 | ||
930 | /* disable the interrupt */ | |
931 | free_irq(dev->irq, dev); | |
932 | spin_unlock_irqrestore(&aup->lock, flags); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
1da177e4 LT |
937 | /* |
938 | * Au1000 transmit routine. | |
939 | */ | |
940 | static int au1000_tx(struct sk_buff *skb, struct net_device *dev) | |
941 | { | |
454d7c9b | 942 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 943 | struct net_device_stats *ps = &dev->stats; |
1da177e4 LT |
944 | volatile tx_dma_t *ptxd; |
945 | u32 buff_stat; | |
946 | db_dest_t *pDB; | |
947 | int i; | |
948 | ||
949 | if (au1000_debug > 5) | |
6aa20a22 JG |
950 | printk("%s: tx: aup %x len=%d, data=%p, head %d\n", |
951 | dev->name, (unsigned)aup, skb->len, | |
1da177e4 LT |
952 | skb->data, aup->tx_head); |
953 | ||
954 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
955 | buff_stat = ptxd->buff_stat; | |
956 | if (buff_stat & TX_DMA_ENABLE) { | |
957 | /* We've wrapped around and the transmitter is still busy */ | |
958 | netif_stop_queue(dev); | |
959 | aup->tx_full = 1; | |
960 | return 1; | |
961 | } | |
962 | else if (buff_stat & TX_T_DONE) { | |
c2d3d4b9 | 963 | update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
964 | ptxd->len = 0; |
965 | } | |
966 | ||
967 | if (aup->tx_full) { | |
968 | aup->tx_full = 0; | |
969 | netif_wake_queue(dev); | |
970 | } | |
971 | ||
972 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
d626f62b | 973 | skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); |
1da177e4 | 974 | if (skb->len < ETH_ZLEN) { |
6aa20a22 | 975 | for (i=skb->len; i<ETH_ZLEN; i++) { |
1da177e4 LT |
976 | ((char *)pDB->vaddr)[i] = 0; |
977 | } | |
978 | ptxd->len = ETH_ZLEN; | |
979 | } | |
980 | else | |
5ef3041e | 981 | ptxd->len = skb->len; |
1da177e4 | 982 | |
5ef3041e FF |
983 | ps->tx_packets++; |
984 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 985 | |
5ef3041e FF |
986 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
987 | au_sync(); | |
988 | dev_kfree_skb(skb); | |
989 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
990 | dev->trans_start = jiffies; | |
991 | return 0; | |
1da177e4 LT |
992 | } |
993 | ||
1da177e4 LT |
994 | /* |
995 | * The Tx ring has been full longer than the watchdog timeout | |
996 | * value. The transmitter must be hung? | |
997 | */ | |
998 | static void au1000_tx_timeout(struct net_device *dev) | |
999 | { | |
1000 | printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev); | |
1001 | reset_mac(dev); | |
1002 | au1000_init(dev); | |
1003 | dev->trans_start = jiffies; | |
1004 | netif_wake_queue(dev); | |
1005 | } | |
1006 | ||
d9a92cee | 1007 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 1008 | { |
454d7c9b | 1009 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1010 | |
6aa20a22 | 1011 | if (au1000_debug > 4) |
d9a92cee | 1012 | printk("%s: au1000_multicast_list: flags=%x\n", dev->name, dev->flags); |
1da177e4 LT |
1013 | |
1014 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1015 | aup->mac->control |= MAC_PROMISCUOUS; | |
1da177e4 LT |
1016 | } else if ((dev->flags & IFF_ALLMULTI) || |
1017 | dev->mc_count > MULTICAST_FILTER_LIMIT) { | |
1018 | aup->mac->control |= MAC_PASS_ALL_MULTI; | |
1019 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1020 | printk(KERN_INFO "%s: Pass all multicast\n", dev->name); | |
1021 | } else { | |
1022 | int i; | |
1023 | struct dev_mc_list *mclist; | |
1024 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1025 | ||
1026 | mc_filter[1] = mc_filter[0] = 0; | |
1027 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1028 | i++, mclist = mclist->next) { | |
6aa20a22 | 1029 | set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26, |
1da177e4 LT |
1030 | (long *)mc_filter); |
1031 | } | |
1032 | aup->mac->multi_hash_high = mc_filter[1]; | |
1033 | aup->mac->multi_hash_low = mc_filter[0]; | |
1034 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1035 | aup->mac->control |= MAC_HASH_MODE; | |
1036 | } | |
1037 | } | |
1038 | ||
1da177e4 LT |
1039 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1040 | { | |
454d7c9b | 1041 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1042 | |
0638dec0 | 1043 | if (!netif_running(dev)) return -EINVAL; |
1da177e4 | 1044 | |
0638dec0 | 1045 | if (!aup->phy_dev) return -EINVAL; // PHY not controllable |
1da177e4 | 1046 | |
0638dec0 | 1047 | return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd); |
1da177e4 LT |
1048 | } |
1049 | ||
d9a92cee AB |
1050 | static const struct net_device_ops au1000_netdev_ops = { |
1051 | .ndo_open = au1000_open, | |
1052 | .ndo_stop = au1000_close, | |
1053 | .ndo_start_xmit = au1000_tx, | |
1054 | .ndo_set_multicast_list = au1000_multicast_list, | |
1055 | .ndo_do_ioctl = au1000_ioctl, | |
1056 | .ndo_tx_timeout = au1000_tx_timeout, | |
1057 | .ndo_set_mac_address = eth_mac_addr, | |
1058 | .ndo_validate_addr = eth_validate_addr, | |
1059 | .ndo_change_mtu = eth_change_mtu, | |
1060 | }; | |
1061 | ||
5ef3041e FF |
1062 | static struct net_device * au1000_probe(int port_num) |
1063 | { | |
1064 | static unsigned version_printed = 0; | |
1065 | struct au1000_private *aup = NULL; | |
1066 | struct net_device *dev = NULL; | |
1067 | db_dest_t *pDB, *pDBfree; | |
1068 | char ethaddr[6]; | |
1069 | int irq, i, err; | |
1070 | u32 base, macen; | |
1071 | ||
1072 | if (port_num >= NUM_ETH_INTERFACES) | |
1073 | return NULL; | |
1074 | ||
1075 | base = CPHYSADDR(iflist[port_num].base_addr ); | |
1076 | macen = CPHYSADDR(iflist[port_num].macen_addr); | |
1077 | irq = iflist[port_num].irq; | |
1078 | ||
1079 | if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") || | |
1080 | !request_mem_region(macen, 4, "Au1x00 ENET")) | |
1081 | return NULL; | |
1082 | ||
1083 | if (version_printed++ == 0) | |
1084 | printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
1085 | ||
1086 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
1087 | if (!dev) { | |
1088 | printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME); | |
1089 | return NULL; | |
1090 | } | |
1091 | ||
1092 | if ((err = register_netdev(dev)) != 0) { | |
1093 | printk(KERN_ERR "%s: Cannot register net device, error %d\n", | |
1094 | DRV_NAME, err); | |
1095 | free_netdev(dev); | |
1096 | return NULL; | |
1097 | } | |
1098 | ||
1099 | printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", | |
1100 | dev->name, base, irq); | |
1101 | ||
1102 | aup = netdev_priv(dev); | |
1103 | ||
1104 | spin_lock_init(&aup->lock); | |
1105 | ||
1106 | /* Allocate the data buffers */ | |
1107 | /* Snooping works fine with eth on all au1xxx */ | |
1108 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * | |
1109 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1110 | &aup->dma_addr, 0); | |
1111 | if (!aup->vaddr) { | |
1112 | free_netdev(dev); | |
1113 | release_mem_region( base, MAC_IOSIZE); | |
1114 | release_mem_region(macen, 4); | |
1115 | return NULL; | |
1116 | } | |
1117 | ||
1118 | /* aup->mac is the base address of the MAC's registers */ | |
1119 | aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr; | |
1120 | ||
1121 | /* Setup some variables for quick register address access */ | |
1122 | aup->enable = (volatile u32 *)iflist[port_num].macen_addr; | |
1123 | aup->mac_id = port_num; | |
1124 | au_macs[port_num] = aup; | |
1125 | ||
1126 | if (port_num == 0) { | |
1127 | if (prom_get_ethernet_addr(ethaddr) == 0) | |
1128 | memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr)); | |
1129 | else { | |
1130 | printk(KERN_INFO "%s: No MAC address found\n", | |
1131 | dev->name); | |
1132 | /* Use the hard coded MAC addresses */ | |
1133 | } | |
1134 | ||
1135 | setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); | |
1136 | } else if (port_num == 1) | |
1137 | setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); | |
1138 | ||
1139 | /* | |
1140 | * Assign to the Ethernet ports two consecutive MAC addresses | |
1141 | * to match those that are printed on their stickers | |
1142 | */ | |
1143 | memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr)); | |
1144 | dev->dev_addr[5] += port_num; | |
1145 | ||
1146 | *aup->enable = 0; | |
1147 | aup->mac_enabled = 0; | |
1148 | ||
1149 | aup->mii_bus = mdiobus_alloc(); | |
1150 | if (aup->mii_bus == NULL) | |
1151 | goto err_out; | |
1152 | ||
1153 | aup->mii_bus->priv = dev; | |
1154 | aup->mii_bus->read = au1000_mdiobus_read; | |
1155 | aup->mii_bus->write = au1000_mdiobus_write; | |
1156 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1157 | aup->mii_bus->name = "au1000_eth_mii"; | |
1158 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id); | |
1159 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1160 | for(i = 0; i < PHY_MAX_ADDR; ++i) | |
1161 | aup->mii_bus->irq[i] = PHY_POLL; | |
1162 | ||
1163 | /* if known, set corresponding PHY IRQs */ | |
1164 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
1165 | # if defined(AU1XXX_PHY0_IRQ) | |
1166 | if (AU1XXX_PHY0_BUSID == aup->mac_id) | |
1167 | aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ; | |
1168 | # endif | |
1169 | # if defined(AU1XXX_PHY1_IRQ) | |
1170 | if (AU1XXX_PHY1_BUSID == aup->mac_id) | |
1171 | aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ; | |
1172 | # endif | |
1173 | #endif | |
1174 | mdiobus_register(aup->mii_bus); | |
1175 | ||
1176 | if (mii_probe(dev) != 0) { | |
1177 | goto err_out; | |
1178 | } | |
1179 | ||
1180 | pDBfree = NULL; | |
1181 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1182 | pDB = aup->db; | |
1183 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1184 | pDB->pnext = pDBfree; | |
1185 | pDBfree = pDB; | |
1186 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1187 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1188 | pDB++; | |
1189 | } | |
1190 | aup->pDBfree = pDBfree; | |
1191 | ||
1192 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1193 | pDB = GetFreeDB(aup); | |
1194 | if (!pDB) { | |
1195 | goto err_out; | |
1196 | } | |
1197 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1198 | aup->rx_db_inuse[i] = pDB; | |
1199 | } | |
1200 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1201 | pDB = GetFreeDB(aup); | |
1202 | if (!pDB) { | |
1203 | goto err_out; | |
1204 | } | |
1205 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1206 | aup->tx_dma_ring[i]->len = 0; | |
1207 | aup->tx_db_inuse[i] = pDB; | |
1208 | } | |
1209 | ||
1210 | dev->base_addr = base; | |
1211 | dev->irq = irq; | |
d9a92cee | 1212 | dev->netdev_ops = &au1000_netdev_ops; |
5ef3041e | 1213 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); |
5ef3041e FF |
1214 | dev->watchdog_timeo = ETH_TX_TIMEOUT; |
1215 | ||
1216 | /* | |
1217 | * The boot code uses the ethernet controller, so reset it to start | |
1218 | * fresh. au1000_init() expects that the device is in reset state. | |
1219 | */ | |
1220 | reset_mac(dev); | |
1221 | ||
1222 | return dev; | |
1223 | ||
1224 | err_out: | |
1225 | if (aup->mii_bus != NULL) { | |
1226 | mdiobus_unregister(aup->mii_bus); | |
1227 | mdiobus_free(aup->mii_bus); | |
1228 | } | |
1229 | ||
1230 | /* here we should have a valid dev plus aup-> register addresses | |
1231 | * so we can reset the mac properly.*/ | |
1232 | reset_mac(dev); | |
1233 | ||
1234 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1235 | if (aup->rx_db_inuse[i]) | |
1236 | ReleaseDB(aup, aup->rx_db_inuse[i]); | |
1237 | } | |
1238 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1239 | if (aup->tx_db_inuse[i]) | |
1240 | ReleaseDB(aup, aup->tx_db_inuse[i]); | |
1241 | } | |
1242 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1243 | (void *)aup->vaddr, aup->dma_addr); | |
1244 | unregister_netdev(dev); | |
1245 | free_netdev(dev); | |
1246 | release_mem_region( base, MAC_IOSIZE); | |
1247 | release_mem_region(macen, 4); | |
1248 | return NULL; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * Setup the base address and interrupt of the Au1xxx ethernet macs | |
1253 | * based on cpu type and whether the interface is enabled in sys_pinfunc | |
1254 | * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0. | |
1255 | */ | |
1256 | static int __init au1000_init_module(void) | |
1257 | { | |
1258 | int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); | |
1259 | struct net_device *dev; | |
1260 | int i, found_one = 0; | |
1261 | ||
1262 | num_ifs = NUM_ETH_INTERFACES - ni; | |
1263 | ||
1264 | for(i = 0; i < num_ifs; i++) { | |
1265 | dev = au1000_probe(i); | |
1266 | iflist[i].dev = dev; | |
1267 | if (dev) | |
1268 | found_one++; | |
1269 | } | |
1270 | if (!found_one) | |
1271 | return -ENODEV; | |
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static void __exit au1000_cleanup_module(void) | |
1276 | { | |
1277 | int i, j; | |
1278 | struct net_device *dev; | |
1279 | struct au1000_private *aup; | |
1280 | ||
1281 | for (i = 0; i < num_ifs; i++) { | |
1282 | dev = iflist[i].dev; | |
1283 | if (dev) { | |
1284 | aup = netdev_priv(dev); | |
1285 | unregister_netdev(dev); | |
1286 | mdiobus_unregister(aup->mii_bus); | |
1287 | mdiobus_free(aup->mii_bus); | |
1288 | for (j = 0; j < NUM_RX_DMA; j++) | |
1289 | if (aup->rx_db_inuse[j]) | |
1290 | ReleaseDB(aup, aup->rx_db_inuse[j]); | |
1291 | for (j = 0; j < NUM_TX_DMA; j++) | |
1292 | if (aup->tx_db_inuse[j]) | |
1293 | ReleaseDB(aup, aup->tx_db_inuse[j]); | |
1294 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1295 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1296 | (void *)aup->vaddr, aup->dma_addr); | |
1297 | release_mem_region(dev->base_addr, MAC_IOSIZE); | |
1298 | release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4); | |
1299 | free_netdev(dev); | |
1300 | } | |
1301 | } | |
1302 | } | |
1303 | ||
1da177e4 LT |
1304 | module_init(au1000_init_module); |
1305 | module_exit(au1000_cleanup_module); |