2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/percpu.h>
12 #include <asm/processor.h>
17 * Support for Intel Correct Machine Check Interrupts. This allows
18 * the CPU to raise an interrupt when a corrected machine check happened.
19 * Normally we pick those up using a regular polling timer.
20 * Also supports reliable discovery of shared banks.
23 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
26 * cmci_discover_lock protects against parallel discovery attempts
27 * which could race against each other.
29 static DEFINE_SPINLOCK(cmci_discover_lock);
31 #define CMCI_THRESHOLD 1
33 static int cmci_supported(int *banks)
37 if (mce_cmci_disabled || mce_ignore_ce)
41 * Vendor check is not strictly needed, but the initial
42 * initialization is vendor keyed and this
43 * makes sure none of the backdoors are entered otherwise.
45 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
47 if (!cpu_has_apic || lapic_get_maxlvt() < 6)
49 rdmsrl(MSR_IA32_MCG_CAP, cap);
50 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
51 return !!(cap & MCG_CMCI_P);
55 * The interrupt handler. This is called on every event.
56 * Just call the poller directly to log any events.
57 * This could in theory increase the threshold under high load,
58 * but doesn't for now.
60 static void intel_threshold_interrupt(void)
62 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
66 static void print_update(char *type, int *hdr, int num)
69 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
71 printk(KERN_CONT " %s:%d", type, num);
75 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
76 * on this CPU. Use the algorithm recommended in the SDM to discover shared
79 static void cmci_discover(int banks, int boot)
81 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
86 spin_lock_irqsave(&cmci_discover_lock, flags);
87 for (i = 0; i < banks; i++) {
90 if (test_bit(i, owned))
93 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
95 /* Already owned by someone else? */
97 if (test_and_clear_bit(i, owned) || boot)
98 print_update("SHD", &hdr, i);
99 __clear_bit(i, __get_cpu_var(mce_poll_banks));
103 val |= CMCI_EN | CMCI_THRESHOLD;
104 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
105 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
107 /* Did the enable bit stick? -- the bank supports CMCI */
109 if (!test_and_set_bit(i, owned) || boot)
110 print_update("CMCI", &hdr, i);
111 __clear_bit(i, __get_cpu_var(mce_poll_banks));
113 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
116 spin_unlock_irqrestore(&cmci_discover_lock, flags);
118 printk(KERN_CONT "\n");
122 * Just in case we missed an event during initialization check
123 * all the CMCI owned banks.
125 void cmci_recheck(void)
130 if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks))
132 local_irq_save(flags);
133 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
134 local_irq_restore(flags);
138 * Disable CMCI on this CPU for all banks it owns when it goes down.
139 * This allows other CPUs to claim the banks on rediscovery.
141 void cmci_clear(void)
148 if (!cmci_supported(&banks))
150 spin_lock_irqsave(&cmci_discover_lock, flags);
151 for (i = 0; i < banks; i++) {
152 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
155 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
156 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
157 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
158 __clear_bit(i, __get_cpu_var(mce_banks_owned));
160 spin_unlock_irqrestore(&cmci_discover_lock, flags);
164 * After a CPU went down cycle through all the others and rediscover
165 * Must run in process context.
167 void cmci_rediscover(int dying)
173 if (!cmci_supported(&banks))
175 if (!alloc_cpumask_var(&old, GFP_KERNEL))
177 cpumask_copy(old, ¤t->cpus_allowed);
179 for_each_online_cpu(cpu) {
182 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
184 /* Recheck banks in case CPUs don't all have the same */
185 if (cmci_supported(&banks))
186 cmci_discover(banks, 0);
189 set_cpus_allowed_ptr(current, old);
190 free_cpumask_var(old);
194 * Reenable CMCI on this CPU in case a CPU down failed.
196 void cmci_reenable(void)
199 if (cmci_supported(&banks))
200 cmci_discover(banks, 0);
203 static void intel_init_cmci(void)
207 if (!cmci_supported(&banks))
210 mce_threshold_vector = intel_threshold_interrupt;
211 cmci_discover(banks, 1);
213 * For CPU #0 this runs with still disabled APIC, but that's
214 * ok because only the vector is set up. We still do another
215 * check for the banks later for CPU #0 just to make sure
216 * to not miss any events.
218 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
222 void mce_intel_feature_init(struct cpuinfo_x86 *c)
224 intel_init_thermal(c);