2 * Copyright (C) 2001 MandrakeSoft S.A.
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
36 #include <asm/processor.h>
38 #include <asm/current.h>
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
47 #define ioapic_debug(fmt, arg...)
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
55 unsigned long result = 0;
57 switch (ioapic->ioregsel) {
58 case IOAPIC_REG_VERSION:
59 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60 | (IOAPIC_VERSION_ID & 0xff));
63 case IOAPIC_REG_APIC_ID:
64 case IOAPIC_REG_ARB_ID:
65 result = ((ioapic->id & 0xf) << 24);
70 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
73 ASSERT(redir_index < IOAPIC_NUM_PINS);
75 redir_content = ioapic->redirtbl[redir_index].bits;
76 result = (ioapic->ioregsel & 0x1) ?
77 (redir_content >> 32) & 0xffffffff :
78 redir_content & 0xffffffff;
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
88 union kvm_ioapic_redirect_entry *pent;
91 pent = &ioapic->redirtbl[idx];
93 if (!pent->fields.mask) {
94 injected = ioapic_deliver(ioapic, idx);
95 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96 pent->fields.remote_irr = 1;
98 if (!pent->fields.trig_mode)
99 ioapic->irr &= ~(1 << idx);
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
107 bool mask_before, mask_after;
109 switch (ioapic->ioregsel) {
110 case IOAPIC_REG_VERSION:
111 /* Writes are ignored. */
114 case IOAPIC_REG_APIC_ID:
115 ioapic->id = (val >> 24) & 0xf;
118 case IOAPIC_REG_ARB_ID:
122 index = (ioapic->ioregsel - 0x10) >> 1;
124 ioapic_debug("change redir index %x val %x\n", index, val);
125 if (index >= IOAPIC_NUM_PINS)
127 mask_before = ioapic->redirtbl[index].fields.mask;
128 if (ioapic->ioregsel & 1) {
129 ioapic->redirtbl[index].bits &= 0xffffffff;
130 ioapic->redirtbl[index].bits |= (u64) val << 32;
132 ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133 ioapic->redirtbl[index].bits |= (u32) val;
134 ioapic->redirtbl[index].fields.remote_irr = 0;
136 mask_after = ioapic->redirtbl[index].fields.mask;
137 if (mask_before != mask_after)
138 kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139 if (ioapic->irr & (1 << index))
140 ioapic_service(ioapic, index);
145 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
146 struct kvm_vcpu *vcpu,
147 u8 vector, u8 trig_mode, u8 delivery_mode)
149 ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
152 ASSERT((delivery_mode == IOAPIC_FIXED) ||
153 (delivery_mode == IOAPIC_LOWEST_PRIORITY));
155 return kvm_apic_set_irq(vcpu, vector, trig_mode);
158 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
160 kvm_inject_nmi(vcpu);
164 void kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
165 u8 dest_mode, unsigned long *mask)
168 struct kvm *kvm = ioapic->kvm;
169 struct kvm_vcpu *vcpu;
171 ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
174 if (dest_mode == 0) { /* Physical mode. */
175 if (dest == 0xFF) { /* Broadcast. */
176 for (i = 0; i < KVM_MAX_VCPUS; ++i)
177 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
181 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
182 vcpu = kvm->vcpus[i];
185 if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
191 } else if (dest != 0) /* Logical mode, MDA non-zero. */
192 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
193 vcpu = kvm->vcpus[i];
196 if (vcpu->arch.apic &&
197 kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
198 *mask |= 1 << vcpu->vcpu_id;
200 ioapic_debug("mask %x\n", *mask);
203 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
205 union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
206 unsigned long deliver_bitmask;
207 struct kvm_vcpu *vcpu;
210 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
211 "vector=%x trig_mode=%x\n",
212 entry.fields.dest, entry.fields.dest_mode,
213 entry.fields.delivery_mode, entry.fields.vector,
214 entry.fields.trig_mode);
216 kvm_get_intr_delivery_bitmask(ioapic, &entry, &deliver_bitmask);
217 if (!deliver_bitmask) {
218 ioapic_debug("no target on destination\n");
222 /* Always delivery PIT interrupt to vcpu 0 */
228 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
229 if (!(deliver_bitmask & (1 << vcpu_id)))
231 deliver_bitmask &= ~(1 << vcpu_id);
232 vcpu = ioapic->kvm->vcpus[vcpu_id];
234 if (entry.fields.delivery_mode ==
235 IOAPIC_LOWEST_PRIORITY ||
236 entry.fields.delivery_mode == IOAPIC_FIXED) {
239 r += ioapic_inj_irq(ioapic, vcpu,
241 entry.fields.trig_mode,
242 entry.fields.delivery_mode);
243 } else if (entry.fields.delivery_mode == IOAPIC_NMI) {
245 ioapic_inj_nmi(vcpu);
247 ioapic_debug("unsupported delivery mode %x!\n",
248 entry.fields.delivery_mode);
250 ioapic_debug("null destination vcpu: "
251 "mask=%x vector=%x delivery_mode=%x\n",
252 entry.fields.deliver_bitmask,
254 entry.fields.delivery_mode);
259 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
261 u32 old_irr = ioapic->irr;
263 union kvm_ioapic_redirect_entry entry;
266 if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
267 entry = ioapic->redirtbl[irq];
268 level ^= entry.fields.polarity;
270 ioapic->irr &= ~mask;
273 if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
274 || !entry.fields.remote_irr)
275 ret = ioapic_service(ioapic, irq);
281 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
284 union kvm_ioapic_redirect_entry *ent;
286 ent = &ioapic->redirtbl[pin];
288 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
290 if (trigger_mode == IOAPIC_LEVEL_TRIG) {
291 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
292 ent->fields.remote_irr = 0;
293 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
294 ioapic_service(ioapic, pin);
298 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
300 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
303 for (i = 0; i < IOAPIC_NUM_PINS; i++)
304 if (ioapic->redirtbl[i].fields.vector == vector)
305 __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
308 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
309 int len, int is_write)
311 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
313 return ((addr >= ioapic->base_address &&
314 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
317 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
320 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
323 ioapic_debug("addr %lx\n", (unsigned long)addr);
324 ASSERT(!(addr & 0xf)); /* check alignment */
328 case IOAPIC_REG_SELECT:
329 result = ioapic->ioregsel;
332 case IOAPIC_REG_WINDOW:
333 result = ioapic_read_indirect(ioapic, addr, len);
342 *(u64 *) val = result;
347 memcpy(val, (char *)&result, len);
350 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
354 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
357 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
360 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
361 (void*)addr, len, val);
362 ASSERT(!(addr & 0xf)); /* check alignment */
363 if (len == 4 || len == 8)
366 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
372 case IOAPIC_REG_SELECT:
373 ioapic->ioregsel = data;
376 case IOAPIC_REG_WINDOW:
377 ioapic_write_indirect(ioapic, data);
381 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
390 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
394 for (i = 0; i < IOAPIC_NUM_PINS; i++)
395 ioapic->redirtbl[i].fields.mask = 1;
396 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
397 ioapic->ioregsel = 0;
402 int kvm_ioapic_init(struct kvm *kvm)
404 struct kvm_ioapic *ioapic;
406 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
409 kvm->arch.vioapic = ioapic;
410 kvm_ioapic_reset(ioapic);
411 ioapic->dev.read = ioapic_mmio_read;
412 ioapic->dev.write = ioapic_mmio_write;
413 ioapic->dev.in_range = ioapic_in_range;
414 ioapic->dev.private = ioapic;
416 kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);