git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63 static int modparam_nohwcrypt;
  64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  66
  67
  68 /******************\
  69 * Internal defines *
  70 \******************/
  71
  72 /* Module info */
  73 MODULE_AUTHOR("Jiri Slaby");
  74 MODULE_AUTHOR("Nick Kossifidis");
  75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  79
  80
  81 /* Known PCI ids */
  82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  83         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  84         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  85         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  86         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  87         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  88         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  89         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  90         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  91         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  95         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  96         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  97         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  98         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  99         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
 100         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
 101         { 0 }
 102 };
 103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 104
 105 /* Known SREVs */
 106 static struct ath5k_srev_name srev_names[] = {
 107         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 108         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 109         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 110         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 111         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 112         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 113         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 114         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 115         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 116         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 117         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 118         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 119         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 120         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 121         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 122         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 123         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 124         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 125         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 126         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 127         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 128         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 129         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 130         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 131         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 132         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 133         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 134         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 135         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 136         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 137         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 138         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 139         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 140         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 141         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 142         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 143 };
 144
 145 static struct ieee80211_rate ath5k_rates[] = {
 146         { .bitrate = 10,
 147           .hw_value = ATH5K_RATE_CODE_1M, },
 148         { .bitrate = 20,
 149           .hw_value = ATH5K_RATE_CODE_2M,
 150           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 151           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 152         { .bitrate = 55,
 153           .hw_value = ATH5K_RATE_CODE_5_5M,
 154           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 155           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 156         { .bitrate = 110,
 157           .hw_value = ATH5K_RATE_CODE_11M,
 158           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 159           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 160         { .bitrate = 60,
 161           .hw_value = ATH5K_RATE_CODE_6M,
 162           .flags = 0 },
 163         { .bitrate = 90,
 164           .hw_value = ATH5K_RATE_CODE_9M,
 165           .flags = 0 },
 166         { .bitrate = 120,
 167           .hw_value = ATH5K_RATE_CODE_12M,
 168           .flags = 0 },
 169         { .bitrate = 180,
 170           .hw_value = ATH5K_RATE_CODE_18M,
 171           .flags = 0 },
 172         { .bitrate = 240,
 173           .hw_value = ATH5K_RATE_CODE_24M,
 174           .flags = 0 },
 175         { .bitrate = 360,
 176           .hw_value = ATH5K_RATE_CODE_36M,
 177           .flags = 0 },
 178         { .bitrate = 480,
 179           .hw_value = ATH5K_RATE_CODE_48M,
 180           .flags = 0 },
 181         { .bitrate = 540,
 182           .hw_value = ATH5K_RATE_CODE_54M,
 183           .flags = 0 },
 184         /* XR missing */
 185 };
 186
 187 /*
 188  * Prototypes - PCI stack related functions
 189  */
 190 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 191                                 const struct pci_device_id *id);
 192 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 193 #ifdef CONFIG_PM
 194 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 195                                         pm_message_t state);
 196 static int              ath5k_pci_resume(struct pci_dev *pdev);
 197 #else
 198 #define ath5k_pci_suspend NULL
 199 #define ath5k_pci_resume NULL
 200 #endif /* CONFIG_PM */
 201
 202 static struct pci_driver ath5k_pci_driver = {
 203         .name           = KBUILD_MODNAME,
 204         .id_table       = ath5k_pci_id_table,
 205         .probe          = ath5k_pci_probe,
 206         .remove         = __devexit_p(ath5k_pci_remove),
 207         .suspend        = ath5k_pci_suspend,
 208         .resume         = ath5k_pci_resume,
 209 };
 210
 211
 212
 213 /*
 214  * Prototypes - MAC 802.11 stack related functions
 215  */
 216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 218 static int ath5k_reset_wake(struct ath5k_softc *sc);
 219 static int ath5k_start(struct ieee80211_hw *hw);
 220 static void ath5k_stop(struct ieee80211_hw *hw);
 221 static int ath5k_add_interface(struct ieee80211_hw *hw,
 222                 struct ieee80211_if_init_conf *conf);
 223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 224                 struct ieee80211_if_init_conf *conf);
 225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
 226 static int ath5k_config_interface(struct ieee80211_hw *hw,
 227                 struct ieee80211_vif *vif,
 228                 struct ieee80211_if_conf *conf);
 229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 230                 unsigned int changed_flags,
 231                 unsigned int *new_flags,
 232                 int mc_count, struct dev_mc_list *mclist);
 233 static int ath5k_set_key(struct ieee80211_hw *hw,
 234                 enum set_key_cmd cmd,
 235                 const u8 *local_addr, const u8 *addr,
 236                 struct ieee80211_key_conf *key);
 237 static int ath5k_get_stats(struct ieee80211_hw *hw,
 238                 struct ieee80211_low_level_stats *stats);
 239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 240                 struct ieee80211_tx_queue_stats *stats);
 241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 242 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 243 static int ath5k_beacon_update(struct ath5k_softc *sc,
 244                 struct sk_buff *skb);
 245 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
 246                 struct ieee80211_vif *vif,
 247                 struct ieee80211_bss_conf *bss_conf,
 248                 u32 changes);
 249
 250 static struct ieee80211_ops ath5k_hw_ops = {
 251         .tx             = ath5k_tx,
 252         .start          = ath5k_start,
 253         .stop           = ath5k_stop,
 254         .add_interface  = ath5k_add_interface,
 255         .remove_interface = ath5k_remove_interface,
 256         .config         = ath5k_config,
 257         .config_interface = ath5k_config_interface,
 258         .configure_filter = ath5k_configure_filter,
 259         .set_key        = ath5k_set_key,
 260         .get_stats      = ath5k_get_stats,
 261         .conf_tx        = NULL,
 262         .get_tx_stats   = ath5k_get_tx_stats,
 263         .get_tsf        = ath5k_get_tsf,
 264         .reset_tsf      = ath5k_reset_tsf,
 265         .bss_info_changed = ath5k_bss_info_changed,
 266 };
 267
 268 /*
 269  * Prototypes - Internal functions
 270  */
 271 /* Attach detach */
 272 static int      ath5k_attach(struct pci_dev *pdev,
 273                         struct ieee80211_hw *hw);
 274 static void     ath5k_detach(struct pci_dev *pdev,
 275                         struct ieee80211_hw *hw);
 276 /* Channel/mode setup */
 277 static inline short ath5k_ieee2mhz(short chan);
 278 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 279                                 struct ieee80211_channel *channels,
 280                                 unsigned int mode,
 281                                 unsigned int max);
 282 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 283 static int      ath5k_chan_set(struct ath5k_softc *sc,
 284                                 struct ieee80211_channel *chan);
 285 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 286                                 unsigned int mode);
 287 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 288
 289 /* Descriptor setup */
 290 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 291                                 struct pci_dev *pdev);
 292 static void     ath5k_desc_free(struct ath5k_softc *sc,
 293                                 struct pci_dev *pdev);
 294 /* Buffers setup */
 295 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 296                                 struct ath5k_buf *bf);
 297 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 298                                 struct ath5k_buf *bf);
 299 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 300                                 struct ath5k_buf *bf)
 301 {
 302         BUG_ON(!bf);
 303         if (!bf->skb)
 304                 return;
 305         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 306                         PCI_DMA_TODEVICE);
 307         dev_kfree_skb_any(bf->skb);
 308         bf->skb = NULL;
 309 }
 310
 311 /* Queues setup */
 312 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 313                                 int qtype, int subtype);
 314 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 315 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 316 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 317                                 struct ath5k_txq *txq);
 318 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 319 static void     ath5k_txq_release(struct ath5k_softc *sc);
 320 /* Rx handling */
 321 static int      ath5k_rx_start(struct ath5k_softc *sc);
 322 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 323 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 324                                         struct ath5k_desc *ds,
 325                                         struct sk_buff *skb,
 326                                         struct ath5k_rx_status *rs);
 327 static void     ath5k_tasklet_rx(unsigned long data);
 328 /* Tx handling */
 329 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 330                                 struct ath5k_txq *txq);
 331 static void     ath5k_tasklet_tx(unsigned long data);
 332 /* Beacon handling */
 333 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 334                                         struct ath5k_buf *bf);
 335 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 336 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 337 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 338
 339 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 340 {
 341         u64 tsf = ath5k_hw_get_tsf64(ah);
 342
 343         if ((tsf & 0x7fff) < rstamp)
 344                 tsf -= 0x8000;
 345
 346         return (tsf & ~0x7fff) | rstamp;
 347 }
 348
 349 /* Interrupt handling */
 350 static int      ath5k_init(struct ath5k_softc *sc, bool is_resume);
 351 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 352 static int      ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
 353 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 354 static void     ath5k_tasklet_reset(unsigned long data);
 355
 356 static void     ath5k_calibrate(unsigned long data);
 357 /* LED functions */
 358 static int      ath5k_init_leds(struct ath5k_softc *sc);
 359 static void     ath5k_led_enable(struct ath5k_softc *sc);
 360 static void     ath5k_led_off(struct ath5k_softc *sc);
 361 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 362
 363 /*
 364  * Module init/exit functions
 365  */
 366 static int __init
 367 init_ath5k_pci(void)
 368 {
 369         int ret;
 370
 371         ath5k_debug_init();
 372
 373         ret = pci_register_driver(&ath5k_pci_driver);
 374         if (ret) {
 375                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 376                 return ret;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static void __exit
 383 exit_ath5k_pci(void)
 384 {
 385         pci_unregister_driver(&ath5k_pci_driver);
 386
 387         ath5k_debug_finish();
 388 }
 389
 390 module_init(init_ath5k_pci);
 391 module_exit(exit_ath5k_pci);
 392
 393
 394 /********************\
 395 * PCI Initialization *
 396 \********************/
 397
 398 static const char *
 399 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 400 {
 401         const char *name = "xxxxx";
 402         unsigned int i;
 403
 404         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 405                 if (srev_names[i].sr_type != type)
 406                         continue;
 407
 408                 if ((val & 0xf0) == srev_names[i].sr_val)
 409                         name = srev_names[i].sr_name;
 410
 411                 if ((val & 0xff) == srev_names[i].sr_val) {
 412                         name = srev_names[i].sr_name;
 413                         break;
 414                 }
 415         }
 416
 417         return name;
 418 }
 419
 420 static int __devinit
 421 ath5k_pci_probe(struct pci_dev *pdev,
 422                 const struct pci_device_id *id)
 423 {
 424         void __iomem *mem;
 425         struct ath5k_softc *sc;
 426         struct ieee80211_hw *hw;
 427         int ret;
 428         u8 csz;
 429
 430         ret = pci_enable_device(pdev);
 431         if (ret) {
 432                 dev_err(&pdev->dev, "can't enable device\n");
 433                 goto err;
 434         }
 435
 436         /* XXX 32-bit addressing only */
 437         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 438         if (ret) {
 439                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 440                 goto err_dis;
 441         }
 442
 443         /*
 444          * Cache line size is used to size and align various
 445          * structures used to communicate with the hardware.
 446          */
 447         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 448         if (csz == 0) {
 449                 /*
 450                  * Linux 2.4.18 (at least) writes the cache line size
 451                  * register as a 16-bit wide register which is wrong.
 452                  * We must have this setup properly for rx buffer
 453                  * DMA to work so force a reasonable value here if it
 454                  * comes up zero.
 455                  */
 456                 csz = L1_CACHE_BYTES / sizeof(u32);
 457                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 458         }
 459         /*
 460          * The default setting of latency timer yields poor results,
 461          * set it to the value used by other systems.  It may be worth
 462          * tweaking this setting more.
 463          */
 464         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 465
 466         /* Enable bus mastering */
 467         pci_set_master(pdev);
 468
 469         /*
 470          * Disable the RETRY_TIMEOUT register (0x41) to keep
 471          * PCI Tx retries from interfering with C3 CPU state.
 472          */
 473         pci_write_config_byte(pdev, 0x41, 0);
 474
 475         ret = pci_request_region(pdev, 0, "ath5k");
 476         if (ret) {
 477                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 478                 goto err_dis;
 479         }
 480
 481         mem = pci_iomap(pdev, 0, 0);
 482         if (!mem) {
 483                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 484                 ret = -EIO;
 485                 goto err_reg;
 486         }
 487
 488         /*
 489          * Allocate hw (mac80211 main struct)
 490          * and hw->priv (driver private data)
 491          */
 492         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 493         if (hw == NULL) {
 494                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 495                 ret = -ENOMEM;
 496                 goto err_map;
 497         }
 498
 499         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 500
 501         /* Initialize driver private data */
 502         SET_IEEE80211_DEV(hw, &pdev->dev);
 503         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 504                     IEEE80211_HW_SIGNAL_DBM |
 505                     IEEE80211_HW_NOISE_DBM;
 506
 507         hw->wiphy->interface_modes =
 508                 BIT(NL80211_IFTYPE_STATION) |
 509                 BIT(NL80211_IFTYPE_ADHOC) |
 510                 BIT(NL80211_IFTYPE_MESH_POINT);
 511
 512         hw->extra_tx_headroom = 2;
 513         hw->channel_change_time = 5000;
 514         sc = hw->priv;
 515         sc->hw = hw;
 516         sc->pdev = pdev;
 517
 518         ath5k_debug_init_device(sc);
 519
 520         /*
 521          * Mark the device as detached to avoid processing
 522          * interrupts until setup is complete.
 523          */
 524         __set_bit(ATH_STAT_INVALID, sc->status);
 525
 526         sc->iobase = mem; /* So we can unmap it on detach */
 527         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 528         sc->opmode = NL80211_IFTYPE_STATION;
 529         mutex_init(&sc->lock);
 530         spin_lock_init(&sc->rxbuflock);
 531         spin_lock_init(&sc->txbuflock);
 532         spin_lock_init(&sc->block);
 533
 534         /* Set private data */
 535         pci_set_drvdata(pdev, hw);
 536
 537         /* Setup interrupt handler */
 538         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 539         if (ret) {
 540                 ATH5K_ERR(sc, "request_irq failed\n");
 541                 goto err_free;
 542         }
 543
 544         /* Initialize device */
 545         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 546         if (IS_ERR(sc->ah)) {
 547                 ret = PTR_ERR(sc->ah);
 548                 goto err_irq;
 549         }
 550
 551         /* set up multi-rate retry capabilities */
 552         if (sc->ah->ah_version == AR5K_AR5212) {
 553                 hw->max_rates = 4;
 554                 hw->max_rate_tries = 11;
 555         }
 556
 557         /* Finish private driver data initialization */
 558         ret = ath5k_attach(pdev, hw);
 559         if (ret)
 560                 goto err_ah;
 561
 562         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 563                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 564                                         sc->ah->ah_mac_srev,
 565                                         sc->ah->ah_phy_revision);
 566
 567         if (!sc->ah->ah_single_chip) {
 568                 /* Single chip radio (!RF5111) */
 569                 if (sc->ah->ah_radio_5ghz_revision &&
 570                         !sc->ah->ah_radio_2ghz_revision) {
 571                         /* No 5GHz support -> report 2GHz radio */
 572                         if (!test_bit(AR5K_MODE_11A,
 573                                 sc->ah->ah_capabilities.cap_mode)) {
 574                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 575                                         ath5k_chip_name(AR5K_VERSION_RAD,
 576                                                 sc->ah->ah_radio_5ghz_revision),
 577                                                 sc->ah->ah_radio_5ghz_revision);
 578                         /* No 2GHz support (5110 and some
 579                          * 5Ghz only cards) -> report 5Ghz radio */
 580                         } else if (!test_bit(AR5K_MODE_11B,
 581                                 sc->ah->ah_capabilities.cap_mode)) {
 582                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 583                                         ath5k_chip_name(AR5K_VERSION_RAD,
 584                                                 sc->ah->ah_radio_5ghz_revision),
 585                                                 sc->ah->ah_radio_5ghz_revision);
 586                         /* Multiband radio */
 587                         } else {
 588                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 589                                         " (0x%x)\n",
 590                                         ath5k_chip_name(AR5K_VERSION_RAD,
 591                                                 sc->ah->ah_radio_5ghz_revision),
 592                                                 sc->ah->ah_radio_5ghz_revision);
 593                         }
 594                 }
 595                 /* Multi chip radio (RF5111 - RF2111) ->
 596                  * report both 2GHz/5GHz radios */
 597                 else if (sc->ah->ah_radio_5ghz_revision &&
 598                                 sc->ah->ah_radio_2ghz_revision){
 599                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 600                                 ath5k_chip_name(AR5K_VERSION_RAD,
 601                                         sc->ah->ah_radio_5ghz_revision),
 602                                         sc->ah->ah_radio_5ghz_revision);
 603                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 604                                 ath5k_chip_name(AR5K_VERSION_RAD,
 605                                         sc->ah->ah_radio_2ghz_revision),
 606                                         sc->ah->ah_radio_2ghz_revision);
 607                 }
 608         }
 609
 610
 611         /* ready to process interrupts */
 612         __clear_bit(ATH_STAT_INVALID, sc->status);
 613
 614         return 0;
 615 err_ah:
 616         ath5k_hw_detach(sc->ah);
 617 err_irq:
 618         free_irq(pdev->irq, sc);
 619 err_free:
 620         ieee80211_free_hw(hw);
 621 err_map:
 622         pci_iounmap(pdev, mem);
 623 err_reg:
 624         pci_release_region(pdev, 0);
 625 err_dis:
 626         pci_disable_device(pdev);
 627 err:
 628         return ret;
 629 }
 630
 631 static void __devexit
 632 ath5k_pci_remove(struct pci_dev *pdev)
 633 {
 634         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 635         struct ath5k_softc *sc = hw->priv;
 636
 637         ath5k_debug_finish_device(sc);
 638         ath5k_detach(pdev, hw);
 639         ath5k_hw_detach(sc->ah);
 640         free_irq(pdev->irq, sc);
 641         pci_iounmap(pdev, sc->iobase);
 642         pci_release_region(pdev, 0);
 643         pci_disable_device(pdev);
 644         ieee80211_free_hw(hw);
 645 }
 646
 647 #ifdef CONFIG_PM
 648 static int
 649 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 650 {
 651         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 652         struct ath5k_softc *sc = hw->priv;
 653
 654         ath5k_led_off(sc);
 655
 656         ath5k_stop_hw(sc, true);
 657
 658         free_irq(pdev->irq, sc);
 659         pci_save_state(pdev);
 660         pci_disable_device(pdev);
 661         pci_set_power_state(pdev, PCI_D3hot);
 662
 663         return 0;
 664 }
 665
 666 static int
 667 ath5k_pci_resume(struct pci_dev *pdev)
 668 {
 669         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 670         struct ath5k_softc *sc = hw->priv;
 671         int err;
 672
 673         pci_restore_state(pdev);
 674
 675         err = pci_enable_device(pdev);
 676         if (err)
 677                 return err;
 678
 679         /*
 680          * Suspend/Resume resets the PCI configuration space, so we have to
 681          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 682          * PCI Tx retries from interfering with C3 CPU state
 683          */
 684         pci_write_config_byte(pdev, 0x41, 0);
 685
 686         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 687         if (err) {
 688                 ATH5K_ERR(sc, "request_irq failed\n");
 689                 goto err_no_irq;
 690         }
 691
 692         err = ath5k_init(sc, true);
 693         if (err)
 694                 goto err_irq;
 695         ath5k_led_enable(sc);
 696
 697         return 0;
 698 err_irq:
 699         free_irq(pdev->irq, sc);
 700 err_no_irq:
 701         pci_disable_device(pdev);
 702         return err;
 703 }
 704 #endif /* CONFIG_PM */
 705
 706
 707 /***********************\
 708 * Driver Initialization *
 709 \***********************/
 710
 711 static int
 712 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 713 {
 714         struct ath5k_softc *sc = hw->priv;
 715         struct ath5k_hw *ah = sc->ah;
 716         u8 mac[ETH_ALEN] = {};
 717         int ret;
 718
 719         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 720
 721         /*
 722          * Check if the MAC has multi-rate retry support.
 723          * We do this by trying to setup a fake extended
 724          * descriptor.  MAC's that don't have support will
 725          * return false w/o doing anything.  MAC's that do
 726          * support it will return true w/o doing anything.
 727          */
 728         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 729         if (ret < 0)
 730                 goto err;
 731         if (ret > 0)
 732                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 733
 734         /*
 735          * Collect the channel list.  The 802.11 layer
 736          * is resposible for filtering this list based
 737          * on settings like the phy mode and regulatory
 738          * domain restrictions.
 739          */
 740         ret = ath5k_setup_bands(hw);
 741         if (ret) {
 742                 ATH5K_ERR(sc, "can't get channels\n");
 743                 goto err;
 744         }
 745
 746         /* NB: setup here so ath5k_rate_update is happy */
 747         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 748                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 749         else
 750                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 751
 752         /*
 753          * Allocate tx+rx descriptors and populate the lists.
 754          */
 755         ret = ath5k_desc_alloc(sc, pdev);
 756         if (ret) {
 757                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 758                 goto err;
 759         }
 760
 761         /*
 762          * Allocate hardware transmit queues: one queue for
 763          * beacon frames and one data queue for each QoS
 764          * priority.  Note that hw functions handle reseting
 765          * these queues at the needed time.
 766          */
 767         ret = ath5k_beaconq_setup(ah);
 768         if (ret < 0) {
 769                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 770                 goto err_desc;
 771         }
 772         sc->bhalq = ret;
 773
 774         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 775         if (IS_ERR(sc->txq)) {
 776                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 777                 ret = PTR_ERR(sc->txq);
 778                 goto err_bhal;
 779         }
 780
 781         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 782         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 783         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 784         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 785
 786         ret = ath5k_eeprom_read_mac(ah, mac);
 787         if (ret) {
 788                 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
 789                         sc->pdev->device);
 790                 goto err_queues;
 791         }
 792
 793         SET_IEEE80211_PERM_ADDR(hw, mac);
 794         /* All MAC address bits matter for ACKs */
 795         memset(sc->bssidmask, 0xff, ETH_ALEN);
 796         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 797
 798         ret = ieee80211_register_hw(hw);
 799         if (ret) {
 800                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 801                 goto err_queues;
 802         }
 803
 804         ath5k_init_leds(sc);
 805
 806         return 0;
 807 err_queues:
 808         ath5k_txq_release(sc);
 809 err_bhal:
 810         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 811 err_desc:
 812         ath5k_desc_free(sc, pdev);
 813 err:
 814         return ret;
 815 }
 816
 817 static void
 818 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 819 {
 820         struct ath5k_softc *sc = hw->priv;
 821
 822         /*
 823          * NB: the order of these is important:
 824          * o call the 802.11 layer before detaching ath5k_hw to
 825          *   insure callbacks into the driver to delete global
 826          *   key cache entries can be handled
 827          * o reclaim the tx queue data structures after calling
 828          *   the 802.11 layer as we'll get called back to reclaim
 829          *   node state and potentially want to use them
 830          * o to cleanup the tx queues the hal is called, so detach
 831          *   it last
 832          * XXX: ??? detach ath5k_hw ???
 833          * Other than that, it's straightforward...
 834          */
 835         ieee80211_unregister_hw(hw);
 836         ath5k_desc_free(sc, pdev);
 837         ath5k_txq_release(sc);
 838         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 839         ath5k_unregister_leds(sc);
 840
 841         /*
 842          * NB: can't reclaim these until after ieee80211_ifdetach
 843          * returns because we'll get called back to reclaim node
 844          * state and potentially want to use them.
 845          */
 846 }
 847
 848
 849
 850
 851 /********************\
 852 * Channel/mode setup *
 853 \********************/
 854
 855 /*
 856  * Convert IEEE channel number to MHz frequency.
 857  */
 858 static inline short
 859 ath5k_ieee2mhz(short chan)
 860 {
 861         if (chan <= 14 || chan >= 27)
 862                 return ieee80211chan2mhz(chan);
 863         else
 864                 return 2212 + chan * 20;
 865 }
 866
 867 static unsigned int
 868 ath5k_copy_channels(struct ath5k_hw *ah,
 869                 struct ieee80211_channel *channels,
 870                 unsigned int mode,
 871                 unsigned int max)
 872 {
 873         unsigned int i, count, size, chfreq, freq, ch;
 874
 875         if (!test_bit(mode, ah->ah_modes))
 876                 return 0;
 877
 878         switch (mode) {
 879         case AR5K_MODE_11A:
 880         case AR5K_MODE_11A_TURBO:
 881                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 882                 size = 220 ;
 883                 chfreq = CHANNEL_5GHZ;
 884                 break;
 885         case AR5K_MODE_11B:
 886         case AR5K_MODE_11G:
 887         case AR5K_MODE_11G_TURBO:
 888                 size = 26;
 889                 chfreq = CHANNEL_2GHZ;
 890                 break;
 891         default:
 892                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 893                 return 0;
 894         }
 895
 896         for (i = 0, count = 0; i < size && max > 0; i++) {
 897                 ch = i + 1 ;
 898                 freq = ath5k_ieee2mhz(ch);
 899
 900                 /* Check if channel is supported by the chipset */
 901                 if (!ath5k_channel_ok(ah, freq, chfreq))
 902                         continue;
 903
 904                 /* Write channel info and increment counter */
 905                 channels[count].center_freq = freq;
 906                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 907                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 908                 switch (mode) {
 909                 case AR5K_MODE_11A:
 910                 case AR5K_MODE_11G:
 911                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 912                         break;
 913                 case AR5K_MODE_11A_TURBO:
 914                 case AR5K_MODE_11G_TURBO:
 915                         channels[count].hw_value = chfreq |
 916                                 CHANNEL_OFDM | CHANNEL_TURBO;
 917                         break;
 918                 case AR5K_MODE_11B:
 919                         channels[count].hw_value = CHANNEL_B;
 920                 }
 921
 922                 count++;
 923                 max--;
 924         }
 925
 926         return count;
 927 }
 928
 929 static void
 930 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 931 {
 932         u8 i;
 933
 934         for (i = 0; i < AR5K_MAX_RATES; i++)
 935                 sc->rate_idx[b->band][i] = -1;
 936
 937         for (i = 0; i < b->n_bitrates; i++) {
 938                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 939                 if (b->bitrates[i].hw_value_short)
 940                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 941         }
 942 }
 943
 944 static int
 945 ath5k_setup_bands(struct ieee80211_hw *hw)
 946 {
 947         struct ath5k_softc *sc = hw->priv;
 948         struct ath5k_hw *ah = sc->ah;
 949         struct ieee80211_supported_band *sband;
 950         int max_c, count_c = 0;
 951         int i;
 952
 953         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 954         max_c = ARRAY_SIZE(sc->channels);
 955
 956         /* 2GHz band */
 957         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 958         sband->band = IEEE80211_BAND_2GHZ;
 959         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 960
 961         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 962                 /* G mode */
 963                 memcpy(sband->bitrates, &ath5k_rates[0],
 964                        sizeof(struct ieee80211_rate) * 12);
 965                 sband->n_bitrates = 12;
 966
 967                 sband->channels = sc->channels;
 968                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 969                                         AR5K_MODE_11G, max_c);
 970
 971                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 972                 count_c = sband->n_channels;
 973                 max_c -= count_c;
 974         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 975                 /* B mode */
 976                 memcpy(sband->bitrates, &ath5k_rates[0],
 977                        sizeof(struct ieee80211_rate) * 4);
 978                 sband->n_bitrates = 4;
 979
 980                 /* 5211 only supports B rates and uses 4bit rate codes
 981                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 982                  * fix them up here:
 983                  */
 984                 if (ah->ah_version == AR5K_AR5211) {
 985                         for (i = 0; i < 4; i++) {
 986                                 sband->bitrates[i].hw_value =
 987                                         sband->bitrates[i].hw_value & 0xF;
 988                                 sband->bitrates[i].hw_value_short =
 989                                         sband->bitrates[i].hw_value_short & 0xF;
 990                         }
 991                 }
 992
 993                 sband->channels = sc->channels;
 994                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 995                                         AR5K_MODE_11B, max_c);
 996
 997                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 998                 count_c = sband->n_channels;
 999                 max_c -= count_c;
1000         }
1001         ath5k_setup_rate_idx(sc, sband);
1002
1003         /* 5GHz band, A mode */
1004         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1005                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1006                 sband->band = IEEE80211_BAND_5GHZ;
1007                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1008
1009                 memcpy(sband->bitrates, &ath5k_rates[4],
1010                        sizeof(struct ieee80211_rate) * 8);
1011                 sband->n_bitrates = 8;
1012
1013                 sband->channels = &sc->channels[count_c];
1014                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1015                                         AR5K_MODE_11A, max_c);
1016
1017                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1018         }
1019         ath5k_setup_rate_idx(sc, sband);
1020
1021         ath5k_debug_dump_bands(sc);
1022
1023         return 0;
1024 }
1025
1026 /*
1027  * Set/change channels.  If the channel is really being changed,
1028  * it's done by reseting the chip.  To accomplish this we must
1029  * first cleanup any pending DMA, then restart stuff after a la
1030  * ath5k_init.
1031  */
1032 static int
1033 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034 {
1035         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036                 sc->curchan->center_freq, chan->center_freq);
1037
1038         if (chan->center_freq != sc->curchan->center_freq ||
1039                 chan->hw_value != sc->curchan->hw_value) {
1040
1041                 sc->curchan = chan;
1042                 sc->curband = &sc->sbands[chan->band];
1043
1044                 /*
1045                  * To switch channels clear any pending DMA operations;
1046                  * wait long enough for the RX fifo to drain, reset the
1047                  * hardware at the new frequency, and then re-enable
1048                  * the relevant bits of the h/w.
1049                  */
1050                 return ath5k_reset(sc, true, true);
1051         }
1052
1053         return 0;
1054 }
1055
1056 static void
1057 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1058 {
1059         sc->curmode = mode;
1060
1061         if (mode == AR5K_MODE_11A) {
1062                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1063         } else {
1064                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1065         }
1066 }
1067
1068 static void
1069 ath5k_mode_setup(struct ath5k_softc *sc)
1070 {
1071         struct ath5k_hw *ah = sc->ah;
1072         u32 rfilt;
1073
1074         /* configure rx filter */
1075         rfilt = sc->filter_flags;
1076         ath5k_hw_set_rx_filter(ah, rfilt);
1077
1078         if (ath5k_hw_hasbssidmask(ah))
1079                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1080
1081         /* configure operational mode */
1082         ath5k_hw_set_opmode(ah);
1083
1084         ath5k_hw_set_mcast_filter(ah, 0, 0);
1085         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1086 }
1087
1088 static inline int
1089 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1090 {
1091         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1092         return sc->rate_idx[sc->curband->band][hw_rix];
1093 }
1094
1095 /***************\
1096 * Buffers setup *
1097 \***************/
1098
1099 static int
1100 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1101 {
1102         struct ath5k_hw *ah = sc->ah;
1103         struct sk_buff *skb = bf->skb;
1104         struct ath5k_desc *ds;
1105
1106         if (likely(skb == NULL)) {
1107                 unsigned int off;
1108
1109                 /*
1110                  * Allocate buffer with headroom_needed space for the
1111                  * fake physical layer header at the start.
1112                  */
1113                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1114                 if (unlikely(skb == NULL)) {
1115                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1116                                         sc->rxbufsize + sc->cachelsz - 1);
1117                         return -ENOMEM;
1118                 }
1119                 /*
1120                  * Cache-line-align.  This is important (for the
1121                  * 5210 at least) as not doing so causes bogus data
1122                  * in rx'd frames.
1123                  */
1124                 off = ((unsigned long)skb->data) % sc->cachelsz;
1125                 if (off != 0)
1126                         skb_reserve(skb, sc->cachelsz - off);
1127
1128                 bf->skb = skb;
1129                 bf->skbaddr = pci_map_single(sc->pdev,
1130                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1131                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1132                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1133                         dev_kfree_skb(skb);
1134                         bf->skb = NULL;
1135                         return -ENOMEM;
1136                 }
1137         }
1138
1139         /*
1140          * Setup descriptors.  For receive we always terminate
1141          * the descriptor list with a self-linked entry so we'll
1142          * not get overrun under high load (as can happen with a
1143          * 5212 when ANI processing enables PHY error frames).
1144          *
1145          * To insure the last descriptor is self-linked we create
1146          * each descriptor as self-linked and add it to the end.  As
1147          * each additional descriptor is added the previous self-linked
1148          * entry is ``fixed'' naturally.  This should be safe even
1149          * if DMA is happening.  When processing RX interrupts we
1150          * never remove/process the last, self-linked, entry on the
1151          * descriptor list.  This insures the hardware always has
1152          * someplace to write a new frame.
1153          */
1154         ds = bf->desc;
1155         ds->ds_link = bf->daddr;        /* link to self */
1156         ds->ds_data = bf->skbaddr;
1157         ah->ah_setup_rx_desc(ah, ds,
1158                 skb_tailroom(skb),      /* buffer size */
1159                 0);
1160
1161         if (sc->rxlink != NULL)
1162                 *sc->rxlink = bf->daddr;
1163         sc->rxlink = &ds->ds_link;
1164         return 0;
1165 }
1166
1167 static int
1168 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1169 {
1170         struct ath5k_hw *ah = sc->ah;
1171         struct ath5k_txq *txq = sc->txq;
1172         struct ath5k_desc *ds = bf->desc;
1173         struct sk_buff *skb = bf->skb;
1174         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1175         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1176         struct ieee80211_rate *rate;
1177         unsigned int mrr_rate[3], mrr_tries[3];
1178         int i, ret;
1179
1180         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1181
1182         /* XXX endianness */
1183         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1184                         PCI_DMA_TODEVICE);
1185
1186         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1187                 flags |= AR5K_TXDESC_NOACK;
1188
1189         pktlen = skb->len;
1190
1191         if (info->control.hw_key) {
1192                 keyidx = info->control.hw_key->hw_key_idx;
1193                 pktlen += info->control.hw_key->icv_len;
1194         }
1195         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1196                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1197                 (sc->power_level * 2),
1198                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1199                 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
1200         if (ret)
1201                 goto err_unmap;
1202
1203         memset(mrr_rate, 0, sizeof(mrr_rate));
1204         memset(mrr_tries, 0, sizeof(mrr_tries));
1205         for (i = 0; i < 3; i++) {
1206                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1207                 if (!rate)
1208                         break;
1209
1210                 mrr_rate[i] = rate->hw_value;
1211                 mrr_tries[i] = info->control.rates[i + 1].count;
1212         }
1213
1214         ah->ah_setup_mrr_tx_desc(ah, ds,
1215                 mrr_rate[0], mrr_tries[0],
1216                 mrr_rate[1], mrr_tries[1],
1217                 mrr_rate[2], mrr_tries[2]);
1218
1219         ds->ds_link = 0;
1220         ds->ds_data = bf->skbaddr;
1221
1222         spin_lock_bh(&txq->lock);
1223         list_add_tail(&bf->list, &txq->q);
1224         sc->tx_stats[txq->qnum].len++;
1225         if (txq->link == NULL) /* is this first packet? */
1226                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1227         else /* no, so only link it */
1228                 *txq->link = bf->daddr;
1229
1230         txq->link = &ds->ds_link;
1231         ath5k_hw_start_tx_dma(ah, txq->qnum);
1232         mmiowb();
1233         spin_unlock_bh(&txq->lock);
1234
1235         return 0;
1236 err_unmap:
1237         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1238         return ret;
1239 }
1240
1241 /*******************\
1242 * Descriptors setup *
1243 \*******************/
1244
1245 static int
1246 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1247 {
1248         struct ath5k_desc *ds;
1249         struct ath5k_buf *bf;
1250         dma_addr_t da;
1251         unsigned int i;
1252         int ret;
1253
1254         /* allocate descriptors */
1255         sc->desc_len = sizeof(struct ath5k_desc) *
1256                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1257         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1258         if (sc->desc == NULL) {
1259                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1260                 ret = -ENOMEM;
1261                 goto err;
1262         }
1263         ds = sc->desc;
1264         da = sc->desc_daddr;
1265         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1266                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1267
1268         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1269                         sizeof(struct ath5k_buf), GFP_KERNEL);
1270         if (bf == NULL) {
1271                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1272                 ret = -ENOMEM;
1273                 goto err_free;
1274         }
1275         sc->bufptr = bf;
1276
1277         INIT_LIST_HEAD(&sc->rxbuf);
1278         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1279                 bf->desc = ds;
1280                 bf->daddr = da;
1281                 list_add_tail(&bf->list, &sc->rxbuf);
1282         }
1283
1284         INIT_LIST_HEAD(&sc->txbuf);
1285         sc->txbuf_len = ATH_TXBUF;
1286         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1287                         da += sizeof(*ds)) {
1288                 bf->desc = ds;
1289                 bf->daddr = da;
1290                 list_add_tail(&bf->list, &sc->txbuf);
1291         }
1292
1293         /* beacon buffer */
1294         bf->desc = ds;
1295         bf->daddr = da;
1296         sc->bbuf = bf;
1297
1298         return 0;
1299 err_free:
1300         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1301 err:
1302         sc->desc = NULL;
1303         return ret;
1304 }
1305
1306 static void
1307 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1308 {
1309         struct ath5k_buf *bf;
1310
1311         ath5k_txbuf_free(sc, sc->bbuf);
1312         list_for_each_entry(bf, &sc->txbuf, list)
1313                 ath5k_txbuf_free(sc, bf);
1314         list_for_each_entry(bf, &sc->rxbuf, list)
1315                 ath5k_txbuf_free(sc, bf);
1316
1317         /* Free memory associated with all descriptors */
1318         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1319
1320         kfree(sc->bufptr);
1321         sc->bufptr = NULL;
1322 }
1323
1324
1325
1326
1327
1328 /**************\
1329 * Queues setup *
1330 \**************/
1331
1332 static struct ath5k_txq *
1333 ath5k_txq_setup(struct ath5k_softc *sc,
1334                 int qtype, int subtype)
1335 {
1336         struct ath5k_hw *ah = sc->ah;
1337         struct ath5k_txq *txq;
1338         struct ath5k_txq_info qi = {
1339                 .tqi_subtype = subtype,
1340                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1341                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1342                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1343         };
1344         int qnum;
1345
1346         /*
1347          * Enable interrupts only for EOL and DESC conditions.
1348          * We mark tx descriptors to receive a DESC interrupt
1349          * when a tx queue gets deep; otherwise waiting for the
1350          * EOL to reap descriptors.  Note that this is done to
1351          * reduce interrupt load and this only defers reaping
1352          * descriptors, never transmitting frames.  Aside from
1353          * reducing interrupts this also permits more concurrency.
1354          * The only potential downside is if the tx queue backs
1355          * up in which case the top half of the kernel may backup
1356          * due to a lack of tx descriptors.
1357          */
1358         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1359                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1360         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1361         if (qnum < 0) {
1362                 /*
1363                  * NB: don't print a message, this happens
1364                  * normally on parts with too few tx queues
1365                  */
1366                 return ERR_PTR(qnum);
1367         }
1368         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1369                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1370                         qnum, ARRAY_SIZE(sc->txqs));
1371                 ath5k_hw_release_tx_queue(ah, qnum);
1372                 return ERR_PTR(-EINVAL);
1373         }
1374         txq = &sc->txqs[qnum];
1375         if (!txq->setup) {
1376                 txq->qnum = qnum;
1377                 txq->link = NULL;
1378                 INIT_LIST_HEAD(&txq->q);
1379                 spin_lock_init(&txq->lock);
1380                 txq->setup = true;
1381         }
1382         return &sc->txqs[qnum];
1383 }
1384
1385 static int
1386 ath5k_beaconq_setup(struct ath5k_hw *ah)
1387 {
1388         struct ath5k_txq_info qi = {
1389                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1390                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1391                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1392                 /* NB: for dynamic turbo, don't enable any other interrupts */
1393                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1394         };
1395
1396         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1397 }
1398
1399 static int
1400 ath5k_beaconq_config(struct ath5k_softc *sc)
1401 {
1402         struct ath5k_hw *ah = sc->ah;
1403         struct ath5k_txq_info qi;
1404         int ret;
1405
1406         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1407         if (ret)
1408                 return ret;
1409         if (sc->opmode == NL80211_IFTYPE_AP ||
1410                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1411                 /*
1412                  * Always burst out beacon and CAB traffic
1413                  * (aifs = cwmin = cwmax = 0)
1414                  */
1415                 qi.tqi_aifs = 0;
1416                 qi.tqi_cw_min = 0;
1417                 qi.tqi_cw_max = 0;
1418         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1419                 /*
1420                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1421                  */
1422                 qi.tqi_aifs = 0;
1423                 qi.tqi_cw_min = 0;
1424                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1425         }
1426
1427         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1428                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1429                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1430
1431         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1432         if (ret) {
1433                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1434                         "hardware queue!\n", __func__);
1435                 return ret;
1436         }
1437
1438         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1439 }
1440
1441 static void
1442 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1443 {
1444         struct ath5k_buf *bf, *bf0;
1445
1446         /*
1447          * NB: this assumes output has been stopped and
1448          *     we do not need to block ath5k_tx_tasklet
1449          */
1450         spin_lock_bh(&txq->lock);
1451         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1452                 ath5k_debug_printtxbuf(sc, bf);
1453
1454                 ath5k_txbuf_free(sc, bf);
1455
1456                 spin_lock_bh(&sc->txbuflock);
1457                 sc->tx_stats[txq->qnum].len--;
1458                 list_move_tail(&bf->list, &sc->txbuf);
1459                 sc->txbuf_len++;
1460                 spin_unlock_bh(&sc->txbuflock);
1461         }
1462         txq->link = NULL;
1463         spin_unlock_bh(&txq->lock);
1464 }
1465
1466 /*
1467  * Drain the transmit queues and reclaim resources.
1468  */
1469 static void
1470 ath5k_txq_cleanup(struct ath5k_softc *sc)
1471 {
1472         struct ath5k_hw *ah = sc->ah;
1473         unsigned int i;
1474
1475         /* XXX return value */
1476         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1477                 /* don't touch the hardware if marked invalid */
1478                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1479                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1480                         ath5k_hw_get_txdp(ah, sc->bhalq));
1481                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1482                         if (sc->txqs[i].setup) {
1483                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1484                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1485                                         "link %p\n",
1486                                         sc->txqs[i].qnum,
1487                                         ath5k_hw_get_txdp(ah,
1488                                                         sc->txqs[i].qnum),
1489                                         sc->txqs[i].link);
1490                         }
1491         }
1492         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1493
1494         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1495                 if (sc->txqs[i].setup)
1496                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1497 }
1498
1499 static void
1500 ath5k_txq_release(struct ath5k_softc *sc)
1501 {
1502         struct ath5k_txq *txq = sc->txqs;
1503         unsigned int i;
1504
1505         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1506                 if (txq->setup) {
1507                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1508                         txq->setup = false;
1509                 }
1510 }
1511
1512
1513
1514
1515 /*************\
1516 * RX Handling *
1517 \*************/
1518
1519 /*
1520  * Enable the receive h/w following a reset.
1521  */
1522 static int
1523 ath5k_rx_start(struct ath5k_softc *sc)
1524 {
1525         struct ath5k_hw *ah = sc->ah;
1526         struct ath5k_buf *bf;
1527         int ret;
1528
1529         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1530
1531         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1532                 sc->cachelsz, sc->rxbufsize);
1533
1534         sc->rxlink = NULL;
1535
1536         spin_lock_bh(&sc->rxbuflock);
1537         list_for_each_entry(bf, &sc->rxbuf, list) {
1538                 ret = ath5k_rxbuf_setup(sc, bf);
1539                 if (ret != 0) {
1540                         spin_unlock_bh(&sc->rxbuflock);
1541                         goto err;
1542                 }
1543         }
1544         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1545         spin_unlock_bh(&sc->rxbuflock);
1546
1547         ath5k_hw_set_rxdp(ah, bf->daddr);
1548         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1549         ath5k_mode_setup(sc);           /* set filters, etc. */
1550         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1551
1552         return 0;
1553 err:
1554         return ret;
1555 }
1556
1557 /*
1558  * Disable the receive h/w in preparation for a reset.
1559  */
1560 static void
1561 ath5k_rx_stop(struct ath5k_softc *sc)
1562 {
1563         struct ath5k_hw *ah = sc->ah;
1564
1565         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1566         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1567         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1568
1569         ath5k_debug_printrxbuffs(sc, ah);
1570
1571         sc->rxlink = NULL;              /* just in case */
1572 }
1573
1574 static unsigned int
1575 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1576                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1577 {
1578         struct ieee80211_hdr *hdr = (void *)skb->data;
1579         unsigned int keyix, hlen;
1580
1581         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1582                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1583                 return RX_FLAG_DECRYPTED;
1584
1585         /* Apparently when a default key is used to decrypt the packet
1586            the hw does not set the index used to decrypt.  In such cases
1587            get the index from the packet. */
1588         hlen = ieee80211_hdrlen(hdr->frame_control);
1589         if (ieee80211_has_protected(hdr->frame_control) &&
1590             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1591             skb->len >= hlen + 4) {
1592                 keyix = skb->data[hlen + 3] >> 6;
1593
1594                 if (test_bit(keyix, sc->keymap))
1595                         return RX_FLAG_DECRYPTED;
1596         }
1597
1598         return 0;
1599 }
1600
1601
1602 static void
1603 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1604                      struct ieee80211_rx_status *rxs)
1605 {
1606         u64 tsf, bc_tstamp;
1607         u32 hw_tu;
1608         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1609
1610         if (ieee80211_is_beacon(mgmt->frame_control) &&
1611             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1612             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1613                 /*
1614                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1615                  * have updated the local TSF. We have to work around various
1616                  * hardware bugs, though...
1617                  */
1618                 tsf = ath5k_hw_get_tsf64(sc->ah);
1619                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1620                 hw_tu = TSF_TO_TU(tsf);
1621
1622                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1623                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1624                         (unsigned long long)bc_tstamp,
1625                         (unsigned long long)rxs->mactime,
1626                         (unsigned long long)(rxs->mactime - bc_tstamp),
1627                         (unsigned long long)tsf);
1628
1629                 /*
1630                  * Sometimes the HW will give us a wrong tstamp in the rx
1631                  * status, causing the timestamp extension to go wrong.
1632                  * (This seems to happen especially with beacon frames bigger
1633                  * than 78 byte (incl. FCS))
1634                  * But we know that the receive timestamp must be later than the
1635                  * timestamp of the beacon since HW must have synced to that.
1636                  *
1637                  * NOTE: here we assume mactime to be after the frame was
1638                  * received, not like mac80211 which defines it at the start.
1639                  */
1640                 if (bc_tstamp > rxs->mactime) {
1641                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1642                                 "fixing mactime from %llx to %llx\n",
1643                                 (unsigned long long)rxs->mactime,
1644                                 (unsigned long long)tsf);
1645                         rxs->mactime = tsf;
1646                 }
1647
1648                 /*
1649                  * Local TSF might have moved higher than our beacon timers,
1650                  * in that case we have to update them to continue sending
1651                  * beacons. This also takes care of synchronizing beacon sending
1652                  * times with other stations.
1653                  */
1654                 if (hw_tu >= sc->nexttbtt)
1655                         ath5k_beacon_update_timers(sc, bc_tstamp);
1656         }
1657 }
1658
1659
1660 static void
1661 ath5k_tasklet_rx(unsigned long data)
1662 {
1663         struct ieee80211_rx_status rxs = {};
1664         struct ath5k_rx_status rs = {};
1665         struct sk_buff *skb;
1666         struct ath5k_softc *sc = (void *)data;
1667         struct ath5k_buf *bf, *bf_last;
1668         struct ath5k_desc *ds;
1669         int ret;
1670         int hdrlen;
1671         int pad;
1672
1673         spin_lock(&sc->rxbuflock);
1674         if (list_empty(&sc->rxbuf)) {
1675                 ATH5K_WARN(sc, "empty rx buf pool\n");
1676                 goto unlock;
1677         }
1678         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1679         do {
1680                 rxs.flag = 0;
1681
1682                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1683                 BUG_ON(bf->skb == NULL);
1684                 skb = bf->skb;
1685                 ds = bf->desc;
1686
1687                 /*
1688                  * last buffer must not be freed to ensure proper hardware
1689                  * function. When the hardware finishes also a packet next to
1690                  * it, we are sure, it doesn't use it anymore and we can go on.
1691                  */
1692                 if (bf_last == bf)
1693                         bf->flags |= 1;
1694                 if (bf->flags) {
1695                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1696                                         struct ath5k_buf, list);
1697                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1698                                         &rs);
1699                         if (ret)
1700                                 break;
1701                         bf->flags &= ~1;
1702                         /* skip the overwritten one (even status is martian) */
1703                         goto next;
1704                 }
1705
1706                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1707                 if (unlikely(ret == -EINPROGRESS))
1708                         break;
1709                 else if (unlikely(ret)) {
1710                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1711                         spin_unlock(&sc->rxbuflock);
1712                         return;
1713                 }
1714
1715                 if (unlikely(rs.rs_more)) {
1716                         ATH5K_WARN(sc, "unsupported jumbo\n");
1717                         goto next;
1718                 }
1719
1720                 if (unlikely(rs.rs_status)) {
1721                         if (rs.rs_status & AR5K_RXERR_PHY)
1722                                 goto next;
1723                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1724                                 /*
1725                                  * Decrypt error.  If the error occurred
1726                                  * because there was no hardware key, then
1727                                  * let the frame through so the upper layers
1728                                  * can process it.  This is necessary for 5210
1729                                  * parts which have no way to setup a ``clear''
1730                                  * key cache entry.
1731                                  *
1732                                  * XXX do key cache faulting
1733                                  */
1734                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1735                                     !(rs.rs_status & AR5K_RXERR_CRC))
1736                                         goto accept;
1737                         }
1738                         if (rs.rs_status & AR5K_RXERR_MIC) {
1739                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1740                                 goto accept;
1741                         }
1742
1743                         /* let crypto-error packets fall through in MNTR */
1744                         if ((rs.rs_status &
1745                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1746                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1747                                 goto next;
1748                 }
1749 accept:
1750                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1751                                 PCI_DMA_FROMDEVICE);
1752                 bf->skb = NULL;
1753
1754                 skb_put(skb, rs.rs_datalen);
1755
1756                 /*
1757                  * the hardware adds a padding to 4 byte boundaries between
1758                  * the header and the payload data if the header length is
1759                  * not multiples of 4 - remove it
1760                  */
1761                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1762                 if (hdrlen & 3) {
1763                         pad = hdrlen % 4;
1764                         memmove(skb->data + pad, skb->data, hdrlen);
1765                         skb_pull(skb, pad);
1766                 }
1767
1768                 /*
1769                  * always extend the mac timestamp, since this information is
1770                  * also needed for proper IBSS merging.
1771                  *
1772                  * XXX: it might be too late to do it here, since rs_tstamp is
1773                  * 15bit only. that means TSF extension has to be done within
1774                  * 32768usec (about 32ms). it might be necessary to move this to
1775                  * the interrupt handler, like it is done in madwifi.
1776                  *
1777                  * Unfortunately we don't know when the hardware takes the rx
1778                  * timestamp (beginning of phy frame, data frame, end of rx?).
1779                  * The only thing we know is that it is hardware specific...
1780                  * On AR5213 it seems the rx timestamp is at the end of the
1781                  * frame, but i'm not sure.
1782                  *
1783                  * NOTE: mac80211 defines mactime at the beginning of the first
1784                  * data symbol. Since we don't have any time references it's
1785                  * impossible to comply to that. This affects IBSS merge only
1786                  * right now, so it's not too bad...
1787                  */
1788                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1789                 rxs.flag |= RX_FLAG_TSFT;
1790
1791                 rxs.freq = sc->curchan->center_freq;
1792                 rxs.band = sc->curband->band;
1793
1794                 rxs.noise = sc->ah->ah_noise_floor;
1795                 rxs.signal = rxs.noise + rs.rs_rssi;
1796
1797                 /* An rssi of 35 indicates you should be able use
1798                  * 54 Mbps reliably. A more elaborate scheme can be used
1799                  * here but it requires a map of SNR/throughput for each
1800                  * possible mode used */
1801                 rxs.qual = rs.rs_rssi * 100 / 35;
1802
1803                 /* rssi can be more than 35 though, anything above that
1804                  * should be considered at 100% */
1805                 if (rxs.qual > 100)
1806                         rxs.qual = 100;
1807
1808                 rxs.antenna = rs.rs_antenna;
1809                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1810                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1811
1812                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1813                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1814                         rxs.flag |= RX_FLAG_SHORTPRE;
1815
1816                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1817
1818                 /* check beacons in IBSS mode */
1819                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1820                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1821
1822                 __ieee80211_rx(sc->hw, skb, &rxs);
1823 next:
1824                 list_move_tail(&bf->list, &sc->rxbuf);
1825         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1826 unlock:
1827         spin_unlock(&sc->rxbuflock);
1828 }
1829
1830
1831
1832
1833 /*************\
1834 * TX Handling *
1835 \*************/
1836
1837 static void
1838 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1839 {
1840         struct ath5k_tx_status ts = {};
1841         struct ath5k_buf *bf, *bf0;
1842         struct ath5k_desc *ds;
1843         struct sk_buff *skb;
1844         struct ieee80211_tx_info *info;
1845         int i, ret;
1846
1847         spin_lock(&txq->lock);
1848         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1849                 ds = bf->desc;
1850
1851                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1852                 if (unlikely(ret == -EINPROGRESS))
1853                         break;
1854                 else if (unlikely(ret)) {
1855                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1856                                 ret, txq->qnum);
1857                         break;
1858                 }
1859
1860                 skb = bf->skb;
1861                 info = IEEE80211_SKB_CB(skb);
1862                 bf->skb = NULL;
1863
1864                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1865                                 PCI_DMA_TODEVICE);
1866
1867                 ieee80211_tx_info_clear_status(info);
1868                 for (i = 0; i < 4; i++) {
1869                         struct ieee80211_tx_rate *r =
1870                                 &info->status.rates[i];
1871
1872                         if (ts.ts_rate[i]) {
1873                                 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1874                                 r->count = ts.ts_retry[i];
1875                         } else {
1876                                 r->idx = -1;
1877                                 r->count = 0;
1878                         }
1879                 }
1880
1881                 /* count the successful attempt as well */
1882                 info->status.rates[ts.ts_final_idx].count++;
1883
1884                 if (unlikely(ts.ts_status)) {
1885                         sc->ll_stats.dot11ACKFailureCount++;
1886                         if (ts.ts_status & AR5K_TXERR_FILT)
1887                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1888                 } else {
1889                         info->flags |= IEEE80211_TX_STAT_ACK;
1890                         info->status.ack_signal = ts.ts_rssi;
1891                 }
1892
1893                 ieee80211_tx_status(sc->hw, skb);
1894                 sc->tx_stats[txq->qnum].count++;
1895
1896                 spin_lock(&sc->txbuflock);
1897                 sc->tx_stats[txq->qnum].len--;
1898                 list_move_tail(&bf->list, &sc->txbuf);
1899                 sc->txbuf_len++;
1900                 spin_unlock(&sc->txbuflock);
1901         }
1902         if (likely(list_empty(&txq->q)))
1903                 txq->link = NULL;
1904         spin_unlock(&txq->lock);
1905         if (sc->txbuf_len > ATH_TXBUF / 5)
1906                 ieee80211_wake_queues(sc->hw);
1907 }
1908
1909 static void
1910 ath5k_tasklet_tx(unsigned long data)
1911 {
1912         struct ath5k_softc *sc = (void *)data;
1913
1914         ath5k_tx_processq(sc, sc->txq);
1915 }
1916
1917
1918 /*****************\
1919 * Beacon handling *
1920 \*****************/
1921
1922 /*
1923  * Setup the beacon frame for transmit.
1924  */
1925 static int
1926 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1927 {
1928         struct sk_buff *skb = bf->skb;
1929         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1930         struct ath5k_hw *ah = sc->ah;
1931         struct ath5k_desc *ds;
1932         int ret, antenna = 0;
1933         u32 flags;
1934
1935         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1936                         PCI_DMA_TODEVICE);
1937         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1938                         "skbaddr %llx\n", skb, skb->data, skb->len,
1939                         (unsigned long long)bf->skbaddr);
1940         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1941                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1942                 return -EIO;
1943         }
1944
1945         ds = bf->desc;
1946
1947         flags = AR5K_TXDESC_NOACK;
1948         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1949                 ds->ds_link = bf->daddr;        /* self-linked */
1950                 flags |= AR5K_TXDESC_VEOL;
1951                 /*
1952                  * Let hardware handle antenna switching if txantenna is not set
1953                  */
1954         } else {
1955                 ds->ds_link = 0;
1956                 /*
1957                  * Switch antenna every 4 beacons if txantenna is not set
1958                  * XXX assumes two antennas
1959                  */
1960                 if (antenna == 0)
1961                         antenna = sc->bsent & 4 ? 2 : 1;
1962         }
1963
1964         ds->ds_data = bf->skbaddr;
1965         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1966                         ieee80211_get_hdrlen_from_skb(skb),
1967                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1968                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1969                         1, AR5K_TXKEYIX_INVALID,
1970                         antenna, flags, 0, 0);
1971         if (ret)
1972                 goto err_unmap;
1973
1974         return 0;
1975 err_unmap:
1976         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1977         return ret;
1978 }
1979
1980 /*
1981  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1982  * frame contents are done as needed and the slot time is
1983  * also adjusted based on current state.
1984  *
1985  * this is usually called from interrupt context (ath5k_intr())
1986  * but also from ath5k_beacon_config() in IBSS mode which in turn
1987  * can be called from a tasklet and user context
1988  */
1989 static void
1990 ath5k_beacon_send(struct ath5k_softc *sc)
1991 {
1992         struct ath5k_buf *bf = sc->bbuf;
1993         struct ath5k_hw *ah = sc->ah;
1994
1995         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1996
1997         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1998                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1999                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2000                 return;
2001         }
2002         /*
2003          * Check if the previous beacon has gone out.  If
2004          * not don't don't try to post another, skip this
2005          * period and wait for the next.  Missed beacons
2006          * indicate a problem and should not occur.  If we
2007          * miss too many consecutive beacons reset the device.
2008          */
2009         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2010                 sc->bmisscount++;
2011                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2012                         "missed %u consecutive beacons\n", sc->bmisscount);
2013                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2014                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2015                                 "stuck beacon time (%u missed)\n",
2016                                 sc->bmisscount);
2017                         tasklet_schedule(&sc->restq);
2018                 }
2019                 return;
2020         }
2021         if (unlikely(sc->bmisscount != 0)) {
2022                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2023                         "resume beacon xmit after %u misses\n",
2024                         sc->bmisscount);
2025                 sc->bmisscount = 0;
2026         }
2027
2028         /*
2029          * Stop any current dma and put the new frame on the queue.
2030          * This should never fail since we check above that no frames
2031          * are still pending on the queue.
2032          */
2033         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2034                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2035                 /* NB: hw still stops DMA, so proceed */
2036         }
2037
2038         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2039         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2040         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2041                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2042
2043         sc->bsent++;
2044 }
2045
2046
2047 /**
2048  * ath5k_beacon_update_timers - update beacon timers
2049  *
2050  * @sc: struct ath5k_softc pointer we are operating on
2051  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2052  *          beacon timer update based on the current HW TSF.
2053  *
2054  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2055  * of a received beacon or the current local hardware TSF and write it to the
2056  * beacon timer registers.
2057  *
2058  * This is called in a variety of situations, e.g. when a beacon is received,
2059  * when a TSF update has been detected, but also when an new IBSS is created or
2060  * when we otherwise know we have to update the timers, but we keep it in this
2061  * function to have it all together in one place.
2062  */
2063 static void
2064 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2065 {
2066         struct ath5k_hw *ah = sc->ah;
2067         u32 nexttbtt, intval, hw_tu, bc_tu;
2068         u64 hw_tsf;
2069
2070         intval = sc->bintval & AR5K_BEACON_PERIOD;
2071         if (WARN_ON(!intval))
2072                 return;
2073
2074         /* beacon TSF converted to TU */
2075         bc_tu = TSF_TO_TU(bc_tsf);
2076
2077         /* current TSF converted to TU */
2078         hw_tsf = ath5k_hw_get_tsf64(ah);
2079         hw_tu = TSF_TO_TU(hw_tsf);
2080
2081 #define FUDGE 3
2082         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2083         if (bc_tsf == -1) {
2084                 /*
2085                  * no beacons received, called internally.
2086                  * just need to refresh timers based on HW TSF.
2087                  */
2088                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2089         } else if (bc_tsf == 0) {
2090                 /*
2091                  * no beacon received, probably called by ath5k_reset_tsf().
2092                  * reset TSF to start with 0.
2093                  */
2094                 nexttbtt = intval;
2095                 intval |= AR5K_BEACON_RESET_TSF;
2096         } else if (bc_tsf > hw_tsf) {
2097                 /*
2098                  * beacon received, SW merge happend but HW TSF not yet updated.
2099                  * not possible to reconfigure timers yet, but next time we
2100                  * receive a beacon with the same BSSID, the hardware will
2101                  * automatically update the TSF and then we need to reconfigure
2102                  * the timers.
2103                  */
2104                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2105                         "need to wait for HW TSF sync\n");
2106                 return;
2107         } else {
2108                 /*
2109                  * most important case for beacon synchronization between STA.
2110                  *
2111                  * beacon received and HW TSF has been already updated by HW.
2112                  * update next TBTT based on the TSF of the beacon, but make
2113                  * sure it is ahead of our local TSF timer.
2114                  */
2115                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2116         }
2117 #undef FUDGE
2118
2119         sc->nexttbtt = nexttbtt;
2120
2121         intval |= AR5K_BEACON_ENA;
2122         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2123
2124         /*
2125          * debugging output last in order to preserve the time critical aspect
2126          * of this function
2127          */
2128         if (bc_tsf == -1)
2129                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2130                         "reconfigured timers based on HW TSF\n");
2131         else if (bc_tsf == 0)
2132                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133                         "reset HW TSF and timers\n");
2134         else
2135                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2136                         "updated timers based on beacon TSF\n");
2137
2138         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2139                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2140                           (unsigned long long) bc_tsf,
2141                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2142         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2143                 intval & AR5K_BEACON_PERIOD,
2144                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2145                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2146 }
2147
2148
2149 /**
2150  * ath5k_beacon_config - Configure the beacon queues and interrupts
2151  *
2152  * @sc: struct ath5k_softc pointer we are operating on
2153  *
2154  * When operating in station mode we want to receive a BMISS interrupt when we
2155  * stop seeing beacons from the AP we've associated with so we can look for
2156  * another AP to associate with.
2157  *
2158  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2159  * interrupts to detect TSF updates only.
2160  */
2161 static void
2162 ath5k_beacon_config(struct ath5k_softc *sc)
2163 {
2164         struct ath5k_hw *ah = sc->ah;
2165
2166         ath5k_hw_set_imr(ah, 0);
2167         sc->bmisscount = 0;
2168         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2169
2170         if (sc->opmode == NL80211_IFTYPE_STATION) {
2171                 sc->imask |= AR5K_INT_BMISS;
2172         } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2173                         sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2174                         sc->opmode == NL80211_IFTYPE_AP) {
2175                 /*
2176                  * In IBSS mode we use a self-linked tx descriptor and let the
2177                  * hardware send the beacons automatically. We have to load it
2178                  * only once here.
2179                  * We use the SWBA interrupt only to keep track of the beacon
2180                  * timers in order to detect automatic TSF updates.
2181                  */
2182                 ath5k_beaconq_config(sc);
2183
2184                 sc->imask |= AR5K_INT_SWBA;
2185
2186                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2187                         if (ath5k_hw_hasveol(ah)) {
2188                                 spin_lock(&sc->block);
2189                                 ath5k_beacon_send(sc);
2190                                 spin_unlock(&sc->block);
2191                         }
2192                 } else
2193                         ath5k_beacon_update_timers(sc, -1);
2194         }
2195
2196         ath5k_hw_set_imr(ah, sc->imask);
2197 }
2198
2199
2200 /********************\
2201 * Interrupt handling *
2202 \********************/
2203
2204 static int
2205 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2206 {
2207         struct ath5k_hw *ah = sc->ah;
2208         int ret, i;
2209
2210         mutex_lock(&sc->lock);
2211
2212         if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2213                 goto out_ok;
2214
2215         __clear_bit(ATH_STAT_STARTED, sc->status);
2216
2217         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2218
2219         /*
2220          * Stop anything previously setup.  This is safe
2221          * no matter this is the first time through or not.
2222          */
2223         ath5k_stop_locked(sc);
2224
2225         /*
2226          * The basic interface to setting the hardware in a good
2227          * state is ``reset''.  On return the hardware is known to
2228          * be powered up and with interrupts disabled.  This must
2229          * be followed by initialization of the appropriate bits
2230          * and then setup of the interrupt mask.
2231          */
2232         sc->curchan = sc->hw->conf.channel;
2233         sc->curband = &sc->sbands[sc->curchan->band];
2234         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2235                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2236                 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2237         ret = ath5k_reset(sc, false, false);
2238         if (ret)
2239                 goto done;
2240
2241         /*
2242          * Reset the key cache since some parts do not reset the
2243          * contents on initial power up or resume from suspend.
2244          */
2245         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2246                 ath5k_hw_reset_key(ah, i);
2247
2248         __set_bit(ATH_STAT_STARTED, sc->status);
2249
2250         /* Set ack to be sent at low bit-rates */
2251         ath5k_hw_set_ack_bitrate_high(ah, false);
2252
2253         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2254                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2255
2256 out_ok:
2257         ret = 0;
2258 done:
2259         mmiowb();
2260         mutex_unlock(&sc->lock);
2261         return ret;
2262 }
2263
2264 static int
2265 ath5k_stop_locked(struct ath5k_softc *sc)
2266 {
2267         struct ath5k_hw *ah = sc->ah;
2268
2269         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2270                         test_bit(ATH_STAT_INVALID, sc->status));
2271
2272         /*
2273          * Shutdown the hardware and driver:
2274          *    stop output from above
2275          *    disable interrupts
2276          *    turn off timers
2277          *    turn off the radio
2278          *    clear transmit machinery
2279          *    clear receive machinery
2280          *    drain and release tx queues
2281          *    reclaim beacon resources
2282          *    power down hardware
2283          *
2284          * Note that some of this work is not possible if the
2285          * hardware is gone (invalid).
2286          */
2287         ieee80211_stop_queues(sc->hw);
2288
2289         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2290                 ath5k_led_off(sc);
2291                 ath5k_hw_set_imr(ah, 0);
2292                 synchronize_irq(sc->pdev->irq);
2293         }
2294         ath5k_txq_cleanup(sc);
2295         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2296                 ath5k_rx_stop(sc);
2297                 ath5k_hw_phy_disable(ah);
2298         } else
2299                 sc->rxlink = NULL;
2300
2301         return 0;
2302 }
2303
2304 /*
2305  * Stop the device, grabbing the top-level lock to protect
2306  * against concurrent entry through ath5k_init (which can happen
2307  * if another thread does a system call and the thread doing the
2308  * stop is preempted).
2309  */
2310 static int
2311 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2312 {
2313         int ret;
2314
2315         mutex_lock(&sc->lock);
2316         ret = ath5k_stop_locked(sc);
2317         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2318                 /*
2319                  * Set the chip in full sleep mode.  Note that we are
2320                  * careful to do this only when bringing the interface
2321                  * completely to a stop.  When the chip is in this state
2322                  * it must be carefully woken up or references to
2323                  * registers in the PCI clock domain may freeze the bus
2324                  * (and system).  This varies by chip and is mostly an
2325                  * issue with newer parts that go to sleep more quickly.
2326                  */
2327                 if (sc->ah->ah_mac_srev >= 0x78) {
2328                         /*
2329                          * XXX
2330                          * don't put newer MAC revisions > 7.8 to sleep because
2331                          * of the above mentioned problems
2332                          */
2333                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2334                                 "not putting device to sleep\n");
2335                 } else {
2336                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2337                                 "putting device to full sleep\n");
2338                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2339                 }
2340         }
2341         ath5k_txbuf_free(sc, sc->bbuf);
2342         if (!is_suspend)
2343                 __clear_bit(ATH_STAT_STARTED, sc->status);
2344
2345         mmiowb();
2346         mutex_unlock(&sc->lock);
2347
2348         del_timer_sync(&sc->calib_tim);
2349         tasklet_kill(&sc->rxtq);
2350         tasklet_kill(&sc->txtq);
2351         tasklet_kill(&sc->restq);
2352
2353         return ret;
2354 }
2355
2356 static irqreturn_t
2357 ath5k_intr(int irq, void *dev_id)
2358 {
2359         struct ath5k_softc *sc = dev_id;
2360         struct ath5k_hw *ah = sc->ah;
2361         enum ath5k_int status;
2362         unsigned int counter = 1000;
2363
2364         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2365                                 !ath5k_hw_is_intr_pending(ah)))
2366                 return IRQ_NONE;
2367
2368         do {
2369                 /*
2370                  * Figure out the reason(s) for the interrupt.  Note
2371                  * that get_isr returns a pseudo-ISR that may include
2372                  * bits we haven't explicitly enabled so we mask the
2373                  * value to insure we only process bits we requested.
2374                  */
2375                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2376                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2377                                 status, sc->imask);
2378                 status &= sc->imask; /* discard unasked for bits */
2379                 if (unlikely(status & AR5K_INT_FATAL)) {
2380                         /*
2381                          * Fatal errors are unrecoverable.
2382                          * Typically these are caused by DMA errors.
2383                          */
2384                         tasklet_schedule(&sc->restq);
2385                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2386                         tasklet_schedule(&sc->restq);
2387                 } else {
2388                         if (status & AR5K_INT_SWBA) {
2389                                 /*
2390                                 * Software beacon alert--time to send a beacon.
2391                                 * Handle beacon transmission directly; deferring
2392                                 * this is too slow to meet timing constraints
2393                                 * under load.
2394                                 *
2395                                 * In IBSS mode we use this interrupt just to
2396                                 * keep track of the next TBTT (target beacon
2397                                 * transmission time) in order to detect wether
2398                                 * automatic TSF updates happened.
2399                                 */
2400                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2401                                          /* XXX: only if VEOL suppported */
2402                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2403                                         sc->nexttbtt += sc->bintval;
2404                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2405                                                   "SWBA nexttbtt: %x hw_tu: %x "
2406                                                   "TSF: %llx\n",
2407                                                   sc->nexttbtt,
2408                                                   TSF_TO_TU(tsf),
2409                                                   (unsigned long long) tsf);
2410                                 } else {
2411                                         spin_lock(&sc->block);
2412                                         ath5k_beacon_send(sc);
2413                                         spin_unlock(&sc->block);
2414                                 }
2415                         }
2416                         if (status & AR5K_INT_RXEOL) {
2417                                 /*
2418                                 * NB: the hardware should re-read the link when
2419                                 *     RXE bit is written, but it doesn't work at
2420                                 *     least on older hardware revs.
2421                                 */
2422                                 sc->rxlink = NULL;
2423                         }
2424                         if (status & AR5K_INT_TXURN) {
2425                                 /* bump tx trigger level */
2426                                 ath5k_hw_update_tx_triglevel(ah, true);
2427                         }
2428                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2429                                 tasklet_schedule(&sc->rxtq);
2430                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2431                                         | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2432                                 tasklet_schedule(&sc->txtq);
2433                         if (status & AR5K_INT_BMISS) {
2434                         }
2435                         if (status & AR5K_INT_MIB) {
2436                                 /*
2437                                  * These stats are also used for ANI i think
2438                                  * so how about updating them more often ?
2439                                  */
2440                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2441                         }
2442                 }
2443         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2444
2445         if (unlikely(!counter))
2446                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2447
2448         return IRQ_HANDLED;
2449 }
2450
2451 static void
2452 ath5k_tasklet_reset(unsigned long data)
2453 {
2454         struct ath5k_softc *sc = (void *)data;
2455
2456         ath5k_reset_wake(sc);
2457 }
2458
2459 /*
2460  * Periodically recalibrate the PHY to account
2461  * for temperature/environment changes.
2462  */
2463 static void
2464 ath5k_calibrate(unsigned long data)
2465 {
2466         struct ath5k_softc *sc = (void *)data;
2467         struct ath5k_hw *ah = sc->ah;
2468
2469         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2470                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2471                 sc->curchan->hw_value);
2472
2473         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2474                 /*
2475                  * Rfgain is out of bounds, reset the chip
2476                  * to load new gain values.
2477                  */
2478                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2479                 ath5k_reset_wake(sc);
2480         }
2481         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2482                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2483                         ieee80211_frequency_to_channel(
2484                                 sc->curchan->center_freq));
2485
2486         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2487                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2488 }
2489
2490
2491
2492 /***************\
2493 * LED functions *
2494 \***************/
2495
2496 static void
2497 ath5k_led_enable(struct ath5k_softc *sc)
2498 {
2499         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2500                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2501                 ath5k_led_off(sc);
2502         }
2503 }
2504
2505 static void
2506 ath5k_led_on(struct ath5k_softc *sc)
2507 {
2508         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2509                 return;
2510         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2511 }
2512
2513 static void
2514 ath5k_led_off(struct ath5k_softc *sc)
2515 {
2516         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2517                 return;
2518         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2519 }
2520
2521 static void
2522 ath5k_led_brightness_set(struct led_classdev *led_dev,
2523         enum led_brightness brightness)
2524 {
2525         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2526                 led_dev);
2527
2528         if (brightness == LED_OFF)
2529                 ath5k_led_off(led->sc);
2530         else
2531                 ath5k_led_on(led->sc);
2532 }
2533
2534 static int
2535 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2536                    const char *name, char *trigger)
2537 {
2538         int err;
2539
2540         led->sc = sc;
2541         strncpy(led->name, name, sizeof(led->name));
2542         led->led_dev.name = led->name;
2543         led->led_dev.default_trigger = trigger;
2544         led->led_dev.brightness_set = ath5k_led_brightness_set;
2545
2546         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2547         if (err) {
2548                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2549                 led->sc = NULL;
2550         }
2551         return err;
2552 }
2553
2554 static void
2555 ath5k_unregister_led(struct ath5k_led *led)
2556 {
2557         if (!led->sc)
2558                 return;
2559         led_classdev_unregister(&led->led_dev);
2560         ath5k_led_off(led->sc);
2561         led->sc = NULL;
2562 }
2563
2564 static void
2565 ath5k_unregister_leds(struct ath5k_softc *sc)
2566 {
2567         ath5k_unregister_led(&sc->rx_led);
2568         ath5k_unregister_led(&sc->tx_led);
2569 }
2570
2571
2572 static int
2573 ath5k_init_leds(struct ath5k_softc *sc)
2574 {
2575         int ret = 0;
2576         struct ieee80211_hw *hw = sc->hw;
2577         struct pci_dev *pdev = sc->pdev;
2578         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2579
2580         /*
2581          * Auto-enable soft led processing for IBM cards and for
2582          * 5211 minipci cards.
2583          */
2584         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2585             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2586                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2587                 sc->led_pin = 0;
2588                 sc->led_on = 0;  /* active low */
2589         }
2590         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2591         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2592                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2593                 sc->led_pin = 1;
2594                 sc->led_on = 1;  /* active high */
2595         }
2596         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2597                 goto out;
2598
2599         ath5k_led_enable(sc);
2600
2601         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2602         ret = ath5k_register_led(sc, &sc->rx_led, name,
2603                 ieee80211_get_rx_led_name(hw));
2604         if (ret)
2605                 goto out;
2606
2607         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2608         ret = ath5k_register_led(sc, &sc->tx_led, name,
2609                 ieee80211_get_tx_led_name(hw));
2610 out:
2611         return ret;
2612 }
2613
2614
2615 /********************\
2616 * Mac80211 functions *
2617 \********************/
2618
2619 static int
2620 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2621 {
2622         struct ath5k_softc *sc = hw->priv;
2623         struct ath5k_buf *bf;
2624         unsigned long flags;
2625         int hdrlen;
2626         int pad;
2627
2628         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2629
2630         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2631                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2632
2633         /*
2634          * the hardware expects the header padded to 4 byte boundaries
2635          * if this is not the case we add the padding after the header
2636          */
2637         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2638         if (hdrlen & 3) {
2639                 pad = hdrlen % 4;
2640                 if (skb_headroom(skb) < pad) {
2641                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2642                                 " headroom to pad %d\n", hdrlen, pad);
2643                         return -1;
2644                 }
2645                 skb_push(skb, pad);
2646                 memmove(skb->data, skb->data+pad, hdrlen);
2647         }
2648
2649         spin_lock_irqsave(&sc->txbuflock, flags);
2650         if (list_empty(&sc->txbuf)) {
2651                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2652                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2653                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2654                 return -1;
2655         }
2656         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2657         list_del(&bf->list);
2658         sc->txbuf_len--;
2659         if (list_empty(&sc->txbuf))
2660                 ieee80211_stop_queues(hw);
2661         spin_unlock_irqrestore(&sc->txbuflock, flags);
2662
2663         bf->skb = skb;
2664
2665         if (ath5k_txbuf_setup(sc, bf)) {
2666                 bf->skb = NULL;
2667                 spin_lock_irqsave(&sc->txbuflock, flags);
2668                 list_add_tail(&bf->list, &sc->txbuf);
2669                 sc->txbuf_len++;
2670                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2671                 dev_kfree_skb_any(skb);
2672                 return 0;
2673         }
2674
2675         return 0;
2676 }
2677
2678 static int
2679 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2680 {
2681         struct ath5k_hw *ah = sc->ah;
2682         int ret;
2683
2684         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2685
2686         if (stop) {
2687                 ath5k_hw_set_imr(ah, 0);
2688                 ath5k_txq_cleanup(sc);
2689                 ath5k_rx_stop(sc);
2690         }
2691         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2692         if (ret) {
2693                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2694                 goto err;
2695         }
2696
2697         /*
2698          * This is needed only to setup initial state
2699          * but it's best done after a reset.
2700          */
2701         ath5k_hw_set_txpower_limit(sc->ah, 0);
2702
2703         ret = ath5k_rx_start(sc);
2704         if (ret) {
2705                 ATH5K_ERR(sc, "can't start recv logic\n");
2706                 goto err;
2707         }
2708
2709         /*
2710          * Change channels and update the h/w rate map if we're switching;
2711          * e.g. 11a to 11b/g.
2712          *
2713          * We may be doing a reset in response to an ioctl that changes the
2714          * channel so update any state that might change as a result.
2715          *
2716          * XXX needed?
2717          */
2718 /*      ath5k_chan_change(sc, c); */
2719
2720         ath5k_beacon_config(sc);
2721         /* intrs are enabled by ath5k_beacon_config */
2722
2723         return 0;
2724 err:
2725         return ret;
2726 }
2727
2728 static int
2729 ath5k_reset_wake(struct ath5k_softc *sc)
2730 {
2731         int ret;
2732
2733         ret = ath5k_reset(sc, true, true);
2734         if (!ret)
2735                 ieee80211_wake_queues(sc->hw);
2736
2737         return ret;
2738 }
2739
2740 static int ath5k_start(struct ieee80211_hw *hw)
2741 {
2742         return ath5k_init(hw->priv, false);
2743 }
2744
2745 static void ath5k_stop(struct ieee80211_hw *hw)
2746 {
2747         ath5k_stop_hw(hw->priv, false);
2748 }
2749
2750 static int ath5k_add_interface(struct ieee80211_hw *hw,
2751                 struct ieee80211_if_init_conf *conf)
2752 {
2753         struct ath5k_softc *sc = hw->priv;
2754         int ret;
2755
2756         mutex_lock(&sc->lock);
2757         if (sc->vif) {
2758                 ret = 0;
2759                 goto end;
2760         }
2761
2762         sc->vif = conf->vif;
2763
2764         switch (conf->type) {
2765         case NL80211_IFTYPE_AP:
2766         case NL80211_IFTYPE_STATION:
2767         case NL80211_IFTYPE_ADHOC:
2768         case NL80211_IFTYPE_MESH_POINT:
2769         case NL80211_IFTYPE_MONITOR:
2770                 sc->opmode = conf->type;
2771                 break;
2772         default:
2773                 ret = -EOPNOTSUPP;
2774                 goto end;
2775         }
2776
2777         /* Set to a reasonable value. Note that this will
2778          * be set to mac80211's value at ath5k_config(). */
2779         sc->bintval = 1000;
2780         ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2781
2782         ret = 0;
2783 end:
2784         mutex_unlock(&sc->lock);
2785         return ret;
2786 }
2787
2788 static void
2789 ath5k_remove_interface(struct ieee80211_hw *hw,
2790                         struct ieee80211_if_init_conf *conf)
2791 {
2792         struct ath5k_softc *sc = hw->priv;
2793         u8 mac[ETH_ALEN] = {};
2794
2795         mutex_lock(&sc->lock);
2796         if (sc->vif != conf->vif)
2797                 goto end;
2798
2799         ath5k_hw_set_lladdr(sc->ah, mac);
2800         sc->vif = NULL;
2801 end:
2802         mutex_unlock(&sc->lock);
2803 }
2804
2805 /*
2806  * TODO: Phy disable/diversity etc
2807  */
2808 static int
2809 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2810 {
2811         struct ath5k_softc *sc = hw->priv;
2812         struct ieee80211_conf *conf = &hw->conf;
2813
2814         sc->bintval = conf->beacon_int;
2815         sc->power_level = conf->power_level;
2816
2817         return ath5k_chan_set(sc, conf->channel);
2818 }
2819
2820 static int
2821 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2822                         struct ieee80211_if_conf *conf)
2823 {
2824         struct ath5k_softc *sc = hw->priv;
2825         struct ath5k_hw *ah = sc->ah;
2826         int ret;
2827
2828         mutex_lock(&sc->lock);
2829         if (sc->vif != vif) {
2830                 ret = -EIO;
2831                 goto unlock;
2832         }
2833         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2834                 /* Cache for later use during resets */
2835                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2836                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2837                  * a clean way of letting us retrieve this yet. */
2838                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2839                 mmiowb();
2840         }
2841         if (conf->changed & IEEE80211_IFCC_BEACON &&
2842                         (vif->type == NL80211_IFTYPE_ADHOC ||
2843                          vif->type == NL80211_IFTYPE_MESH_POINT ||
2844                          vif->type == NL80211_IFTYPE_AP)) {
2845                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2846                 if (!beacon) {
2847                         ret = -ENOMEM;
2848                         goto unlock;
2849                 }
2850                 ath5k_beacon_update(sc, beacon);
2851         }
2852         mutex_unlock(&sc->lock);
2853
2854         return ath5k_reset_wake(sc);
2855 unlock:
2856         mutex_unlock(&sc->lock);
2857         return ret;
2858 }
2859
2860 #define SUPPORTED_FIF_FLAGS \
2861         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2862         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2863         FIF_BCN_PRBRESP_PROMISC
2864 /*
2865  * o always accept unicast, broadcast, and multicast traffic
2866  * o multicast traffic for all BSSIDs will be enabled if mac80211
2867  *   says it should be
2868  * o maintain current state of phy ofdm or phy cck error reception.
2869  *   If the hardware detects any of these type of errors then
2870  *   ath5k_hw_get_rx_filter() will pass to us the respective
2871  *   hardware filters to be able to receive these type of frames.
2872  * o probe request frames are accepted only when operating in
2873  *   hostap, adhoc, or monitor modes
2874  * o enable promiscuous mode according to the interface state
2875  * o accept beacons:
2876  *   - when operating in adhoc mode so the 802.11 layer creates
2877  *     node table entries for peers,
2878  *   - when operating in station mode for collecting rssi data when
2879  *     the station is otherwise quiet, or
2880  *   - when scanning
2881  */
2882 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2883                 unsigned int changed_flags,
2884                 unsigned int *new_flags,
2885                 int mc_count, struct dev_mc_list *mclist)
2886 {
2887         struct ath5k_softc *sc = hw->priv;
2888         struct ath5k_hw *ah = sc->ah;
2889         u32 mfilt[2], val, rfilt;
2890         u8 pos;
2891         int i;
2892
2893         mfilt[0] = 0;
2894         mfilt[1] = 0;
2895
2896         /* Only deal with supported flags */
2897         changed_flags &= SUPPORTED_FIF_FLAGS;
2898         *new_flags &= SUPPORTED_FIF_FLAGS;
2899
2900         /* If HW detects any phy or radar errors, leave those filters on.
2901          * Also, always enable Unicast, Broadcasts and Multicast
2902          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2903         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2904                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2905                 AR5K_RX_FILTER_MCAST);
2906
2907         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2908                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2909                         rfilt |= AR5K_RX_FILTER_PROM;
2910                         __set_bit(ATH_STAT_PROMISC, sc->status);
2911                 } else {
2912                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2913                 }
2914         }
2915
2916         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2917         if (*new_flags & FIF_ALLMULTI) {
2918                 mfilt[0] =  ~0;
2919                 mfilt[1] =  ~0;
2920         } else {
2921                 for (i = 0; i < mc_count; i++) {
2922                         if (!mclist)
2923                                 break;
2924                         /* calculate XOR of eight 6-bit values */
2925                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2926                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2927                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2928                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2929                         pos &= 0x3f;
2930                         mfilt[pos / 32] |= (1 << (pos % 32));
2931                         /* XXX: we might be able to just do this instead,
2932                         * but not sure, needs testing, if we do use this we'd
2933                         * neet to inform below to not reset the mcast */
2934                         /* ath5k_hw_set_mcast_filterindex(ah,
2935                          *      mclist->dmi_addr[5]); */
2936                         mclist = mclist->next;
2937                 }
2938         }
2939
2940         /* This is the best we can do */
2941         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2942                 rfilt |= AR5K_RX_FILTER_PHYERR;
2943
2944         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2945         * and probes for any BSSID, this needs testing */
2946         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2947                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2948
2949         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2950          * set we should only pass on control frames for this
2951          * station. This needs testing. I believe right now this
2952          * enables *all* control frames, which is OK.. but
2953          * but we should see if we can improve on granularity */
2954         if (*new_flags & FIF_CONTROL)
2955                 rfilt |= AR5K_RX_FILTER_CONTROL;
2956
2957         /* Additional settings per mode -- this is per ath5k */
2958
2959         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2960
2961         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2962                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2963                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2964         if (sc->opmode != NL80211_IFTYPE_STATION)
2965                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2966         if (sc->opmode != NL80211_IFTYPE_AP &&
2967                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2968                 test_bit(ATH_STAT_PROMISC, sc->status))
2969                 rfilt |= AR5K_RX_FILTER_PROM;
2970         if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2971                 sc->opmode == NL80211_IFTYPE_ADHOC ||
2972                 sc->opmode == NL80211_IFTYPE_AP)
2973                 rfilt |= AR5K_RX_FILTER_BEACON;
2974         if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2975                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2976                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2977
2978         /* Set filters */
2979         ath5k_hw_set_rx_filter(ah, rfilt);
2980
2981         /* Set multicast bits */
2982         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2983         /* Set the cached hw filter flags, this will alter actually
2984          * be set in HW */
2985         sc->filter_flags = rfilt;
2986 }
2987
2988 static int
2989 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2990                 const u8 *local_addr, const u8 *addr,
2991                 struct ieee80211_key_conf *key)
2992 {
2993         struct ath5k_softc *sc = hw->priv;
2994         int ret = 0;
2995
2996         if (modparam_nohwcrypt)
2997                 return -EOPNOTSUPP;
2998
2999         switch (key->alg) {
3000         case ALG_WEP:
3001         case ALG_TKIP:
3002                 break;
3003         case ALG_CCMP:
3004                 return -EOPNOTSUPP;
3005         default:
3006                 WARN_ON(1);
3007                 return -EINVAL;
3008         }
3009
3010         mutex_lock(&sc->lock);
3011
3012         switch (cmd) {
3013         case SET_KEY:
3014                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
3015                 if (ret) {
3016                         ATH5K_ERR(sc, "can't set the key\n");
3017                         goto unlock;
3018                 }
3019                 __set_bit(key->keyidx, sc->keymap);
3020                 key->hw_key_idx = key->keyidx;
3021                 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3022                                IEEE80211_KEY_FLAG_GENERATE_MMIC);
3023                 break;
3024         case DISABLE_KEY:
3025                 ath5k_hw_reset_key(sc->ah, key->keyidx);
3026                 __clear_bit(key->keyidx, sc->keymap);
3027                 break;
3028         default:
3029                 ret = -EINVAL;
3030                 goto unlock;
3031         }
3032
3033 unlock:
3034         mmiowb();
3035         mutex_unlock(&sc->lock);
3036         return ret;
3037 }
3038
3039 static int
3040 ath5k_get_stats(struct ieee80211_hw *hw,
3041                 struct ieee80211_low_level_stats *stats)
3042 {
3043         struct ath5k_softc *sc = hw->priv;
3044         struct ath5k_hw *ah = sc->ah;
3045
3046         /* Force update */
3047         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3048
3049         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3050
3051         return 0;
3052 }
3053
3054 static int
3055 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3056                 struct ieee80211_tx_queue_stats *stats)
3057 {
3058         struct ath5k_softc *sc = hw->priv;
3059
3060         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3061
3062         return 0;
3063 }
3064
3065 static u64
3066 ath5k_get_tsf(struct ieee80211_hw *hw)
3067 {
3068         struct ath5k_softc *sc = hw->priv;
3069
3070         return ath5k_hw_get_tsf64(sc->ah);
3071 }
3072
3073 static void
3074 ath5k_reset_tsf(struct ieee80211_hw *hw)
3075 {
3076         struct ath5k_softc *sc = hw->priv;
3077
3078         /*
3079          * in IBSS mode we need to update the beacon timers too.
3080          * this will also reset the TSF if we call it with 0
3081          */
3082         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3083                 ath5k_beacon_update_timers(sc, 0);
3084         else
3085                 ath5k_hw_reset_tsf(sc->ah);
3086 }
3087
3088 static int
3089 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3090 {
3091         unsigned long flags;
3092         int ret;
3093
3094         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3095
3096         spin_lock_irqsave(&sc->block, flags);
3097         ath5k_txbuf_free(sc, sc->bbuf);
3098         sc->bbuf->skb = skb;
3099         ret = ath5k_beacon_setup(sc, sc->bbuf);
3100         if (ret)
3101                 sc->bbuf->skb = NULL;
3102         spin_unlock_irqrestore(&sc->block, flags);
3103         if (!ret) {
3104                 ath5k_beacon_config(sc);
3105                 mmiowb();
3106         }
3107
3108         return ret;
3109 }
3110 static void
3111 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3112 {
3113         struct ath5k_softc *sc = hw->priv;
3114         struct ath5k_hw *ah = sc->ah;
3115         u32 rfilt;
3116         rfilt = ath5k_hw_get_rx_filter(ah);
3117         if (enable)
3118                 rfilt |= AR5K_RX_FILTER_BEACON;
3119         else
3120                 rfilt &= ~AR5K_RX_FILTER_BEACON;
3121         ath5k_hw_set_rx_filter(ah, rfilt);
3122         sc->filter_flags = rfilt;
3123 }
3124
3125 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3126                                     struct ieee80211_vif *vif,
3127                                     struct ieee80211_bss_conf *bss_conf,
3128                                     u32 changes)
3129 {
3130         struct ath5k_softc *sc = hw->priv;
3131         if (changes & BSS_CHANGED_ASSOC) {
3132                 mutex_lock(&sc->lock);
3133                 sc->assoc = bss_conf->assoc;
3134                 if (sc->opmode == NL80211_IFTYPE_STATION)
3135                         set_beacon_filter(hw, sc->assoc);
3136                 mutex_unlock(&sc->lock);
3137         }
3138 }