1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/timer.h>
22 #include <linux/mii.h>
23 #include <linux/list.h>
24 #include <linux/pci.h>
25 #include <linux/device.h>
26 #include <linux/highmem.h>
27 #include <linux/workqueue.h>
28 #include <linux/inet_lro.h>
29 #include <linux/i2c.h>
34 #define EFX_MAX_LRO_DESCRIPTORS 8
35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
37 /**************************************************************************
41 **************************************************************************/
42 #ifndef EFX_DRIVER_NAME
43 #define EFX_DRIVER_NAME "sfc"
45 #define EFX_DRIVER_VERSION "2.2"
47 #ifdef EFX_ENABLE_DEBUG
48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
55 /* Un-rate-limited logging */
56 #define EFX_ERR(efx, fmt, args...) \
57 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
59 #define EFX_INFO(efx, fmt, args...) \
60 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
62 #ifdef EFX_ENABLE_DEBUG
63 #define EFX_LOG(efx, fmt, args...) \
64 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
66 #define EFX_LOG(efx, fmt, args...) \
67 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
70 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
72 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
74 /* Rate-limited logging */
75 #define EFX_ERR_RL(efx, fmt, args...) \
76 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
78 #define EFX_INFO_RL(efx, fmt, args...) \
79 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
81 #define EFX_LOG_RL(efx, fmt, args...) \
82 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
84 /**************************************************************************
88 **************************************************************************/
90 #define EFX_MAX_CHANNELS 32
91 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
93 #define EFX_TX_QUEUE_OFFLOAD_CSUM 0
94 #define EFX_TX_QUEUE_NO_CSUM 1
95 #define EFX_TX_QUEUE_COUNT 2
98 * struct efx_special_buffer - An Efx special buffer
99 * @addr: CPU base address of the buffer
100 * @dma_addr: DMA base address of the buffer
101 * @len: Buffer length, in bytes
102 * @index: Buffer index within controller;s buffer table
103 * @entries: Number of buffer table entries
105 * Special buffers are used for the event queues and the TX and RX
106 * descriptor queues for each channel. They are *not* used for the
107 * actual transmit and receive buffers.
109 * Note that for Falcon, TX and RX descriptor queues live in host memory.
110 * Allocation and freeing procedures must take this into account.
112 struct efx_special_buffer {
121 * struct efx_tx_buffer - An Efx TX buffer
122 * @skb: The associated socket buffer.
123 * Set only on the final fragment of a packet; %NULL for all other
124 * fragments. When this fragment completes, then we can free this
126 * @tsoh: The associated TSO header structure, or %NULL if this
127 * buffer is not a TSO header.
128 * @dma_addr: DMA address of the fragment.
129 * @len: Length of this fragment.
130 * This field is zero when the queue slot is empty.
131 * @continuation: True if this fragment is not the end of a packet.
132 * @unmap_single: True if pci_unmap_single should be used.
133 * @unmap_len: Length of this fragment to unmap
135 struct efx_tx_buffer {
136 const struct sk_buff *skb;
137 struct efx_tso_header *tsoh;
142 unsigned short unmap_len;
146 * struct efx_tx_queue - An Efx TX queue
148 * This is a ring buffer of TX fragments.
149 * Since the TX completion path always executes on the same
150 * CPU and the xmit path can operate on different CPUs,
151 * performance is increased by ensuring that the completion
152 * path and the xmit path operate on different cache lines.
153 * This is particularly important if the xmit path is always
154 * executing on one CPU which is different from the completion
155 * path. There is also a cache line for members which are
156 * read but not written on the fast path.
158 * @efx: The associated Efx NIC
159 * @queue: DMA queue number
160 * @channel: The associated channel
161 * @buffer: The software buffer ring
162 * @txd: The hardware descriptor ring
163 * @read_count: Current read pointer.
164 * This is the number of buffers that have been removed from both rings.
165 * @stopped: Stopped count.
166 * Set if this TX queue is currently stopping its port.
167 * @insert_count: Current insert pointer
168 * This is the number of buffers that have been added to the
170 * @write_count: Current write pointer
171 * This is the number of buffers that have been added to the
173 * @old_read_count: The value of read_count when last checked.
174 * This is here for performance reasons. The xmit path will
175 * only get the up-to-date value of read_count if this
176 * variable indicates that the queue is full. This is to
177 * avoid cache-line ping-pong between the xmit path and the
179 * @tso_headers_free: A list of TSO headers allocated for this TX queue
180 * that are not in use, and so available for new TSO sends. The list
181 * is protected by the TX queue lock.
182 * @tso_bursts: Number of times TSO xmit invoked by kernel
183 * @tso_long_headers: Number of packets with headers too long for standard
185 * @tso_packets: Number of packets via the TSO xmit path
187 struct efx_tx_queue {
188 /* Members which don't change on the fast path */
189 struct efx_nic *efx ____cacheline_aligned_in_smp;
191 struct efx_channel *channel;
193 struct efx_tx_buffer *buffer;
194 struct efx_special_buffer txd;
196 /* Members used mainly on the completion path */
197 unsigned int read_count ____cacheline_aligned_in_smp;
200 /* Members used only on the xmit path */
201 unsigned int insert_count ____cacheline_aligned_in_smp;
202 unsigned int write_count;
203 unsigned int old_read_count;
204 struct efx_tso_header *tso_headers_free;
205 unsigned int tso_bursts;
206 unsigned int tso_long_headers;
207 unsigned int tso_packets;
211 * struct efx_rx_buffer - An Efx RX data buffer
212 * @dma_addr: DMA base address of the buffer
213 * @skb: The associated socket buffer, if any.
214 * If both this and page are %NULL, the buffer slot is currently free.
215 * @page: The associated page buffer, if any.
216 * If both this and skb are %NULL, the buffer slot is currently free.
217 * @data: Pointer to ethernet header
218 * @len: Buffer length, in bytes.
219 * @unmap_addr: DMA address to unmap
221 struct efx_rx_buffer {
227 dma_addr_t unmap_addr;
231 * struct efx_rx_queue - An Efx RX queue
232 * @efx: The associated Efx NIC
233 * @queue: DMA queue number
234 * @used: Queue is used by net driver
235 * @channel: The associated channel
236 * @buffer: The software buffer ring
237 * @rxd: The hardware descriptor ring
238 * @added_count: Number of buffers added to the receive queue.
239 * @notified_count: Number of buffers given to NIC (<= @added_count).
240 * @removed_count: Number of buffers removed from the receive queue.
241 * @add_lock: Receive queue descriptor add spin lock.
242 * This lock must be held in order to add buffers to the RX
243 * descriptor ring (rxd and buffer) and to update added_count (but
244 * not removed_count).
245 * @max_fill: RX descriptor maximum fill level (<= ring size)
246 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
248 * @fast_fill_limit: The level to which a fast fill will fill
249 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
250 * @min_fill: RX descriptor minimum non-zero fill level.
251 * This records the minimum fill level observed when a ring
252 * refill was triggered.
253 * @min_overfill: RX descriptor minimum overflow fill level.
254 * This records the minimum fill level at which RX queue
255 * overflow was observed. It should never be set.
256 * @alloc_page_count: RX allocation strategy counter.
257 * @alloc_skb_count: RX allocation strategy counter.
258 * @work: Descriptor push work thread
259 * @buf_page: Page for next RX buffer.
260 * We can use a single page for multiple RX buffers. This tracks
261 * the remaining space in the allocation.
262 * @buf_dma_addr: Page's DMA address.
263 * @buf_data: Page's host address.
265 struct efx_rx_queue {
269 struct efx_channel *channel;
270 struct efx_rx_buffer *buffer;
271 struct efx_special_buffer rxd;
277 unsigned int max_fill;
278 unsigned int fast_fill_trigger;
279 unsigned int fast_fill_limit;
280 unsigned int min_fill;
281 unsigned int min_overfill;
282 unsigned int alloc_page_count;
283 unsigned int alloc_skb_count;
284 struct delayed_work work;
285 unsigned int slow_fill_count;
287 struct page *buf_page;
288 dma_addr_t buf_dma_addr;
293 * struct efx_buffer - An Efx general-purpose buffer
294 * @addr: host base address of the buffer
295 * @dma_addr: DMA base address of the buffer
296 * @len: Buffer length, in bytes
298 * Falcon uses these buffers for its interrupt status registers and
308 /* Flags for channel->used_flags */
309 #define EFX_USED_BY_RX 1
310 #define EFX_USED_BY_TX 2
311 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
313 enum efx_rx_alloc_method {
314 RX_ALLOC_METHOD_AUTO = 0,
315 RX_ALLOC_METHOD_SKB = 1,
316 RX_ALLOC_METHOD_PAGE = 2,
320 * struct efx_channel - An Efx channel
322 * A channel comprises an event queue, at least one TX queue, at least
323 * one RX queue, and an associated tasklet for processing the event
326 * @efx: Associated Efx NIC
327 * @evqnum: Event queue number
328 * @channel: Channel instance number
329 * @used_flags: Channel is used by net driver
330 * @enabled: Channel enabled indicator
331 * @irq: IRQ number (MSI and MSI-X only)
332 * @irq_moderation: IRQ moderation value (in us)
333 * @napi_dev: Net device used with NAPI
334 * @napi_str: NAPI control structure
335 * @reset_work: Scheduled reset work thread
336 * @work_pending: Is work pending via NAPI?
337 * @eventq: Event queue buffer
338 * @eventq_read_ptr: Event queue read pointer
339 * @last_eventq_read_ptr: Last event queue read pointer value.
340 * @eventq_magic: Event queue magic value for driver-generated test events
341 * @lro_mgr: LRO state
342 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
343 * and diagnostic counters
344 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
346 * @rx_alloc_pop_pages: RX allocation method currently in use for popping
348 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
349 * @n_rx_ip_frag_err: Count of RX IP fragment errors
350 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
351 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
352 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
353 * @n_rx_overlength: Count of RX_OVERLENGTH errors
354 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
363 unsigned int irq_moderation;
364 struct net_device *napi_dev;
365 struct napi_struct napi_str;
367 struct efx_special_buffer eventq;
368 unsigned int eventq_read_ptr;
369 unsigned int last_eventq_read_ptr;
370 unsigned int eventq_magic;
372 struct net_lro_mgr lro_mgr;
374 int rx_alloc_push_pages;
375 int rx_alloc_pop_pages;
377 unsigned n_rx_tobe_disc;
378 unsigned n_rx_ip_frag_err;
379 unsigned n_rx_ip_hdr_chksum_err;
380 unsigned n_rx_tcp_udp_chksum_err;
381 unsigned n_rx_frm_trunc;
382 unsigned n_rx_overlength;
383 unsigned n_skbuff_leaks;
385 /* Used to pipeline received packets in order to optimise memory
386 * access with prefetches.
388 struct efx_rx_buffer *rx_pkt;
394 * struct efx_blinker - S/W LED blinking context
395 * @led_num: LED ID (board-specific meaning)
396 * @state: Current state - on or off
397 * @resubmit: Timer resubmission flag
398 * @timer: Control timer for blinking
404 struct timer_list timer;
409 * struct efx_board - board information
410 * @type: Board model type
411 * @major: Major rev. ('A', 'B' ...)
412 * @minor: Minor rev. (0, 1, ...)
413 * @init: Initialisation function
414 * @init_leds: Sets up board LEDs
415 * @set_fault_led: Turns the fault LED on or off
416 * @blink: Starts/stops blinking
417 * @fini: Cleanup function
418 * @blinker: used to blink LEDs in software
419 * @hwmon_client: I2C client for hardware monitor
420 * @ioexp_client: I2C client for power/port control
426 int (*init) (struct efx_nic *nic);
427 /* As the LEDs are typically attached to the PHY, LEDs
428 * have a separate init callback that happens later than
430 int (*init_leds)(struct efx_nic *efx);
431 void (*set_fault_led) (struct efx_nic *efx, bool state);
432 void (*blink) (struct efx_nic *efx, bool start);
433 void (*fini) (struct efx_nic *nic);
434 struct efx_blinker blinker;
435 struct i2c_client *hwmon_client, *ioexp_client;
438 #define STRING_TABLE_LOOKUP(val, member) \
439 member ## _names[val]
442 /* Be careful if altering to correct macro below */
443 EFX_INT_MODE_MSIX = 0,
444 EFX_INT_MODE_MSI = 1,
445 EFX_INT_MODE_LEGACY = 2,
446 EFX_INT_MODE_MAX /* Insert any new items before this */
448 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
452 PHY_TYPE_CX4_RTMR = 1,
453 PHY_TYPE_1G_ALASKA = 2,
454 PHY_TYPE_10XPRESS = 3,
457 PHY_TYPE_MAX /* Insert any new items before this */
460 #define PHY_ADDR_INVALID 0xff
466 STATE_RESETTING = 3, /* rtnl_lock always held */
472 * Alignment of page-allocated RX buffers
474 * Controls the number of bytes inserted at the start of an RX buffer.
475 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
476 * of the skb->head for hardware DMA].
478 #if defined(__i386__) || defined(__x86_64__)
479 #define EFX_PAGE_IP_ALIGN 0
481 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
485 * Alignment of the skb->head which wraps a page-allocated RX buffer
487 * The skb allocated to wrap an rx_buffer can have this alignment. Since
488 * the data is memcpy'd from the rx_buf, it does not need to be equal to
491 #define EFX_PAGE_SKB_ALIGN 2
493 /* Forward declaration */
496 /* Pseudo bit-mask flow control field */
504 * struct efx_phy_operations - Efx PHY operations table
505 * @init: Initialise PHY
506 * @fini: Shut down PHY
507 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
508 * @clear_interrupt: Clear down interrupt
510 * @check_hw: Check hardware
511 * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset)
512 * @mmds: MMD presence mask
513 * @loopbacks: Supported loopback modes mask
515 struct efx_phy_operations {
516 int (*init) (struct efx_nic *efx);
517 void (*fini) (struct efx_nic *efx);
518 void (*reconfigure) (struct efx_nic *efx);
519 void (*clear_interrupt) (struct efx_nic *efx);
520 int (*check_hw) (struct efx_nic *efx);
521 void (*reset_xaui) (struct efx_nic *efx);
527 * Efx extended statistics
529 * Not all statistics are provided by all supported MACs. The purpose
530 * is this structure is to contain the raw statistics provided by each
533 struct efx_mac_stats {
537 unsigned long tx_packets;
538 unsigned long tx_bad;
539 unsigned long tx_pause;
540 unsigned long tx_control;
541 unsigned long tx_unicast;
542 unsigned long tx_multicast;
543 unsigned long tx_broadcast;
544 unsigned long tx_lt64;
546 unsigned long tx_65_to_127;
547 unsigned long tx_128_to_255;
548 unsigned long tx_256_to_511;
549 unsigned long tx_512_to_1023;
550 unsigned long tx_1024_to_15xx;
551 unsigned long tx_15xx_to_jumbo;
552 unsigned long tx_gtjumbo;
553 unsigned long tx_collision;
554 unsigned long tx_single_collision;
555 unsigned long tx_multiple_collision;
556 unsigned long tx_excessive_collision;
557 unsigned long tx_deferred;
558 unsigned long tx_late_collision;
559 unsigned long tx_excessive_deferred;
560 unsigned long tx_non_tcpudp;
561 unsigned long tx_mac_src_error;
562 unsigned long tx_ip_src_error;
566 unsigned long rx_packets;
567 unsigned long rx_good;
568 unsigned long rx_bad;
569 unsigned long rx_pause;
570 unsigned long rx_control;
571 unsigned long rx_unicast;
572 unsigned long rx_multicast;
573 unsigned long rx_broadcast;
574 unsigned long rx_lt64;
576 unsigned long rx_65_to_127;
577 unsigned long rx_128_to_255;
578 unsigned long rx_256_to_511;
579 unsigned long rx_512_to_1023;
580 unsigned long rx_1024_to_15xx;
581 unsigned long rx_15xx_to_jumbo;
582 unsigned long rx_gtjumbo;
583 unsigned long rx_bad_lt64;
584 unsigned long rx_bad_64_to_15xx;
585 unsigned long rx_bad_15xx_to_jumbo;
586 unsigned long rx_bad_gtjumbo;
587 unsigned long rx_overflow;
588 unsigned long rx_missed;
589 unsigned long rx_false_carrier;
590 unsigned long rx_symbol_error;
591 unsigned long rx_align_error;
592 unsigned long rx_length_error;
593 unsigned long rx_internal_error;
594 unsigned long rx_good_lt64;
597 /* Number of bits used in a multicast filter hash address */
598 #define EFX_MCAST_HASH_BITS 8
600 /* Number of (single-bit) entries in a multicast filter hash */
601 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
603 /* An Efx multicast filter hash */
604 union efx_multicast_hash {
605 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
606 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
610 * struct efx_nic - an Efx NIC
611 * @name: Device name (net device name or bus id before net device registered)
612 * @pci_dev: The PCI device
613 * @type: Controller type attributes
614 * @legacy_irq: IRQ number
615 * @workqueue: Workqueue for port reconfigures and the HW monitor.
616 * Work items do not hold and must not acquire RTNL.
617 * @reset_workqueue: Workqueue for resets. Work item will acquire RTNL.
618 * @reset_work: Scheduled reset workitem
619 * @monitor_work: Hardware monitor workitem
620 * @membase_phys: Memory BAR value as physical address
621 * @membase: Memory BAR value
622 * @biu_lock: BIU (bus interface unit) lock
623 * @interrupt_mode: Interrupt mode
624 * @i2c_adap: I2C adapter
625 * @board_info: Board-level information
626 * @state: Device state flag. Serialised by the rtnl_lock.
627 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
628 * @tx_queue: TX DMA queues
629 * @rx_queue: RX DMA queues
631 * @rss_queues: Number of RSS queues
632 * @rx_buffer_len: RX buffer length
633 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
634 * @irq_status: Interrupt status buffer
635 * @last_irq_cpu: Last CPU to handle interrupt.
636 * This register is written with the SMP processor ID whenever an
637 * interrupt is handled. It is used by falcon_test_interrupt()
638 * to verify that an interrupt has occurred.
639 * @spi_flash: SPI flash device
640 * This field will be %NULL if no flash device is present.
641 * @spi_eeprom: SPI EEPROM device
642 * This field will be %NULL if no EEPROM device is present.
643 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
644 * @nic_data: Hardware dependant state
645 * @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
646 * efx_reconfigure_port()
647 * @port_enabled: Port enabled indicator.
648 * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
649 * efx_reconfigure_work with kernel interfaces. Safe to read under any
650 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
651 * be held to modify it.
652 * @port_initialized: Port initialized?
653 * @net_dev: Operating system network device. Consider holding the rtnl lock
654 * @rx_checksum_enabled: RX checksumming enabled
655 * @netif_stop_count: Port stop count
656 * @netif_stop_lock: Port stop lock
657 * @mac_stats: MAC statistics. These include all statistics the MACs
658 * can provide. Generic code converts these into a standard
659 * &struct net_device_stats.
660 * @stats_buffer: DMA buffer for statistics
661 * @stats_lock: Statistics update lock
662 * @mac_address: Permanent MAC address
663 * @phy_type: PHY type
664 * @phy_lock: PHY access lock
665 * @phy_op: PHY interface
666 * @phy_data: PHY private data (including PHY-specific stats)
667 * @mii: PHY interface
668 * @tx_disabled: PHY transmitter turned off
669 * @link_up: Link status
670 * @link_options: Link options (MII/GMII format)
671 * @n_link_state_changes: Number of times the link has changed state
672 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
673 * @multicast_hash: Multicast hash table
674 * @flow_control: Flow control flags - separate RX/TX so can't use link_options
675 * @reconfigure_work: work item for dealing with PHY events
676 * @loopback_mode: Loopback status
677 * @loopback_modes: Supported loopback mode bitmask
678 * @loopback_selftest: Offline self-test private state
680 * The @priv field of the corresponding &struct net_device points to
685 struct pci_dev *pci_dev;
686 const struct efx_nic_type *type;
688 struct workqueue_struct *workqueue;
689 struct workqueue_struct *reset_workqueue;
690 struct work_struct reset_work;
691 struct delayed_work monitor_work;
692 resource_size_t membase_phys;
693 void __iomem *membase;
695 enum efx_int_mode interrupt_mode;
697 struct i2c_adapter i2c_adap;
698 struct efx_board board_info;
700 enum nic_state state;
701 enum reset_type reset_pending;
703 struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
704 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
705 struct efx_channel channel[EFX_MAX_CHANNELS];
708 unsigned int rx_buffer_len;
709 unsigned int rx_buffer_order;
711 struct efx_buffer irq_status;
712 volatile signed int last_irq_cpu;
714 struct efx_spi_device *spi_flash;
715 struct efx_spi_device *spi_eeprom;
717 unsigned n_rx_nodesc_drop_cnt;
719 struct falcon_nic_data *nic_data;
721 struct mutex mac_lock;
724 bool port_initialized;
725 struct net_device *net_dev;
726 bool rx_checksum_enabled;
728 atomic_t netif_stop_count;
729 spinlock_t netif_stop_lock;
731 struct efx_mac_stats mac_stats;
732 struct efx_buffer stats_buffer;
733 spinlock_t stats_lock;
735 unsigned char mac_address[ETH_ALEN];
737 enum phy_type phy_type;
739 struct efx_phy_operations *phy_op;
741 struct mii_if_info mii;
745 unsigned int link_options;
746 unsigned int n_link_state_changes;
749 union efx_multicast_hash multicast_hash;
750 enum efx_fc_type flow_control;
751 struct work_struct reconfigure_work;
754 enum efx_loopback_mode loopback_mode;
755 unsigned int loopback_modes;
757 void *loopback_selftest;
760 static inline int efx_dev_registered(struct efx_nic *efx)
762 return efx->net_dev->reg_state == NETREG_REGISTERED;
765 /* Net device name, for inclusion in log messages if it has been registered.
766 * Use efx->name not efx->net_dev->name so that races with (un)registration
769 static inline const char *efx_dev_name(struct efx_nic *efx)
771 return efx_dev_registered(efx) ? efx->name : "";
775 * struct efx_nic_type - Efx device type definition
776 * @mem_bar: Memory BAR number
777 * @mem_map_size: Memory BAR mapped size
778 * @txd_ptr_tbl_base: TX descriptor ring base address
779 * @rxd_ptr_tbl_base: RX descriptor ring base address
780 * @buf_tbl_base: Buffer table base address
781 * @evq_ptr_tbl_base: Event queue pointer table base address
782 * @evq_rptr_tbl_base: Event queue read-pointer table base address
783 * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
784 * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
785 * @evq_size: Event queue size (must be a power of two)
786 * @max_dma_mask: Maximum possible DMA mask
787 * @tx_dma_mask: TX DMA mask
788 * @bug5391_mask: Address mask for bug 5391 workaround
789 * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
790 * @rx_xon_thresh: RX FIFO XON watermark (bytes)
791 * @rx_buffer_padding: Padding added to each RX buffer
792 * @max_interrupt_mode: Highest capability interrupt mode supported
793 * from &enum efx_init_mode.
794 * @phys_addr_channels: Number of channels with physically addressed
797 struct efx_nic_type {
798 unsigned int mem_bar;
799 unsigned int mem_map_size;
800 unsigned int txd_ptr_tbl_base;
801 unsigned int rxd_ptr_tbl_base;
802 unsigned int buf_tbl_base;
803 unsigned int evq_ptr_tbl_base;
804 unsigned int evq_rptr_tbl_base;
806 unsigned int txd_ring_mask;
807 unsigned int rxd_ring_mask;
808 unsigned int evq_size;
810 unsigned int tx_dma_mask;
811 unsigned bug5391_mask;
815 unsigned int rx_buffer_padding;
816 unsigned int max_interrupt_mode;
817 unsigned int phys_addr_channels;
820 /**************************************************************************
822 * Prototypes and inline functions
824 *************************************************************************/
826 /* Iterate over all used channels */
827 #define efx_for_each_channel(_channel, _efx) \
828 for (_channel = &_efx->channel[0]; \
829 _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
831 if (!_channel->used_flags) \
835 /* Iterate over all used TX queues */
836 #define efx_for_each_tx_queue(_tx_queue, _efx) \
837 for (_tx_queue = &_efx->tx_queue[0]; \
838 _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
841 /* Iterate over all TX queues belonging to a channel */
842 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
843 for (_tx_queue = &_channel->efx->tx_queue[0]; \
844 _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
846 if (_tx_queue->channel != _channel) \
850 /* Iterate over all used RX queues */
851 #define efx_for_each_rx_queue(_rx_queue, _efx) \
852 for (_rx_queue = &_efx->rx_queue[0]; \
853 _rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES]; \
855 if (!_rx_queue->used) \
859 /* Iterate over all RX queues belonging to a channel */
860 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
861 for (_rx_queue = &_channel->efx->rx_queue[0]; \
862 _rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES]; \
864 if ((!_rx_queue->used) || \
865 (_rx_queue->channel != _channel)) \
869 /* Returns a pointer to the specified receive buffer in the RX
872 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
875 return (&rx_queue->buffer[index]);
878 /* Set bit in a little-endian bitfield */
879 static inline void set_bit_le(unsigned nr, unsigned char *addr)
881 addr[nr / 8] |= (1 << (nr % 8));
884 /* Clear bit in a little-endian bitfield */
885 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
887 addr[nr / 8] &= ~(1 << (nr % 8));
892 * EFX_MAX_FRAME_LEN - calculate maximum frame length
894 * This calculates the maximum frame length that will be used for a
895 * given MTU. The frame length will be equal to the MTU plus a
896 * constant amount of header space and padding. This is the quantity
897 * that the net driver will program into the MAC as the maximum frame
900 * The 10G MAC used in Falcon requires 8-byte alignment on the frame
901 * length, so we round up to the nearest 8.
903 #define EFX_MAX_FRAME_LEN(mtu) \
904 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
907 #endif /* EFX_NET_DRIVER_H */