2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
26 #include <asm/byteorder.h>
31 #undef SERIAL_DEBUG_PCI
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *, struct pciserial_board *,
46 struct uart_port *, int);
47 void (*exit)(struct pci_dev *dev);
50 #define PCI_NUM_BAR_RESOURCES 6
52 struct serial_private {
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
60 static void moan_device(const char *str, struct pci_dev *dev)
62 printk(KERN_WARNING "%s: %s\n"
63 KERN_WARNING "Please send the output of lspci -vv, this\n"
64 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 KERN_WARNING "manufacturer and name of serial board or\n"
66 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
72 setup_port(struct serial_private *priv, struct uart_port *port,
73 int bar, int offset, int regshift)
75 struct pci_dev *dev = priv->dev;
76 unsigned long base, len;
78 if (bar >= PCI_NUM_BAR_RESOURCES)
81 base = pci_resource_start(dev, bar);
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 len = pci_resource_len(dev, bar);
86 if (!priv->remapped_bar[bar])
87 priv->remapped_bar[bar] = ioremap_nocache(base, len);
88 if (!priv->remapped_bar[bar])
91 port->iotype = UPIO_MEM;
93 port->mapbase = base + offset;
94 port->membase = priv->remapped_bar[bar] + offset;
95 port->regshift = regshift;
97 port->iotype = UPIO_PORT;
98 port->iobase = base + offset;
100 port->membase = NULL;
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 static int addidata_apci7800_setup(struct serial_private *priv,
110 struct pciserial_board *board,
111 struct uart_port *port, int idx)
113 unsigned int bar = 0, offset = board->first_offset;
114 bar = FL_GET_BASE(board->flags);
117 offset += idx * board->uart_offset;
118 } else if ((idx >= 2) && (idx < 4)) {
120 offset += ((idx - 2) * board->uart_offset);
121 } else if ((idx >= 4) && (idx < 6)) {
123 offset += ((idx - 4) * board->uart_offset);
124 } else if (idx >= 6) {
126 offset += ((idx - 6) * board->uart_offset);
129 return setup_port(priv, port, bar, offset, board->reg_shift);
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
137 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
138 struct uart_port *port, int idx)
140 unsigned int bar, offset = board->first_offset;
142 bar = FL_GET_BASE(board->flags);
147 offset += (idx - 4) * board->uart_offset;
150 return setup_port(priv, port, bar, offset, board->reg_shift);
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
160 static int pci_hp_diva_init(struct pci_dev *dev)
164 switch (dev->subsystem_device) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
191 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
192 struct uart_port *port, int idx)
194 unsigned int offset = board->first_offset;
195 unsigned int bar = FL_GET_BASE(board->flags);
197 switch (priv->dev->subsystem_device) {
198 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
212 offset += idx * board->uart_offset;
214 return setup_port(priv, port, bar, offset, board->reg_shift);
218 * Added for EKF Intel i960 serial boards
220 static int pci_inteli960ni_init(struct pci_dev *dev)
222 unsigned long oldval;
224 if (!(dev->subsystem_device & 0x1000))
227 /* is firmware started? */
228 pci_read_config_dword(dev, 0x44, (void *)&oldval);
229 if (oldval == 0x00001000L) { /* RESET value */
230 printk(KERN_DEBUG "Local i960 firmware missing");
237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
238 * that the card interrupt be explicitly enabled or disabled. This
239 * seems to be mainly needed on card using the PLX which also use I/O
242 static int pci_plx9050_init(struct pci_dev *dev)
247 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
248 moan_device("no memory in bar 0", dev);
253 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
254 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
258 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
269 * enable/disable interrupts
271 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274 writel(irq_config, p + 0x4c);
277 * Read the register back to ensure that it took effect.
285 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
300 * Read the register back to ensure that it took effect.
307 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
309 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
310 struct uart_port *port, int idx)
312 unsigned int bar, offset = board->first_offset;
317 /* first four channels map to 0, 0x100, 0x200, 0x300 */
318 offset += idx * board->uart_offset;
319 } else if (idx < 8) {
320 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
321 offset += idx * board->uart_offset + 0xC00;
322 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return setup_port(priv, port, bar, offset, board->reg_shift);
329 * This does initialization for PMC OCTALPRO cards:
330 * maps the device memory, resets the UARTs (needed, bc
331 * if the module is removed and inserted again, the card
332 * is in the sleep mode) and enables global interrupt.
335 /* global control register offset for SBS PMC-OctalPro */
336 #define OCT_REG_CR_OFF 0x500
338 static int sbs_init(struct pci_dev *dev)
342 p = ioremap_nocache(pci_resource_start(dev, 0),
343 pci_resource_len(dev, 0));
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10, p + OCT_REG_CR_OFF);
350 writeb(0x0, p + OCT_REG_CR_OFF);
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p + OCT_REG_CR_OFF);
360 * Disables the global interrupt of PMC-OctalPro
363 static void __devexit sbs_exit(struct pci_dev *dev)
367 p = ioremap_nocache(pci_resource_start(dev, 0),
368 pci_resource_len(dev, 0));
369 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
371 writeb(0, p + OCT_REG_CR_OFF);
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
393 * Note: all 10x cards have PCI device ids 0x10..
394 * all 20x cards have PCI device ids 0x20..
396 * There are also Quartet Serial cards which use Oxford Semiconductor
397 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
399 * Note: some SIIG cards are probed by the parport_serial object.
402 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
403 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
405 static int pci_siig10x_init(struct pci_dev *dev)
410 switch (dev->device & 0xfff8) {
411 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 default: /* 1S1P, 4S */
422 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
426 writew(readw(p + 0x28) & data, p + 0x28);
432 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
433 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
435 static int pci_siig20x_init(struct pci_dev *dev)
439 /* Change clock frequency for the first UART. */
440 pci_read_config_byte(dev, 0x6f, &data);
441 pci_write_config_byte(dev, 0x6f, data & 0xef);
443 /* If this card has 2 UART, we have to do the same with second UART. */
444 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
445 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
446 pci_read_config_byte(dev, 0x73, &data);
447 pci_write_config_byte(dev, 0x73, data & 0xef);
452 static int pci_siig_init(struct pci_dev *dev)
454 unsigned int type = dev->device & 0xff00;
457 return pci_siig10x_init(dev);
458 else if (type == 0x2000)
459 return pci_siig20x_init(dev);
461 moan_device("Unknown SIIG card", dev);
465 static int pci_siig_setup(struct serial_private *priv,
466 struct pciserial_board *board,
467 struct uart_port *port, int idx)
469 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
473 offset = (idx - 4) * 8;
476 return setup_port(priv, port, bar, offset, 0);
480 * Timedia has an explosion of boards, and to avoid the PCI table from
481 * growing *huge*, we use this function to collapse some 70 entries
482 * in the PCI table into one, for sanity's and compactness's sake.
484 static const unsigned short timedia_single_port[] = {
485 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488 static const unsigned short timedia_dual_port[] = {
489 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
490 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
491 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
492 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
496 static const unsigned short timedia_quad_port[] = {
497 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
498 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
499 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
503 static const unsigned short timedia_eight_port[] = {
504 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
505 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508 static const struct timedia_struct {
510 const unsigned short *ids;
512 { 1, timedia_single_port },
513 { 2, timedia_dual_port },
514 { 4, timedia_quad_port },
515 { 8, timedia_eight_port }
518 static int pci_timedia_init(struct pci_dev *dev)
520 const unsigned short *ids;
523 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
524 ids = timedia_data[i].ids;
525 for (j = 0; ids[j]; j++)
526 if (dev->subsystem_device == ids[j])
527 return timedia_data[i].num;
533 * Timedia/SUNIX uses a mixture of BARs and offsets
534 * Ugh, this is ugly as all hell --- TYT
537 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
538 struct uart_port *port, int idx)
540 unsigned int bar = 0, offset = board->first_offset;
547 offset = board->uart_offset;
554 offset = board->uart_offset;
563 return setup_port(priv, port, bar, offset, board->reg_shift);
567 * Some Titan cards are also a little weird
570 titan_400l_800l_setup(struct serial_private *priv,
571 struct pciserial_board *board,
572 struct uart_port *port, int idx)
574 unsigned int bar, offset = board->first_offset;
585 offset = (idx - 2) * board->uart_offset;
588 return setup_port(priv, port, bar, offset, board->reg_shift);
591 static int pci_xircom_init(struct pci_dev *dev)
597 static int pci_netmos_init(struct pci_dev *dev)
599 /* subdevice 0x00PS means <P> parallel, <S> serial */
600 unsigned int num_serial = dev->subsystem_device & 0xf;
608 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
610 * These chips are available with optionally one parallel port and up to
611 * two serial ports. Unfortunately they all have the same product id.
613 * Basic configuration is done over a region of 32 I/O ports. The base
614 * ioport is called INTA or INTC, depending on docs/other drivers.
616 * The region of the 32 I/O ports is configured in POSIO0R...
620 #define ITE_887x_MISCR 0x9c
621 #define ITE_887x_INTCBAR 0x78
622 #define ITE_887x_UARTBAR 0x7c
623 #define ITE_887x_PS0BAR 0x10
624 #define ITE_887x_POSIO0 0x60
627 #define ITE_887x_IOSIZE 32
628 /* I/O space size (bits 26-24; 8 bytes = 011b) */
629 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
630 /* I/O space size (bits 26-24; 32 bytes = 101b) */
631 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
632 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
633 #define ITE_887x_POSIO_SPEED (3 << 29)
634 /* enable IO_Space bit */
635 #define ITE_887x_POSIO_ENABLE (1 << 31)
637 static int pci_ite887x_init(struct pci_dev *dev)
639 /* inta_addr are the configuration addresses of the ITE */
640 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
643 struct resource *iobase = NULL;
644 u32 miscr, uartbar, ioport;
646 /* search for the base-ioport */
648 while (inta_addr[i] && iobase == NULL) {
649 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
651 if (iobase != NULL) {
652 /* write POSIO0R - speed | size | ioport */
653 pci_write_config_dword(dev, ITE_887x_POSIO0,
654 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
655 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
656 /* write INTCBAR - ioport */
657 pci_write_config_dword(dev, ITE_887x_INTCBAR,
659 ret = inb(inta_addr[i]);
661 /* ioport connected */
664 release_region(iobase->start, ITE_887x_IOSIZE);
671 printk(KERN_ERR "ite887x: could not find iobase\n");
675 /* start of undocumented type checking (see parport_pc.c) */
676 type = inb(iobase->start + 0x18) & 0x0f;
679 case 0x2: /* ITE8871 (1P) */
680 case 0xa: /* ITE8875 (1P) */
683 case 0xe: /* ITE8872 (2S1P) */
686 case 0x6: /* ITE8873 (1S) */
689 case 0x8: /* ITE8874 (2S) */
693 moan_device("Unknown ITE887x", dev);
697 /* configure all serial ports */
698 for (i = 0; i < ret; i++) {
699 /* read the I/O port from the device */
700 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
702 ioport &= 0x0000FF00; /* the actual base address */
703 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
704 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
705 ITE_887x_POSIO_IOSIZE_8 | ioport);
707 /* write the ioport to the UARTBAR */
708 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
709 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
710 uartbar |= (ioport << (16 * i)); /* set the ioport */
711 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
713 /* get current config */
714 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
715 /* disable interrupts (UARTx_Routing[3:0]) */
716 miscr &= ~(0xf << (12 - 4 * i));
717 /* activate the UART (UARTx_En) */
718 miscr |= 1 << (23 - i);
719 /* write new config with activated UART */
720 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
724 /* the device has no UARTs if we get here */
725 release_region(iobase->start, ITE_887x_IOSIZE);
731 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
734 /* the ioport is bit 0-15 in POSIO0R */
735 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
737 release_region(ioport, ITE_887x_IOSIZE);
741 * Oxford Semiconductor Inc.
742 * Check that device is part of the Tornado range of devices, then determine
743 * the number of ports available on the device.
745 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
748 unsigned long deviceID;
749 unsigned int number_uarts = 0;
751 /* OxSemi Tornado devices are all 0xCxxx */
752 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
753 (dev->device & 0xF000) != 0xC000)
756 p = pci_iomap(dev, 0, 5);
760 deviceID = ioread32(p);
762 if (deviceID == 0x07000200) {
763 number_uarts = ioread8(p + 4);
765 "%d ports detected on Oxford PCI Express device\n",
773 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
774 struct uart_port *port, int idx)
776 unsigned int bar, offset = board->first_offset, maxnr;
778 bar = FL_GET_BASE(board->flags);
779 if (board->flags & FL_BASE_BARS)
782 offset += idx * board->uart_offset;
784 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
785 (board->reg_shift + 3);
787 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
790 return setup_port(priv, port, bar, offset, board->reg_shift);
793 /* This should be in linux/pci_ids.h */
794 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
795 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
796 #define PCI_DEVICE_ID_OCTPRO 0x0001
797 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
798 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
799 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
800 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
802 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
803 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
806 * Master list of serial port init/setup/exit quirks.
807 * This does not describe the general nature of the port.
808 * (ie, baud base, number and location of ports, etc)
810 * This list is ordered alphabetically by vendor then device.
811 * Specific entries must come before more generic entries.
813 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
815 * ADDI-DATA GmbH communication cards <info@addi-data.com>
818 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
819 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
822 .setup = addidata_apci7800_setup,
825 * AFAVLAB cards - these may be called via parport_serial
826 * It is not clear whether this applies to all products.
829 .vendor = PCI_VENDOR_ID_AFAVLAB,
830 .device = PCI_ANY_ID,
831 .subvendor = PCI_ANY_ID,
832 .subdevice = PCI_ANY_ID,
833 .setup = afavlab_setup,
839 .vendor = PCI_VENDOR_ID_HP,
840 .device = PCI_DEVICE_ID_HP_DIVA,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .init = pci_hp_diva_init,
844 .setup = pci_hp_diva_setup,
850 .vendor = PCI_VENDOR_ID_INTEL,
851 .device = PCI_DEVICE_ID_INTEL_80960_RP,
853 .subdevice = PCI_ANY_ID,
854 .init = pci_inteli960ni_init,
855 .setup = pci_default_setup,
861 .vendor = PCI_VENDOR_ID_ITE,
862 .device = PCI_DEVICE_ID_ITE_8872,
863 .subvendor = PCI_ANY_ID,
864 .subdevice = PCI_ANY_ID,
865 .init = pci_ite887x_init,
866 .setup = pci_default_setup,
867 .exit = __devexit_p(pci_ite887x_exit),
873 .vendor = PCI_VENDOR_ID_PANACOM,
874 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
875 .subvendor = PCI_ANY_ID,
876 .subdevice = PCI_ANY_ID,
877 .init = pci_plx9050_init,
878 .setup = pci_default_setup,
879 .exit = __devexit_p(pci_plx9050_exit),
882 .vendor = PCI_VENDOR_ID_PANACOM,
883 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .init = pci_plx9050_init,
887 .setup = pci_default_setup,
888 .exit = __devexit_p(pci_plx9050_exit),
894 .vendor = PCI_VENDOR_ID_PLX,
895 .device = PCI_DEVICE_ID_PLX_9030,
896 .subvendor = PCI_SUBVENDOR_ID_PERLE,
897 .subdevice = PCI_ANY_ID,
898 .setup = pci_default_setup,
901 .vendor = PCI_VENDOR_ID_PLX,
902 .device = PCI_DEVICE_ID_PLX_9050,
903 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
904 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
905 .init = pci_plx9050_init,
906 .setup = pci_default_setup,
907 .exit = __devexit_p(pci_plx9050_exit),
910 .vendor = PCI_VENDOR_ID_PLX,
911 .device = PCI_DEVICE_ID_PLX_9050,
912 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
913 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
914 .init = pci_plx9050_init,
915 .setup = pci_default_setup,
916 .exit = __devexit_p(pci_plx9050_exit),
919 .vendor = PCI_VENDOR_ID_PLX,
920 .device = PCI_DEVICE_ID_PLX_9050,
921 .subvendor = PCI_VENDOR_ID_PLX,
922 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
923 .init = pci_plx9050_init,
924 .setup = pci_default_setup,
925 .exit = __devexit_p(pci_plx9050_exit),
928 .vendor = PCI_VENDOR_ID_PLX,
929 .device = PCI_DEVICE_ID_PLX_ROMULUS,
930 .subvendor = PCI_VENDOR_ID_PLX,
931 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
932 .init = pci_plx9050_init,
933 .setup = pci_default_setup,
934 .exit = __devexit_p(pci_plx9050_exit),
937 * SBS Technologies, Inc., PMC-OCTALPRO 232
940 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
941 .device = PCI_DEVICE_ID_OCTPRO,
942 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
943 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
946 .exit = __devexit_p(sbs_exit),
949 * SBS Technologies, Inc., PMC-OCTALPRO 422
952 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
953 .device = PCI_DEVICE_ID_OCTPRO,
954 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
955 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
958 .exit = __devexit_p(sbs_exit),
961 * SBS Technologies, Inc., P-Octal 232
964 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
965 .device = PCI_DEVICE_ID_OCTPRO,
966 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
967 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
970 .exit = __devexit_p(sbs_exit),
973 * SBS Technologies, Inc., P-Octal 422
976 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
977 .device = PCI_DEVICE_ID_OCTPRO,
978 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
979 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
982 .exit = __devexit_p(sbs_exit),
985 * SIIG cards - these may be called via parport_serial
988 .vendor = PCI_VENDOR_ID_SIIG,
989 .device = PCI_ANY_ID,
990 .subvendor = PCI_ANY_ID,
991 .subdevice = PCI_ANY_ID,
992 .init = pci_siig_init,
993 .setup = pci_siig_setup,
999 .vendor = PCI_VENDOR_ID_TITAN,
1000 .device = PCI_DEVICE_ID_TITAN_400L,
1001 .subvendor = PCI_ANY_ID,
1002 .subdevice = PCI_ANY_ID,
1003 .setup = titan_400l_800l_setup,
1006 .vendor = PCI_VENDOR_ID_TITAN,
1007 .device = PCI_DEVICE_ID_TITAN_800L,
1008 .subvendor = PCI_ANY_ID,
1009 .subdevice = PCI_ANY_ID,
1010 .setup = titan_400l_800l_setup,
1016 .vendor = PCI_VENDOR_ID_TIMEDIA,
1017 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1018 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1019 .subdevice = PCI_ANY_ID,
1020 .init = pci_timedia_init,
1021 .setup = pci_timedia_setup,
1024 .vendor = PCI_VENDOR_ID_TIMEDIA,
1025 .device = PCI_ANY_ID,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .setup = pci_timedia_setup,
1034 .vendor = PCI_VENDOR_ID_XIRCOM,
1035 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1036 .subvendor = PCI_ANY_ID,
1037 .subdevice = PCI_ANY_ID,
1038 .init = pci_xircom_init,
1039 .setup = pci_default_setup,
1042 * Netmos cards - these may be called via parport_serial
1045 .vendor = PCI_VENDOR_ID_NETMOS,
1046 .device = PCI_ANY_ID,
1047 .subvendor = PCI_ANY_ID,
1048 .subdevice = PCI_ANY_ID,
1049 .init = pci_netmos_init,
1050 .setup = pci_default_setup,
1053 * For Oxford Semiconductor and Mainpine
1056 .vendor = PCI_VENDOR_ID_OXSEMI,
1057 .device = PCI_ANY_ID,
1058 .subvendor = PCI_ANY_ID,
1059 .subdevice = PCI_ANY_ID,
1060 .init = pci_oxsemi_tornado_init,
1061 .setup = pci_default_setup,
1064 .vendor = PCI_VENDOR_ID_MAINPINE,
1065 .device = PCI_ANY_ID,
1066 .subvendor = PCI_ANY_ID,
1067 .subdevice = PCI_ANY_ID,
1068 .init = pci_oxsemi_tornado_init,
1069 .setup = pci_default_setup,
1072 * Default "match everything" terminator entry
1075 .vendor = PCI_ANY_ID,
1076 .device = PCI_ANY_ID,
1077 .subvendor = PCI_ANY_ID,
1078 .subdevice = PCI_ANY_ID,
1079 .setup = pci_default_setup,
1083 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1085 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1088 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1090 struct pci_serial_quirk *quirk;
1092 for (quirk = pci_serial_quirks; ; quirk++)
1093 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1094 quirk_id_matches(quirk->device, dev->device) &&
1095 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1096 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1101 static inline int get_pci_irq(struct pci_dev *dev,
1102 struct pciserial_board *board)
1104 if (board->flags & FL_NOIRQ)
1111 * This is the configuration table for all of the PCI serial boards
1112 * which we support. It is directly indexed by the pci_board_num_t enum
1113 * value, which is encoded in the pci_device_id PCI probe table's
1114 * driver_data member.
1116 * The makeup of these names are:
1117 * pbn_bn{_bt}_n_baud{_offsetinhex}
1119 * bn = PCI BAR number
1120 * bt = Index using PCI BARs
1121 * n = number of serial ports
1123 * offsetinhex = offset for each sequential port (in hex)
1125 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1127 * Please note: in theory if n = 1, _bt infix should make no difference.
1128 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1130 enum pci_board_num_t {
1150 pbn_b0_2_1843200_200,
1151 pbn_b0_4_1843200_200,
1152 pbn_b0_8_1843200_200,
1215 * Board-specific versions.
1223 pbn_oxsemi_1_4000000,
1224 pbn_oxsemi_2_4000000,
1225 pbn_oxsemi_4_4000000,
1226 pbn_oxsemi_8_4000000,
1240 * uart_offset - the space between channels
1241 * reg_shift - describes how the UART registers are mapped
1242 * to PCI memory by the card.
1243 * For example IER register on SBS, Inc. PMC-OctPro is located at
1244 * offset 0x10 from the UART base, while UART_IER is defined as 1
1245 * in include/linux/serial_reg.h,
1246 * see first lines of serial_in() and serial_out() in 8250.c
1249 static struct pciserial_board pci_boards[] __devinitdata = {
1253 .base_baud = 115200,
1256 [pbn_b0_1_115200] = {
1259 .base_baud = 115200,
1262 [pbn_b0_2_115200] = {
1265 .base_baud = 115200,
1268 [pbn_b0_4_115200] = {
1271 .base_baud = 115200,
1274 [pbn_b0_5_115200] = {
1277 .base_baud = 115200,
1280 [pbn_b0_8_115200] = {
1283 .base_baud = 115200,
1286 [pbn_b0_1_921600] = {
1289 .base_baud = 921600,
1292 [pbn_b0_2_921600] = {
1295 .base_baud = 921600,
1298 [pbn_b0_4_921600] = {
1301 .base_baud = 921600,
1305 [pbn_b0_2_1130000] = {
1308 .base_baud = 1130000,
1312 [pbn_b0_4_1152000] = {
1315 .base_baud = 1152000,
1319 [pbn_b0_2_1843200] = {
1322 .base_baud = 1843200,
1325 [pbn_b0_4_1843200] = {
1328 .base_baud = 1843200,
1332 [pbn_b0_2_1843200_200] = {
1335 .base_baud = 1843200,
1336 .uart_offset = 0x200,
1338 [pbn_b0_4_1843200_200] = {
1341 .base_baud = 1843200,
1342 .uart_offset = 0x200,
1344 [pbn_b0_8_1843200_200] = {
1347 .base_baud = 1843200,
1348 .uart_offset = 0x200,
1350 [pbn_b0_1_4000000] = {
1353 .base_baud = 4000000,
1357 [pbn_b0_bt_1_115200] = {
1358 .flags = FL_BASE0|FL_BASE_BARS,
1360 .base_baud = 115200,
1363 [pbn_b0_bt_2_115200] = {
1364 .flags = FL_BASE0|FL_BASE_BARS,
1366 .base_baud = 115200,
1369 [pbn_b0_bt_8_115200] = {
1370 .flags = FL_BASE0|FL_BASE_BARS,
1372 .base_baud = 115200,
1376 [pbn_b0_bt_1_460800] = {
1377 .flags = FL_BASE0|FL_BASE_BARS,
1379 .base_baud = 460800,
1382 [pbn_b0_bt_2_460800] = {
1383 .flags = FL_BASE0|FL_BASE_BARS,
1385 .base_baud = 460800,
1388 [pbn_b0_bt_4_460800] = {
1389 .flags = FL_BASE0|FL_BASE_BARS,
1391 .base_baud = 460800,
1395 [pbn_b0_bt_1_921600] = {
1396 .flags = FL_BASE0|FL_BASE_BARS,
1398 .base_baud = 921600,
1401 [pbn_b0_bt_2_921600] = {
1402 .flags = FL_BASE0|FL_BASE_BARS,
1404 .base_baud = 921600,
1407 [pbn_b0_bt_4_921600] = {
1408 .flags = FL_BASE0|FL_BASE_BARS,
1410 .base_baud = 921600,
1413 [pbn_b0_bt_8_921600] = {
1414 .flags = FL_BASE0|FL_BASE_BARS,
1416 .base_baud = 921600,
1420 [pbn_b1_1_115200] = {
1423 .base_baud = 115200,
1426 [pbn_b1_2_115200] = {
1429 .base_baud = 115200,
1432 [pbn_b1_4_115200] = {
1435 .base_baud = 115200,
1438 [pbn_b1_8_115200] = {
1441 .base_baud = 115200,
1445 [pbn_b1_1_921600] = {
1448 .base_baud = 921600,
1451 [pbn_b1_2_921600] = {
1454 .base_baud = 921600,
1457 [pbn_b1_4_921600] = {
1460 .base_baud = 921600,
1463 [pbn_b1_8_921600] = {
1466 .base_baud = 921600,
1469 [pbn_b1_2_1250000] = {
1472 .base_baud = 1250000,
1476 [pbn_b1_bt_1_115200] = {
1477 .flags = FL_BASE1|FL_BASE_BARS,
1479 .base_baud = 115200,
1483 [pbn_b1_bt_2_921600] = {
1484 .flags = FL_BASE1|FL_BASE_BARS,
1486 .base_baud = 921600,
1490 [pbn_b1_1_1382400] = {
1493 .base_baud = 1382400,
1496 [pbn_b1_2_1382400] = {
1499 .base_baud = 1382400,
1502 [pbn_b1_4_1382400] = {
1505 .base_baud = 1382400,
1508 [pbn_b1_8_1382400] = {
1511 .base_baud = 1382400,
1515 [pbn_b2_1_115200] = {
1518 .base_baud = 115200,
1521 [pbn_b2_2_115200] = {
1524 .base_baud = 115200,
1527 [pbn_b2_4_115200] = {
1530 .base_baud = 115200,
1533 [pbn_b2_8_115200] = {
1536 .base_baud = 115200,
1540 [pbn_b2_1_460800] = {
1543 .base_baud = 460800,
1546 [pbn_b2_4_460800] = {
1549 .base_baud = 460800,
1552 [pbn_b2_8_460800] = {
1555 .base_baud = 460800,
1558 [pbn_b2_16_460800] = {
1561 .base_baud = 460800,
1565 [pbn_b2_1_921600] = {
1568 .base_baud = 921600,
1571 [pbn_b2_4_921600] = {
1574 .base_baud = 921600,
1577 [pbn_b2_8_921600] = {
1580 .base_baud = 921600,
1584 [pbn_b2_bt_1_115200] = {
1585 .flags = FL_BASE2|FL_BASE_BARS,
1587 .base_baud = 115200,
1590 [pbn_b2_bt_2_115200] = {
1591 .flags = FL_BASE2|FL_BASE_BARS,
1593 .base_baud = 115200,
1596 [pbn_b2_bt_4_115200] = {
1597 .flags = FL_BASE2|FL_BASE_BARS,
1599 .base_baud = 115200,
1603 [pbn_b2_bt_2_921600] = {
1604 .flags = FL_BASE2|FL_BASE_BARS,
1606 .base_baud = 921600,
1609 [pbn_b2_bt_4_921600] = {
1610 .flags = FL_BASE2|FL_BASE_BARS,
1612 .base_baud = 921600,
1616 [pbn_b3_2_115200] = {
1619 .base_baud = 115200,
1622 [pbn_b3_4_115200] = {
1625 .base_baud = 115200,
1628 [pbn_b3_8_115200] = {
1631 .base_baud = 115200,
1636 * Entries following this are board-specific.
1645 .base_baud = 921600,
1646 .uart_offset = 0x400,
1650 .flags = FL_BASE2|FL_BASE_BARS,
1652 .base_baud = 921600,
1653 .uart_offset = 0x400,
1657 .flags = FL_BASE2|FL_BASE_BARS,
1659 .base_baud = 921600,
1660 .uart_offset = 0x400,
1664 [pbn_exsys_4055] = {
1667 .base_baud = 115200,
1671 /* I think this entry is broken - the first_offset looks wrong --rmk */
1672 [pbn_plx_romulus] = {
1675 .base_baud = 921600,
1676 .uart_offset = 8 << 2,
1678 .first_offset = 0x03,
1682 * This board uses the size of PCI Base region 0 to
1683 * signal now many ports are available
1686 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1688 .base_baud = 115200,
1691 [pbn_oxsemi_1_4000000] = {
1694 .base_baud = 4000000,
1695 .uart_offset = 0x200,
1696 .first_offset = 0x1000,
1698 [pbn_oxsemi_2_4000000] = {
1701 .base_baud = 4000000,
1702 .uart_offset = 0x200,
1703 .first_offset = 0x1000,
1705 [pbn_oxsemi_4_4000000] = {
1708 .base_baud = 4000000,
1709 .uart_offset = 0x200,
1710 .first_offset = 0x1000,
1712 [pbn_oxsemi_8_4000000] = {
1715 .base_baud = 4000000,
1716 .uart_offset = 0x200,
1717 .first_offset = 0x1000,
1722 * EKF addition for i960 Boards form EKF with serial port.
1725 [pbn_intel_i960] = {
1728 .base_baud = 921600,
1729 .uart_offset = 8 << 2,
1731 .first_offset = 0x10000,
1734 .flags = FL_BASE0|FL_NOIRQ,
1736 .base_baud = 458333,
1739 .first_offset = 0x20178,
1743 * Computone - uses IOMEM.
1745 [pbn_computone_4] = {
1748 .base_baud = 921600,
1749 .uart_offset = 0x40,
1751 .first_offset = 0x200,
1753 [pbn_computone_6] = {
1756 .base_baud = 921600,
1757 .uart_offset = 0x40,
1759 .first_offset = 0x200,
1761 [pbn_computone_8] = {
1764 .base_baud = 921600,
1765 .uart_offset = 0x40,
1767 .first_offset = 0x200,
1772 .base_baud = 460800,
1777 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1778 * Only basic 16550A support.
1779 * XR17C15[24] are not tested, but they should work.
1781 [pbn_exar_XR17C152] = {
1784 .base_baud = 921600,
1785 .uart_offset = 0x200,
1787 [pbn_exar_XR17C154] = {
1790 .base_baud = 921600,
1791 .uart_offset = 0x200,
1793 [pbn_exar_XR17C158] = {
1796 .base_baud = 921600,
1797 .uart_offset = 0x200,
1800 * PA Semi PWRficient PA6T-1682M on-chip UART
1802 [pbn_pasemi_1682M] = {
1805 .base_baud = 8333333,
1809 static const struct pci_device_id softmodem_blacklist[] = {
1810 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1814 * Given a complete unknown PCI device, try to use some heuristics to
1815 * guess what the configuration might be, based on the pitiful PCI
1816 * serial specs. Returns 0 on success, 1 on failure.
1818 static int __devinit
1819 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1821 const struct pci_device_id *blacklist;
1822 int num_iomem, num_port, first_port = -1, i;
1825 * If it is not a communications device or the programming
1826 * interface is greater than 6, give up.
1828 * (Should we try to make guesses for multiport serial devices
1831 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1832 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1833 (dev->class & 0xff) > 6)
1837 * Do not access blacklisted devices that are known not to
1838 * feature serial ports.
1840 for (blacklist = softmodem_blacklist;
1841 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1843 if (dev->vendor == blacklist->vendor &&
1844 dev->device == blacklist->device)
1848 num_iomem = num_port = 0;
1849 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1850 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1852 if (first_port == -1)
1855 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1860 * If there is 1 or 0 iomem regions, and exactly one port,
1861 * use it. We guess the number of ports based on the IO
1864 if (num_iomem <= 1 && num_port == 1) {
1865 board->flags = first_port;
1866 board->num_ports = pci_resource_len(dev, first_port) / 8;
1871 * Now guess if we've got a board which indexes by BARs.
1872 * Each IO BAR should be 8 bytes, and they should follow
1877 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1878 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1879 pci_resource_len(dev, i) == 8 &&
1880 (first_port == -1 || (first_port + num_port) == i)) {
1882 if (first_port == -1)
1888 board->flags = first_port | FL_BASE_BARS;
1889 board->num_ports = num_port;
1897 serial_pci_matches(struct pciserial_board *board,
1898 struct pciserial_board *guessed)
1901 board->num_ports == guessed->num_ports &&
1902 board->base_baud == guessed->base_baud &&
1903 board->uart_offset == guessed->uart_offset &&
1904 board->reg_shift == guessed->reg_shift &&
1905 board->first_offset == guessed->first_offset;
1908 struct serial_private *
1909 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1911 struct uart_port serial_port;
1912 struct serial_private *priv;
1913 struct pci_serial_quirk *quirk;
1914 int rc, nr_ports, i;
1916 nr_ports = board->num_ports;
1919 * Find an init and setup quirks.
1921 quirk = find_quirk(dev);
1924 * Run the new-style initialization function.
1925 * The initialization function returns:
1927 * 0 - use board->num_ports
1928 * >0 - number of ports
1931 rc = quirk->init(dev);
1940 priv = kzalloc(sizeof(struct serial_private) +
1941 sizeof(unsigned int) * nr_ports,
1944 priv = ERR_PTR(-ENOMEM);
1949 priv->quirk = quirk;
1951 memset(&serial_port, 0, sizeof(struct uart_port));
1952 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1953 serial_port.uartclk = board->base_baud * 16;
1954 serial_port.irq = get_pci_irq(dev, board);
1955 serial_port.dev = &dev->dev;
1957 for (i = 0; i < nr_ports; i++) {
1958 if (quirk->setup(priv, board, &serial_port, i))
1961 #ifdef SERIAL_DEBUG_PCI
1962 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1963 serial_port.iobase, serial_port.irq, serial_port.iotype);
1966 priv->line[i] = serial8250_register_port(&serial_port);
1967 if (priv->line[i] < 0) {
1968 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1981 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1983 void pciserial_remove_ports(struct serial_private *priv)
1985 struct pci_serial_quirk *quirk;
1988 for (i = 0; i < priv->nr; i++)
1989 serial8250_unregister_port(priv->line[i]);
1991 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1992 if (priv->remapped_bar[i])
1993 iounmap(priv->remapped_bar[i]);
1994 priv->remapped_bar[i] = NULL;
1998 * Find the exit quirks.
2000 quirk = find_quirk(priv->dev);
2002 quirk->exit(priv->dev);
2006 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2008 void pciserial_suspend_ports(struct serial_private *priv)
2012 for (i = 0; i < priv->nr; i++)
2013 if (priv->line[i] >= 0)
2014 serial8250_suspend_port(priv->line[i]);
2016 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2018 void pciserial_resume_ports(struct serial_private *priv)
2023 * Ensure that the board is correctly configured.
2025 if (priv->quirk->init)
2026 priv->quirk->init(priv->dev);
2028 for (i = 0; i < priv->nr; i++)
2029 if (priv->line[i] >= 0)
2030 serial8250_resume_port(priv->line[i]);
2032 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2035 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2036 * to the arrangement of serial ports on a PCI card.
2038 static int __devinit
2039 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2041 struct serial_private *priv;
2042 struct pciserial_board *board, tmp;
2045 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2046 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2051 board = &pci_boards[ent->driver_data];
2053 rc = pci_enable_device(dev);
2057 if (ent->driver_data == pbn_default) {
2059 * Use a copy of the pci_board entry for this;
2060 * avoid changing entries in the table.
2062 memcpy(&tmp, board, sizeof(struct pciserial_board));
2066 * We matched one of our class entries. Try to
2067 * determine the parameters of this board.
2069 rc = serial_pci_guess_board(dev, board);
2074 * We matched an explicit entry. If we are able to
2075 * detect this boards settings with our heuristic,
2076 * then we no longer need this entry.
2078 memcpy(&tmp, &pci_boards[pbn_default],
2079 sizeof(struct pciserial_board));
2080 rc = serial_pci_guess_board(dev, &tmp);
2081 if (rc == 0 && serial_pci_matches(board, &tmp))
2082 moan_device("Redundant entry in serial pci_table.",
2086 priv = pciserial_init_ports(dev, board);
2087 if (!IS_ERR(priv)) {
2088 pci_set_drvdata(dev, priv);
2095 pci_disable_device(dev);
2099 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2101 struct serial_private *priv = pci_get_drvdata(dev);
2103 pci_set_drvdata(dev, NULL);
2105 pciserial_remove_ports(priv);
2107 pci_disable_device(dev);
2111 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2113 struct serial_private *priv = pci_get_drvdata(dev);
2116 pciserial_suspend_ports(priv);
2118 pci_save_state(dev);
2119 pci_set_power_state(dev, pci_choose_state(dev, state));
2123 static int pciserial_resume_one(struct pci_dev *dev)
2126 struct serial_private *priv = pci_get_drvdata(dev);
2128 pci_set_power_state(dev, PCI_D0);
2129 pci_restore_state(dev);
2133 * The device may have been disabled. Re-enable it.
2135 err = pci_enable_device(dev);
2136 /* FIXME: We cannot simply error out here */
2138 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2139 pciserial_resume_ports(priv);
2145 static struct pci_device_id serial_pci_tbl[] = {
2146 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2147 PCI_SUBVENDOR_ID_CONNECT_TECH,
2148 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2150 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2151 PCI_SUBVENDOR_ID_CONNECT_TECH,
2152 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2154 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2155 PCI_SUBVENDOR_ID_CONNECT_TECH,
2156 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2158 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2159 PCI_SUBVENDOR_ID_CONNECT_TECH,
2160 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2162 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2163 PCI_SUBVENDOR_ID_CONNECT_TECH,
2164 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2166 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2167 PCI_SUBVENDOR_ID_CONNECT_TECH,
2168 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2170 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2171 PCI_SUBVENDOR_ID_CONNECT_TECH,
2172 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2174 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2175 PCI_SUBVENDOR_ID_CONNECT_TECH,
2176 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2178 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2179 PCI_SUBVENDOR_ID_CONNECT_TECH,
2180 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2182 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2183 PCI_SUBVENDOR_ID_CONNECT_TECH,
2184 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2186 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2187 PCI_SUBVENDOR_ID_CONNECT_TECH,
2188 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2190 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2191 PCI_SUBVENDOR_ID_CONNECT_TECH,
2192 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2194 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2195 PCI_SUBVENDOR_ID_CONNECT_TECH,
2196 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2198 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2199 PCI_SUBVENDOR_ID_CONNECT_TECH,
2200 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2202 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2203 PCI_SUBVENDOR_ID_CONNECT_TECH,
2204 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2207 PCI_SUBVENDOR_ID_CONNECT_TECH,
2208 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2210 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2211 PCI_SUBVENDOR_ID_CONNECT_TECH,
2212 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2214 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2215 PCI_VENDOR_ID_AFAVLAB,
2216 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2218 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2219 PCI_SUBVENDOR_ID_CONNECT_TECH,
2220 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2221 pbn_b0_2_1843200_200 },
2222 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2223 PCI_SUBVENDOR_ID_CONNECT_TECH,
2224 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2225 pbn_b0_4_1843200_200 },
2226 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2227 PCI_SUBVENDOR_ID_CONNECT_TECH,
2228 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2229 pbn_b0_8_1843200_200 },
2230 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2231 PCI_SUBVENDOR_ID_CONNECT_TECH,
2232 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2233 pbn_b0_2_1843200_200 },
2234 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2235 PCI_SUBVENDOR_ID_CONNECT_TECH,
2236 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2237 pbn_b0_4_1843200_200 },
2238 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2239 PCI_SUBVENDOR_ID_CONNECT_TECH,
2240 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2241 pbn_b0_8_1843200_200 },
2242 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2243 PCI_SUBVENDOR_ID_CONNECT_TECH,
2244 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2245 pbn_b0_2_1843200_200 },
2246 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2247 PCI_SUBVENDOR_ID_CONNECT_TECH,
2248 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2249 pbn_b0_4_1843200_200 },
2250 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2251 PCI_SUBVENDOR_ID_CONNECT_TECH,
2252 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2253 pbn_b0_8_1843200_200 },
2254 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2255 PCI_SUBVENDOR_ID_CONNECT_TECH,
2256 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2257 pbn_b0_2_1843200_200 },
2258 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2259 PCI_SUBVENDOR_ID_CONNECT_TECH,
2260 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2261 pbn_b0_4_1843200_200 },
2262 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2263 PCI_SUBVENDOR_ID_CONNECT_TECH,
2264 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2265 pbn_b0_8_1843200_200 },
2267 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2269 pbn_b2_bt_1_115200 },
2270 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2272 pbn_b2_bt_2_115200 },
2273 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2275 pbn_b2_bt_4_115200 },
2276 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2278 pbn_b2_bt_2_115200 },
2279 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2281 pbn_b2_bt_4_115200 },
2282 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2285 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2289 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2291 pbn_b2_bt_2_115200 },
2292 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2294 pbn_b2_bt_2_921600 },
2296 * VScom SPCOM800, from sl@s.pl
2298 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2301 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2304 /* Unknown card - subdevice 0x1584 */
2305 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2307 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2309 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2310 PCI_SUBVENDOR_ID_KEYSPAN,
2311 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2313 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2316 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2319 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2320 PCI_VENDOR_ID_ESDGMBH,
2321 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2323 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2324 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2325 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2327 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2328 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2329 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2331 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2332 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2333 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2336 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2337 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2340 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2341 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2344 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2345 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2347 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2348 PCI_SUBVENDOR_ID_EXSYS,
2349 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2352 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2356 0x10b5, 0x106a, 0, 0,
2358 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2370 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2371 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2374 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2375 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2380 * The below card is a little controversial since it is the
2381 * subject of a PCI vendor/device ID clash. (See
2382 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2383 * For now just used the hex ID 0x950a.
2385 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2388 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2393 pbn_b0_bt_2_921600 },
2396 * Oxford Semiconductor Inc. Tornado PCI express device range.
2398 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2404 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2406 pbn_oxsemi_1_4000000 },
2407 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2409 pbn_oxsemi_1_4000000 },
2410 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2413 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2416 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2418 pbn_oxsemi_1_4000000 },
2419 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2421 pbn_oxsemi_1_4000000 },
2422 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2425 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2428 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2431 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2434 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2436 pbn_oxsemi_2_4000000 },
2437 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2439 pbn_oxsemi_2_4000000 },
2440 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2442 pbn_oxsemi_4_4000000 },
2443 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2445 pbn_oxsemi_4_4000000 },
2446 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2448 pbn_oxsemi_8_4000000 },
2449 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2451 pbn_oxsemi_8_4000000 },
2452 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2454 pbn_oxsemi_1_4000000 },
2455 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2457 pbn_oxsemi_1_4000000 },
2458 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2460 pbn_oxsemi_1_4000000 },
2461 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2463 pbn_oxsemi_1_4000000 },
2464 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2466 pbn_oxsemi_1_4000000 },
2467 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2469 pbn_oxsemi_1_4000000 },
2470 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2472 pbn_oxsemi_1_4000000 },
2473 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2475 pbn_oxsemi_1_4000000 },
2476 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2478 pbn_oxsemi_1_4000000 },
2479 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2481 pbn_oxsemi_1_4000000 },
2482 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2484 pbn_oxsemi_1_4000000 },
2485 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2487 pbn_oxsemi_1_4000000 },
2488 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2490 pbn_oxsemi_1_4000000 },
2491 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2493 pbn_oxsemi_1_4000000 },
2494 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2496 pbn_oxsemi_1_4000000 },
2497 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2499 pbn_oxsemi_1_4000000 },
2500 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2502 pbn_oxsemi_1_4000000 },
2503 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2505 pbn_oxsemi_1_4000000 },
2506 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508 pbn_oxsemi_1_4000000 },
2509 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2511 pbn_oxsemi_1_4000000 },
2512 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2514 pbn_oxsemi_1_4000000 },
2515 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2517 pbn_oxsemi_1_4000000 },
2518 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2520 pbn_oxsemi_1_4000000 },
2521 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2523 pbn_oxsemi_1_4000000 },
2524 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2526 pbn_oxsemi_1_4000000 },
2527 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2529 pbn_oxsemi_1_4000000 },
2531 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2533 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2534 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2535 pbn_oxsemi_1_4000000 },
2536 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2537 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2538 pbn_oxsemi_2_4000000 },
2539 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2540 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2541 pbn_oxsemi_4_4000000 },
2542 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2543 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2544 pbn_oxsemi_8_4000000 },
2546 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2547 * from skokodyn@yahoo.com
2549 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2550 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2552 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2553 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2555 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2556 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2558 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2559 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2563 * Digitan DS560-558, from jimd@esoft.com
2565 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2570 * Titan Electronic cards
2571 * The 400L and 800L have a custom setup quirk.
2573 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2590 pbn_b1_bt_2_921600 },
2591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2593 pbn_b0_bt_4_921600 },
2594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2596 pbn_b0_bt_8_921600 },
2598 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2601 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2604 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2607 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2609 pbn_b2_bt_2_921600 },
2610 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2612 pbn_b2_bt_2_921600 },
2613 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2615 pbn_b2_bt_2_921600 },
2616 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2618 pbn_b2_bt_4_921600 },
2619 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2621 pbn_b2_bt_4_921600 },
2622 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2624 pbn_b2_bt_4_921600 },
2625 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2628 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2631 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2634 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2636 pbn_b0_bt_2_921600 },
2637 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2639 pbn_b0_bt_2_921600 },
2640 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2642 pbn_b0_bt_2_921600 },
2643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2645 pbn_b0_bt_4_921600 },
2646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2648 pbn_b0_bt_4_921600 },
2649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2651 pbn_b0_bt_4_921600 },
2652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2654 pbn_b0_bt_8_921600 },
2655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2657 pbn_b0_bt_8_921600 },
2658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2660 pbn_b0_bt_8_921600 },
2663 * Computone devices submitted by Doug McNash dmcnash@computone.com
2665 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2666 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2667 0, 0, pbn_computone_4 },
2668 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2669 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2670 0, 0, pbn_computone_8 },
2671 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2672 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2673 0, 0, pbn_computone_6 },
2675 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2678 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2679 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2680 pbn_b0_bt_1_921600 },
2683 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2685 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2687 pbn_b0_bt_8_115200 },
2688 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2690 pbn_b0_bt_8_115200 },
2692 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2694 pbn_b0_bt_2_115200 },
2695 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2697 pbn_b0_bt_2_115200 },
2698 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2700 pbn_b0_bt_2_115200 },
2701 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2703 pbn_b0_bt_4_460800 },
2704 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2706 pbn_b0_bt_4_460800 },
2707 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2709 pbn_b0_bt_2_460800 },
2710 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2712 pbn_b0_bt_2_460800 },
2713 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2715 pbn_b0_bt_2_460800 },
2716 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2718 pbn_b0_bt_1_115200 },
2719 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2721 pbn_b0_bt_1_460800 },
2724 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2725 * Cards are identified by their subsystem vendor IDs, which
2726 * (in hex) match the model number.
2728 * Note that JC140x are RS422/485 cards which require ox950
2729 * ACR = 0x10, and as such are not currently fully supported.
2731 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2732 0x1204, 0x0004, 0, 0,
2734 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2735 0x1208, 0x0004, 0, 0,
2737 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2738 0x1402, 0x0002, 0, 0,
2739 pbn_b0_2_921600 }, */
2740 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2741 0x1404, 0x0004, 0, 0,
2742 pbn_b0_4_921600 }, */
2743 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2744 0x1208, 0x0004, 0, 0,
2748 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2750 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2755 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2757 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2762 * RAStel 2 port modem, gerg@moreton.com.au
2764 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2766 pbn_b2_bt_2_115200 },
2769 * EKF addition for i960 Boards form EKF with serial port
2771 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2772 0xE4BF, PCI_ANY_ID, 0, 0,
2776 * Xircom Cardbus/Ethernet combos
2778 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2782 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2784 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2789 * Untested PCI modems, sent in from various folks...
2793 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2795 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2796 0x1048, 0x1500, 0, 0,
2799 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2806 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2807 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2809 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2812 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2816 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2827 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2829 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2830 PCI_ANY_ID, PCI_ANY_ID,
2832 0, pbn_exar_XR17C152 },
2833 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2834 PCI_ANY_ID, PCI_ANY_ID,
2836 0, pbn_exar_XR17C154 },
2837 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2838 PCI_ANY_ID, PCI_ANY_ID,
2840 0, pbn_exar_XR17C158 },
2843 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2845 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2851 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2852 PCI_ANY_ID, PCI_ANY_ID,
2854 pbn_b1_bt_1_115200 },
2859 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2860 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2865 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2866 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
2869 * Perle PCI-RAS cards
2871 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2872 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2873 0, 0, pbn_b2_4_921600 },
2874 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2875 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2876 0, 0, pbn_b2_8_921600 },
2879 * Mainpine series cards: Fairly standard layout but fools
2880 * parts of the autodetect in some cases and uses otherwise
2881 * unmatched communications subclasses in the PCI Express case
2884 { /* RockForceDUO */
2885 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2886 PCI_VENDOR_ID_MAINPINE, 0x0200,
2887 0, 0, pbn_b0_2_115200 },
2888 { /* RockForceQUATRO */
2889 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2890 PCI_VENDOR_ID_MAINPINE, 0x0300,
2891 0, 0, pbn_b0_4_115200 },
2892 { /* RockForceDUO+ */
2893 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2894 PCI_VENDOR_ID_MAINPINE, 0x0400,
2895 0, 0, pbn_b0_2_115200 },
2896 { /* RockForceQUATRO+ */
2897 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2898 PCI_VENDOR_ID_MAINPINE, 0x0500,
2899 0, 0, pbn_b0_4_115200 },
2901 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2902 PCI_VENDOR_ID_MAINPINE, 0x0600,
2903 0, 0, pbn_b0_2_115200 },
2905 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2906 PCI_VENDOR_ID_MAINPINE, 0x0700,
2907 0, 0, pbn_b0_4_115200 },
2908 { /* RockForceOCTO+ */
2909 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2910 PCI_VENDOR_ID_MAINPINE, 0x0800,
2911 0, 0, pbn_b0_8_115200 },
2912 { /* RockForceDUO+ */
2913 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2914 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2915 0, 0, pbn_b0_2_115200 },
2916 { /* RockForceQUARTRO+ */
2917 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2918 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2919 0, 0, pbn_b0_4_115200 },
2920 { /* RockForceOCTO+ */
2921 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2922 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2923 0, 0, pbn_b0_8_115200 },
2925 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2926 PCI_VENDOR_ID_MAINPINE, 0x2000,
2927 0, 0, pbn_b0_1_115200 },
2929 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2930 PCI_VENDOR_ID_MAINPINE, 0x2100,
2931 0, 0, pbn_b0_1_115200 },
2933 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2934 PCI_VENDOR_ID_MAINPINE, 0x2200,
2935 0, 0, pbn_b0_2_115200 },
2937 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2938 PCI_VENDOR_ID_MAINPINE, 0x2300,
2939 0, 0, pbn_b0_2_115200 },
2941 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2942 PCI_VENDOR_ID_MAINPINE, 0x2400,
2943 0, 0, pbn_b0_4_115200 },
2945 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2946 PCI_VENDOR_ID_MAINPINE, 0x2500,
2947 0, 0, pbn_b0_4_115200 },
2949 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2950 PCI_VENDOR_ID_MAINPINE, 0x2600,
2951 0, 0, pbn_b0_8_115200 },
2953 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2954 PCI_VENDOR_ID_MAINPINE, 0x2700,
2955 0, 0, pbn_b0_8_115200 },
2956 { /* IQ Express D1 */
2957 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2958 PCI_VENDOR_ID_MAINPINE, 0x3000,
2959 0, 0, pbn_b0_1_115200 },
2960 { /* IQ Express F1 */
2961 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2962 PCI_VENDOR_ID_MAINPINE, 0x3100,
2963 0, 0, pbn_b0_1_115200 },
2964 { /* IQ Express D2 */
2965 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2966 PCI_VENDOR_ID_MAINPINE, 0x3200,
2967 0, 0, pbn_b0_2_115200 },
2968 { /* IQ Express F2 */
2969 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2970 PCI_VENDOR_ID_MAINPINE, 0x3300,
2971 0, 0, pbn_b0_2_115200 },
2972 { /* IQ Express D4 */
2973 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2974 PCI_VENDOR_ID_MAINPINE, 0x3400,
2975 0, 0, pbn_b0_4_115200 },
2976 { /* IQ Express F4 */
2977 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2978 PCI_VENDOR_ID_MAINPINE, 0x3500,
2979 0, 0, pbn_b0_4_115200 },
2980 { /* IQ Express D8 */
2981 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2982 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2983 0, 0, pbn_b0_8_115200 },
2984 { /* IQ Express F8 */
2985 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2986 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2987 0, 0, pbn_b0_8_115200 },
2991 * PA Semi PA6T-1682M on-chip UART
2993 { PCI_VENDOR_ID_PASEMI, 0xa004,
2994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2998 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3000 { PCI_VENDOR_ID_ADDIDATA,
3001 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3008 { PCI_VENDOR_ID_ADDIDATA,
3009 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3016 { PCI_VENDOR_ID_ADDIDATA,
3017 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3024 { PCI_VENDOR_ID_ADDIDATA_OLD,
3025 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3032 { PCI_VENDOR_ID_ADDIDATA,
3033 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3040 { PCI_VENDOR_ID_ADDIDATA,
3041 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3048 { PCI_VENDOR_ID_ADDIDATA,
3049 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3056 { PCI_VENDOR_ID_ADDIDATA,
3057 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3064 { PCI_VENDOR_ID_ADDIDATA,
3065 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3072 { PCI_VENDOR_ID_ADDIDATA,
3073 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3080 { PCI_VENDOR_ID_ADDIDATA,
3081 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3089 * These entries match devices with class COMMUNICATION_SERIAL,
3090 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3092 { PCI_ANY_ID, PCI_ANY_ID,
3093 PCI_ANY_ID, PCI_ANY_ID,
3094 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3095 0xffff00, pbn_default },
3096 { PCI_ANY_ID, PCI_ANY_ID,
3097 PCI_ANY_ID, PCI_ANY_ID,
3098 PCI_CLASS_COMMUNICATION_MODEM << 8,
3099 0xffff00, pbn_default },
3100 { PCI_ANY_ID, PCI_ANY_ID,
3101 PCI_ANY_ID, PCI_ANY_ID,
3102 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3103 0xffff00, pbn_default },
3107 static struct pci_driver serial_pci_driver = {
3109 .probe = pciserial_init_one,
3110 .remove = __devexit_p(pciserial_remove_one),
3112 .suspend = pciserial_suspend_one,
3113 .resume = pciserial_resume_one,
3115 .id_table = serial_pci_tbl,
3118 static int __init serial8250_pci_init(void)
3120 return pci_register_driver(&serial_pci_driver);
3123 static void __exit serial8250_pci_exit(void)
3125 pci_unregister_driver(&serial_pci_driver);
3128 module_init(serial8250_pci_init);
3129 module_exit(serial8250_pci_exit);
3131 MODULE_LICENSE("GPL");
3132 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3133 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);