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   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/gpio.h>
  16
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/dm644x.h>
  20 #include <mach/clock.h>
  21 #include <mach/cputype.h>
  22 #include <mach/edma.h>
  23 #include <mach/irqs.h>
  24 #include <mach/psc.h>
  25 #include <mach/mux.h>
  26 #include <mach/time.h>
  27 #include <mach/common.h>
  28
  29 #include "clock.h"
  30 #include "mux.h"
  31
  32 /*
  33  * Device specific clocks
  34  */
  35 #define DM644X_REF_FREQ         27000000
  36
  37 static struct pll_data pll1_data = {
  38         .num       = 1,
  39         .phys_base = DAVINCI_PLL1_BASE,
  40 };
  41
  42 static struct pll_data pll2_data = {
  43         .num       = 2,
  44         .phys_base = DAVINCI_PLL2_BASE,
  45 };
  46
  47 static struct clk ref_clk = {
  48         .name = "ref_clk",
  49         .rate = DM644X_REF_FREQ,
  50 };
  51
  52 static struct clk pll1_clk = {
  53         .name = "pll1",
  54         .parent = &ref_clk,
  55         .pll_data = &pll1_data,
  56         .flags = CLK_PLL,
  57 };
  58
  59 static struct clk pll1_sysclk1 = {
  60         .name = "pll1_sysclk1",
  61         .parent = &pll1_clk,
  62         .flags = CLK_PLL,
  63         .div_reg = PLLDIV1,
  64 };
  65
  66 static struct clk pll1_sysclk2 = {
  67         .name = "pll1_sysclk2",
  68         .parent = &pll1_clk,
  69         .flags = CLK_PLL,
  70         .div_reg = PLLDIV2,
  71 };
  72
  73 static struct clk pll1_sysclk3 = {
  74         .name = "pll1_sysclk3",
  75         .parent = &pll1_clk,
  76         .flags = CLK_PLL,
  77         .div_reg = PLLDIV3,
  78 };
  79
  80 static struct clk pll1_sysclk5 = {
  81         .name = "pll1_sysclk5",
  82         .parent = &pll1_clk,
  83         .flags = CLK_PLL,
  84         .div_reg = PLLDIV5,
  85 };
  86
  87 static struct clk pll1_aux_clk = {
  88         .name = "pll1_aux_clk",
  89         .parent = &pll1_clk,
  90         .flags = CLK_PLL | PRE_PLL,
  91 };
  92
  93 static struct clk pll1_sysclkbp = {
  94         .name = "pll1_sysclkbp",
  95         .parent = &pll1_clk,
  96         .flags = CLK_PLL | PRE_PLL,
  97         .div_reg = BPDIV
  98 };
  99
 100 static struct clk pll2_clk = {
 101         .name = "pll2",
 102         .parent = &ref_clk,
 103         .pll_data = &pll2_data,
 104         .flags = CLK_PLL,
 105 };
 106
 107 static struct clk pll2_sysclk1 = {
 108         .name = "pll2_sysclk1",
 109         .parent = &pll2_clk,
 110         .flags = CLK_PLL,
 111         .div_reg = PLLDIV1,
 112 };
 113
 114 static struct clk pll2_sysclk2 = {
 115         .name = "pll2_sysclk2",
 116         .parent = &pll2_clk,
 117         .flags = CLK_PLL,
 118         .div_reg = PLLDIV2,
 119 };
 120
 121 static struct clk pll2_sysclkbp = {
 122         .name = "pll2_sysclkbp",
 123         .parent = &pll2_clk,
 124         .flags = CLK_PLL | PRE_PLL,
 125         .div_reg = BPDIV
 126 };
 127
 128 static struct clk dsp_clk = {
 129         .name = "dsp",
 130         .parent = &pll1_sysclk1,
 131         .lpsc = DAVINCI_LPSC_GEM,
 132         .flags = PSC_DSP,
 133         .usecount = 1,                  /* REVISIT how to disable? */
 134 };
 135
 136 static struct clk arm_clk = {
 137         .name = "arm",
 138         .parent = &pll1_sysclk2,
 139         .lpsc = DAVINCI_LPSC_ARM,
 140         .flags = ALWAYS_ENABLED,
 141 };
 142
 143 static struct clk vicp_clk = {
 144         .name = "vicp",
 145         .parent = &pll1_sysclk2,
 146         .lpsc = DAVINCI_LPSC_IMCOP,
 147         .flags = PSC_DSP,
 148         .usecount = 1,                  /* REVISIT how to disable? */
 149 };
 150
 151 static struct clk vpss_master_clk = {
 152         .name = "vpss_master",
 153         .parent = &pll1_sysclk3,
 154         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 155         .flags = CLK_PSC,
 156 };
 157
 158 static struct clk vpss_slave_clk = {
 159         .name = "vpss_slave",
 160         .parent = &pll1_sysclk3,
 161         .lpsc = DAVINCI_LPSC_VPSSSLV,
 162 };
 163
 164 static struct clk uart0_clk = {
 165         .name = "uart0",
 166         .parent = &pll1_aux_clk,
 167         .lpsc = DAVINCI_LPSC_UART0,
 168 };
 169
 170 static struct clk uart1_clk = {
 171         .name = "uart1",
 172         .parent = &pll1_aux_clk,
 173         .lpsc = DAVINCI_LPSC_UART1,
 174 };
 175
 176 static struct clk uart2_clk = {
 177         .name = "uart2",
 178         .parent = &pll1_aux_clk,
 179         .lpsc = DAVINCI_LPSC_UART2,
 180 };
 181
 182 static struct clk emac_clk = {
 183         .name = "emac",
 184         .parent = &pll1_sysclk5,
 185         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
 186 };
 187
 188 static struct clk i2c_clk = {
 189         .name = "i2c",
 190         .parent = &pll1_aux_clk,
 191         .lpsc = DAVINCI_LPSC_I2C,
 192 };
 193
 194 static struct clk ide_clk = {
 195         .name = "ide",
 196         .parent = &pll1_sysclk5,
 197         .lpsc = DAVINCI_LPSC_ATA,
 198 };
 199
 200 static struct clk asp_clk = {
 201         .name = "asp0",
 202         .parent = &pll1_sysclk5,
 203         .lpsc = DAVINCI_LPSC_McBSP,
 204 };
 205
 206 static struct clk mmcsd_clk = {
 207         .name = "mmcsd",
 208         .parent = &pll1_sysclk5,
 209         .lpsc = DAVINCI_LPSC_MMC_SD,
 210 };
 211
 212 static struct clk spi_clk = {
 213         .name = "spi",
 214         .parent = &pll1_sysclk5,
 215         .lpsc = DAVINCI_LPSC_SPI,
 216 };
 217
 218 static struct clk gpio_clk = {
 219         .name = "gpio",
 220         .parent = &pll1_sysclk5,
 221         .lpsc = DAVINCI_LPSC_GPIO,
 222 };
 223
 224 static struct clk usb_clk = {
 225         .name = "usb",
 226         .parent = &pll1_sysclk5,
 227         .lpsc = DAVINCI_LPSC_USB,
 228 };
 229
 230 static struct clk vlynq_clk = {
 231         .name = "vlynq",
 232         .parent = &pll1_sysclk5,
 233         .lpsc = DAVINCI_LPSC_VLYNQ,
 234 };
 235
 236 static struct clk aemif_clk = {
 237         .name = "aemif",
 238         .parent = &pll1_sysclk5,
 239         .lpsc = DAVINCI_LPSC_AEMIF,
 240 };
 241
 242 static struct clk pwm0_clk = {
 243         .name = "pwm0",
 244         .parent = &pll1_aux_clk,
 245         .lpsc = DAVINCI_LPSC_PWM0,
 246 };
 247
 248 static struct clk pwm1_clk = {
 249         .name = "pwm1",
 250         .parent = &pll1_aux_clk,
 251         .lpsc = DAVINCI_LPSC_PWM1,
 252 };
 253
 254 static struct clk pwm2_clk = {
 255         .name = "pwm2",
 256         .parent = &pll1_aux_clk,
 257         .lpsc = DAVINCI_LPSC_PWM2,
 258 };
 259
 260 static struct clk timer0_clk = {
 261         .name = "timer0",
 262         .parent = &pll1_aux_clk,
 263         .lpsc = DAVINCI_LPSC_TIMER0,
 264 };
 265
 266 static struct clk timer1_clk = {
 267         .name = "timer1",
 268         .parent = &pll1_aux_clk,
 269         .lpsc = DAVINCI_LPSC_TIMER1,
 270 };
 271
 272 static struct clk timer2_clk = {
 273         .name = "timer2",
 274         .parent = &pll1_aux_clk,
 275         .lpsc = DAVINCI_LPSC_TIMER2,
 276         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 277 };
 278
 279 struct davinci_clk dm644x_clks[] = {
 280         CLK(NULL, "ref", &ref_clk),
 281         CLK(NULL, "pll1", &pll1_clk),
 282         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 283         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 284         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 285         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 286         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 287         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 288         CLK(NULL, "pll2", &pll2_clk),
 289         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 290         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 291         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 292         CLK(NULL, "dsp", &dsp_clk),
 293         CLK(NULL, "arm", &arm_clk),
 294         CLK(NULL, "vicp", &vicp_clk),
 295         CLK(NULL, "vpss_master", &vpss_master_clk),
 296         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 297         CLK(NULL, "arm", &arm_clk),
 298         CLK(NULL, "uart0", &uart0_clk),
 299         CLK(NULL, "uart1", &uart1_clk),
 300         CLK(NULL, "uart2", &uart2_clk),
 301         CLK("davinci_emac.1", NULL, &emac_clk),
 302         CLK("i2c_davinci.1", NULL, &i2c_clk),
 303         CLK("palm_bk3710", NULL, &ide_clk),
 304         CLK("soc-audio.0", NULL, &asp_clk),
 305         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
 306         CLK(NULL, "spi", &spi_clk),
 307         CLK(NULL, "gpio", &gpio_clk),
 308         CLK(NULL, "usb", &usb_clk),
 309         CLK(NULL, "vlynq", &vlynq_clk),
 310         CLK(NULL, "aemif", &aemif_clk),
 311         CLK(NULL, "pwm0", &pwm0_clk),
 312         CLK(NULL, "pwm1", &pwm1_clk),
 313         CLK(NULL, "pwm2", &pwm2_clk),
 314         CLK(NULL, "timer0", &timer0_clk),
 315         CLK(NULL, "timer1", &timer1_clk),
 316         CLK("watchdog", NULL, &timer2_clk),
 317         CLK(NULL, NULL, NULL),
 318 };
 319
 320 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 321
 322 static struct resource dm644x_emac_resources[] = {
 323         {
 324                 .start  = DM644X_EMAC_BASE,
 325                 .end    = DM644X_EMAC_BASE + 0x47ff,
 326                 .flags  = IORESOURCE_MEM,
 327         },
 328         {
 329                 .start = IRQ_EMACINT,
 330                 .end   = IRQ_EMACINT,
 331                 .flags = IORESOURCE_IRQ,
 332         },
 333 };
 334
 335 static struct platform_device dm644x_emac_device = {
 336        .name            = "davinci_emac",
 337        .id              = 1,
 338        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
 339        .resource        = dm644x_emac_resources,
 340 };
 341
 342 #endif
 343
 344 /*
 345  * Device specific mux setup
 346  *
 347  *      soc     description     mux  mode   mode  mux    dbg
 348  *                              reg  offset mask  mode
 349  */
 350 static const struct mux_config dm644x_pins[] = {
 351 #ifdef CONFIG_DAVINCI_MUX
 352 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 353 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 354 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
 355
 356 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
 357
 358 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
 359
 360 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
 361
 362 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
 363
 364 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
 365
 366 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
 367 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
 368
 369 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
 370
 371 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
 372
 373 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
 374
 375 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
 376 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
 377 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
 378
 379 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
 380
 381 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
 382
 383 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
 384 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
 385 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
 386 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
 387
 388 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
 389
 390 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 391 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
 392 #endif
 393 };
 394
 395 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 396 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 397         [IRQ_VDINT0]            = 2,
 398         [IRQ_VDINT1]            = 6,
 399         [IRQ_VDINT2]            = 6,
 400         [IRQ_HISTINT]           = 6,
 401         [IRQ_H3AINT]            = 6,
 402         [IRQ_PRVUINT]           = 6,
 403         [IRQ_RSZINT]            = 6,
 404         [7]                     = 7,
 405         [IRQ_VENCINT]           = 6,
 406         [IRQ_ASQINT]            = 6,
 407         [IRQ_IMXINT]            = 6,
 408         [IRQ_VLCDINT]           = 6,
 409         [IRQ_USBINT]            = 4,
 410         [IRQ_EMACINT]           = 4,
 411         [14]                    = 7,
 412         [15]                    = 7,
 413         [IRQ_CCINT0]            = 5,    /* dma */
 414         [IRQ_CCERRINT]          = 5,    /* dma */
 415         [IRQ_TCERRINT0]         = 5,    /* dma */
 416         [IRQ_TCERRINT]          = 5,    /* dma */
 417         [IRQ_PSCIN]             = 7,
 418         [21]                    = 7,
 419         [IRQ_IDE]               = 4,
 420         [23]                    = 7,
 421         [IRQ_MBXINT]            = 7,
 422         [IRQ_MBRINT]            = 7,
 423         [IRQ_MMCINT]            = 7,
 424         [IRQ_SDIOINT]           = 7,
 425         [28]                    = 7,
 426         [IRQ_DDRINT]            = 7,
 427         [IRQ_AEMIFINT]          = 7,
 428         [IRQ_VLQINT]            = 4,
 429         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 430         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 431         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 432         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 433         [IRQ_PWMINT0]           = 7,
 434         [IRQ_PWMINT1]           = 7,
 435         [IRQ_PWMINT2]           = 7,
 436         [IRQ_I2C]               = 3,
 437         [IRQ_UARTINT0]          = 3,
 438         [IRQ_UARTINT1]          = 3,
 439         [IRQ_UARTINT2]          = 3,
 440         [IRQ_SPINT0]            = 3,
 441         [IRQ_SPINT1]            = 3,
 442         [45]                    = 7,
 443         [IRQ_DSP2ARM0]          = 4,
 444         [IRQ_DSP2ARM1]          = 4,
 445         [IRQ_GPIO0]             = 7,
 446         [IRQ_GPIO1]             = 7,
 447         [IRQ_GPIO2]             = 7,
 448         [IRQ_GPIO3]             = 7,
 449         [IRQ_GPIO4]             = 7,
 450         [IRQ_GPIO5]             = 7,
 451         [IRQ_GPIO6]             = 7,
 452         [IRQ_GPIO7]             = 7,
 453         [IRQ_GPIOBNK0]          = 7,
 454         [IRQ_GPIOBNK1]          = 7,
 455         [IRQ_GPIOBNK2]          = 7,
 456         [IRQ_GPIOBNK3]          = 7,
 457         [IRQ_GPIOBNK4]          = 7,
 458         [IRQ_COMMTX]            = 7,
 459         [IRQ_COMMRX]            = 7,
 460         [IRQ_EMUINT]            = 7,
 461 };
 462
 463 /*----------------------------------------------------------------------*/
 464
 465 static const s8 dma_chan_dm644x_no_event[] = {
 466          0,  1, 12, 13, 14,
 467         15, 25, 30, 31, 45,
 468         46, 47, 55, 56, 57,
 469         58, 59, 60, 61, 62,
 470         63,
 471         -1
 472 };
 473
 474 static struct edma_soc_info dm644x_edma_info = {
 475         .n_channel      = 64,
 476         .n_region       = 4,
 477         .n_slot         = 128,
 478         .n_tc           = 2,
 479         .noevent        = dma_chan_dm644x_no_event,
 480 };
 481
 482 static struct resource edma_resources[] = {
 483         {
 484                 .name   = "edma_cc",
 485                 .start  = 0x01c00000,
 486                 .end    = 0x01c00000 + SZ_64K - 1,
 487                 .flags  = IORESOURCE_MEM,
 488         },
 489         {
 490                 .name   = "edma_tc0",
 491                 .start  = 0x01c10000,
 492                 .end    = 0x01c10000 + SZ_1K - 1,
 493                 .flags  = IORESOURCE_MEM,
 494         },
 495         {
 496                 .name   = "edma_tc1",
 497                 .start  = 0x01c10400,
 498                 .end    = 0x01c10400 + SZ_1K - 1,
 499                 .flags  = IORESOURCE_MEM,
 500         },
 501         {
 502                 .start  = IRQ_CCINT0,
 503                 .flags  = IORESOURCE_IRQ,
 504         },
 505         {
 506                 .start  = IRQ_CCERRINT,
 507                 .flags  = IORESOURCE_IRQ,
 508         },
 509         /* not using TC*_ERR */
 510 };
 511
 512 static struct platform_device dm644x_edma_device = {
 513         .name                   = "edma",
 514         .id                     = -1,
 515         .dev.platform_data      = &dm644x_edma_info,
 516         .num_resources          = ARRAY_SIZE(edma_resources),
 517         .resource               = edma_resources,
 518 };
 519
 520 /*----------------------------------------------------------------------*/
 521 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
 522
 523 void dm644x_init_emac(struct emac_platform_data *pdata)
 524 {
 525         pdata->ctrl_reg_offset          = DM644X_EMAC_CNTRL_OFFSET;
 526         pdata->ctrl_mod_reg_offset      = DM644X_EMAC_CNTRL_MOD_OFFSET;
 527         pdata->ctrl_ram_offset          = DM644X_EMAC_CNTRL_RAM_OFFSET;
 528         pdata->mdio_reg_offset          = DM644X_EMAC_MDIO_OFFSET;
 529         pdata->ctrl_ram_size            = DM644X_EMAC_CNTRL_RAM_SIZE;
 530         pdata->version                  = EMAC_VERSION_1;
 531         dm644x_emac_device.dev.platform_data = pdata;
 532         platform_device_register(&dm644x_emac_device);
 533 }
 534 #else
 535
 536 void dm644x_init_emac(struct emac_platform_data *unused) {}
 537
 538 #endif
 539
 540 static struct map_desc dm644x_io_desc[] = {
 541         {
 542                 .virtual        = IO_VIRT,
 543                 .pfn            = __phys_to_pfn(IO_PHYS),
 544                 .length         = IO_SIZE,
 545                 .type           = MT_DEVICE
 546         },
 547 };
 548
 549 /* Contents of JTAG ID register used to identify exact cpu type */
 550 static struct davinci_id dm644x_ids[] = {
 551         {
 552                 .variant        = 0x0,
 553                 .part_no        = 0xb700,
 554                 .manufacturer   = 0x017,
 555                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 556                 .name           = "dm6446",
 557         },
 558 };
 559
 560 static void __iomem *dm644x_psc_bases[] = {
 561         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 562 };
 563
 564 /*
 565  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 566  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 567  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 568  * T1_TOP: Timer 1, top   :  <unused>
 569  */
 570 struct davinci_timer_info dm644x_timer_info = {
 571         .timers         = davinci_timer_instance,
 572         .clockevent_id  = T0_BOT,
 573         .clocksource_id = T0_TOP,
 574 };
 575
 576 static struct davinci_soc_info davinci_soc_info_dm644x = {
 577         .io_desc                = dm644x_io_desc,
 578         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
 579         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 580         .ids                    = dm644x_ids,
 581         .ids_num                = ARRAY_SIZE(dm644x_ids),
 582         .cpu_clks               = dm644x_clks,
 583         .psc_bases              = dm644x_psc_bases,
 584         .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
 585         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 586         .pinmux_pins            = dm644x_pins,
 587         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
 588         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 589         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 590         .intc_irq_prios         = dm644x_default_priorities,
 591         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 592         .timer_info             = &dm644x_timer_info,
 593         .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
 594         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 595         .gpio_num               = 71,
 596         .gpio_irq               = IRQ_GPIOBNK0,
 597 };
 598
 599 void __init dm644x_init(void)
 600 {
 601         davinci_common_init(&davinci_soc_info_dm644x);
 602 }
 603
 604 static int __init dm644x_init_devices(void)
 605 {
 606         if (!cpu_is_davinci_dm644x())
 607                 return 0;
 608
 609         platform_device_register(&dm644x_edma_device);
 610         return 0;
 611 }
 612 postcore_initcall(dm644x_init_devices);