git.oblomov.eu Git - linux-2.6/blob - sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/initval.h>
  31 #include <sound/soc.h>
  32
  33 #include <mach/control.h>
  34 #include <mach/dma.h>
  35 #include <mach/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  40
  41 struct omap_mcbsp_data {
  42         unsigned int                    bus_id;
  43         struct omap_mcbsp_reg_cfg       regs;
  44         unsigned int                    fmt;
  45         /*
  46          * Flags indicating is the bus already activated and configured by
  47          * another substream
  48          */
  49         int                             active;
  50         int                             configured;
  51 };
  52
  53 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  54
  55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  56
  57 /*
  58  * Stream DMA parameters. DMA request line and port address are set runtime
  59  * since they are different between OMAP1 and later OMAPs
  60  */
  61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  62
  63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  64 static const int omap1_dma_reqs[][2] = {
  65         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  66         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  67         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  68 };
  69 static const unsigned long omap1_mcbsp_port[][2] = {
  70         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  71           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  72         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  73           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  74         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  75           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  76 };
  77 #else
  78 static const int omap1_dma_reqs[][2] = {};
  79 static const unsigned long omap1_mcbsp_port[][2] = {};
  80 #endif
  81
  82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  83 static const int omap24xx_dma_reqs[][2] = {
  84         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  85         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  87         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  88         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  89         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  90 #endif
  91 };
  92 #else
  93 static const int omap24xx_dma_reqs[][2] = {};
  94 #endif
  95
  96 #if defined(CONFIG_ARCH_OMAP2420)
  97 static const unsigned long omap2420_mcbsp_port[][2] = {
  98         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  99           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 100         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 101           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 102 };
 103 #else
 104 static const unsigned long omap2420_mcbsp_port[][2] = {};
 105 #endif
 106
 107 #if defined(CONFIG_ARCH_OMAP2430)
 108 static const unsigned long omap2430_mcbsp_port[][2] = {
 109         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 110           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 111         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 112           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 113         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 114           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 115         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 116           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 117         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 118           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 119 };
 120 #else
 121 static const unsigned long omap2430_mcbsp_port[][2] = {};
 122 #endif
 123
 124 #if defined(CONFIG_ARCH_OMAP34XX)
 125 static const unsigned long omap34xx_mcbsp_port[][2] = {
 126         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 127           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 128         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 129           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 130         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 131           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 132         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 133           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 134         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 135           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 136 };
 137 #else
 138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 139 #endif
 140
 141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 142                                   struct snd_soc_dai *dai)
 143 {
 144         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 145         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 146         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 147         int err = 0;
 148
 149         if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
 150                 /*
 151                  * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
 152                  * Set constraint for minimum buffer size to the same than FIFO
 153                  * size in order to avoid underruns in playback startup because
 154                  * HW is keeping the DMA request active until FIFO is filled.
 155                  */
 156                 snd_pcm_hw_constraint_minmax(substream->runtime,
 157                         SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
 158         }
 159
 160         if (!cpu_dai->active)
 161                 err = omap_mcbsp_request(mcbsp_data->bus_id);
 162
 163         return err;
 164 }
 165
 166 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 167                                     struct snd_soc_dai *dai)
 168 {
 169         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 170         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 171         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 172
 173         if (!cpu_dai->active) {
 174                 omap_mcbsp_free(mcbsp_data->bus_id);
 175                 mcbsp_data->configured = 0;
 176         }
 177 }
 178
 179 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 180                                   struct snd_soc_dai *dai)
 181 {
 182         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 183         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 184         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 185         int err = 0;
 186
 187         switch (cmd) {
 188         case SNDRV_PCM_TRIGGER_START:
 189         case SNDRV_PCM_TRIGGER_RESUME:
 190         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 191                 if (!mcbsp_data->active++)
 192                         omap_mcbsp_start(mcbsp_data->bus_id);
 193                 break;
 194
 195         case SNDRV_PCM_TRIGGER_STOP:
 196         case SNDRV_PCM_TRIGGER_SUSPEND:
 197         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 198                 if (!--mcbsp_data->active)
 199                         omap_mcbsp_stop(mcbsp_data->bus_id);
 200                 break;
 201         default:
 202                 err = -EINVAL;
 203         }
 204
 205         return err;
 206 }
 207
 208 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 209                                     struct snd_pcm_hw_params *params,
 210                                     struct snd_soc_dai *dai)
 211 {
 212         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 213         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 214         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 215         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 216         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 217         int wlen, channels, wpf;
 218         unsigned long port;
 219         unsigned int format;
 220
 221         if (cpu_class_is_omap1()) {
 222                 dma = omap1_dma_reqs[bus_id][substream->stream];
 223                 port = omap1_mcbsp_port[bus_id][substream->stream];
 224         } else if (cpu_is_omap2420()) {
 225                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 226                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 227         } else if (cpu_is_omap2430()) {
 228                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 229                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 230         } else if (cpu_is_omap343x()) {
 231                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 232                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 233         } else {
 234                 return -ENODEV;
 235         }
 236         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 237                 substream->stream ? "Audio Capture" : "Audio Playback";
 238         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 239         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 240         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 241
 242         if (mcbsp_data->configured) {
 243                 /* McBSP already configured by another stream */
 244                 return 0;
 245         }
 246
 247         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 248         wpf = channels = params_channels(params);
 249         switch (channels) {
 250         case 2:
 251                 if (format == SND_SOC_DAIFMT_I2S) {
 252                         /* Use dual-phase frames */
 253                         regs->rcr2      |= RPHASE;
 254                         regs->xcr2      |= XPHASE;
 255                         /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 256                         wpf--;
 257                         regs->rcr2      |= RFRLEN2(wpf - 1);
 258                         regs->xcr2      |= XFRLEN2(wpf - 1);
 259                 }
 260         case 1:
 261                 /* Set word per (McBSP) frame for phase1 */
 262                 regs->rcr1      |= RFRLEN1(wpf - 1);
 263                 regs->xcr1      |= XFRLEN1(wpf - 1);
 264                 break;
 265         default:
 266                 /* Unsupported number of channels */
 267                 return -EINVAL;
 268         }
 269
 270         switch (params_format(params)) {
 271         case SNDRV_PCM_FORMAT_S16_LE:
 272                 /* Set word lengths */
 273                 wlen = 16;
 274                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 275                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 276                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 277                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 278                 break;
 279         default:
 280                 /* Unsupported PCM format */
 281                 return -EINVAL;
 282         }
 283
 284         /* Set FS period and length in terms of bit clock periods */
 285         switch (format) {
 286         case SND_SOC_DAIFMT_I2S:
 287                 regs->srgr2     |= FPER(wlen * channels - 1);
 288                 regs->srgr1     |= FWID(wlen - 1);
 289                 break;
 290         case SND_SOC_DAIFMT_DSP_B:
 291                 regs->srgr2     |= FPER(wlen * channels - 1);
 292                 regs->srgr1     |= FWID(wlen * channels - 2);
 293                 break;
 294         }
 295
 296         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 297         mcbsp_data->configured = 1;
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 304  * cache is initialized here
 305  */
 306 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 307                                       unsigned int fmt)
 308 {
 309         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 310         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 311
 312         if (mcbsp_data->configured)
 313                 return 0;
 314
 315         mcbsp_data->fmt = fmt;
 316         memset(regs, 0, sizeof(*regs));
 317         /* Generic McBSP register settings */
 318         regs->spcr2     |= XINTM(3) | FREE;
 319         regs->spcr1     |= RINTM(3);
 320         regs->rcr2      |= RFIG;
 321         regs->xcr2      |= XFIG;
 322         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 323                 regs->xccr = DXENDLY(1) | XDMAEN;
 324                 regs->rccr = RFULL_CYCLE | RDMAEN;
 325         }
 326
 327         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 328         case SND_SOC_DAIFMT_I2S:
 329                 /* 1-bit data delay */
 330                 regs->rcr2      |= RDATDLY(1);
 331                 regs->xcr2      |= XDATDLY(1);
 332                 break;
 333         case SND_SOC_DAIFMT_DSP_B:
 334                 /* 0-bit data delay */
 335                 regs->rcr2      |= RDATDLY(0);
 336                 regs->xcr2      |= XDATDLY(0);
 337                 break;
 338         default:
 339                 /* Unsupported data format */
 340                 return -EINVAL;
 341         }
 342
 343         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 344         case SND_SOC_DAIFMT_CBS_CFS:
 345                 /* McBSP master. Set FS and bit clocks as outputs */
 346                 regs->pcr0      |= FSXM | FSRM |
 347                                    CLKXM | CLKRM;
 348                 /* Sample rate generator drives the FS */
 349                 regs->srgr2     |= FSGM;
 350                 break;
 351         case SND_SOC_DAIFMT_CBM_CFM:
 352                 /* McBSP slave */
 353                 break;
 354         default:
 355                 /* Unsupported master/slave configuration */
 356                 return -EINVAL;
 357         }
 358
 359         /* Set bit clock (CLKX/CLKR) and FS polarities */
 360         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 361         case SND_SOC_DAIFMT_NB_NF:
 362                 /*
 363                  * Normal BCLK + FS.
 364                  * FS active low. TX data driven on falling edge of bit clock
 365                  * and RX data sampled on rising edge of bit clock.
 366                  */
 367                 regs->pcr0      |= FSXP | FSRP |
 368                                    CLKXP | CLKRP;
 369                 break;
 370         case SND_SOC_DAIFMT_NB_IF:
 371                 regs->pcr0      |= CLKXP | CLKRP;
 372                 break;
 373         case SND_SOC_DAIFMT_IB_NF:
 374                 regs->pcr0      |= FSXP | FSRP;
 375                 break;
 376         case SND_SOC_DAIFMT_IB_IF:
 377                 break;
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 386                                      int div_id, int div)
 387 {
 388         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 389         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 390
 391         if (div_id != OMAP_MCBSP_CLKGDV)
 392                 return -ENODEV;
 393
 394         regs->srgr1     |= CLKGDV(div - 1);
 395
 396         return 0;
 397 }
 398
 399 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 400                                        int clk_id)
 401 {
 402         int sel_bit;
 403         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 404
 405         if (cpu_class_is_omap1()) {
 406                 /* OMAP1's can use only external source clock */
 407                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 408                         return -EINVAL;
 409                 else
 410                         return 0;
 411         }
 412
 413         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 414                 return -EINVAL;
 415
 416         if (cpu_is_omap343x())
 417                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 418
 419         switch (mcbsp_data->bus_id) {
 420         case 0:
 421                 reg = OMAP2_CONTROL_DEVCONF0;
 422                 sel_bit = 2;
 423                 break;
 424         case 1:
 425                 reg = OMAP2_CONTROL_DEVCONF0;
 426                 sel_bit = 6;
 427                 break;
 428         case 2:
 429                 reg = reg_devconf1;
 430                 sel_bit = 0;
 431                 break;
 432         case 3:
 433                 reg = reg_devconf1;
 434                 sel_bit = 2;
 435                 break;
 436         case 4:
 437                 reg = reg_devconf1;
 438                 sel_bit = 4;
 439                 break;
 440         default:
 441                 return -EINVAL;
 442         }
 443
 444         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 445                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 446         else
 447                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 448
 449         return 0;
 450 }
 451
 452 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 453                                          int clk_id, unsigned int freq,
 454                                          int dir)
 455 {
 456         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 457         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 458         int err = 0;
 459
 460         switch (clk_id) {
 461         case OMAP_MCBSP_SYSCLK_CLK:
 462                 regs->srgr2     |= CLKSM;
 463                 break;
 464         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 465         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 466                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 467                 break;
 468
 469         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 470                 regs->srgr2     |= CLKSM;
 471         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 472                 regs->pcr0      |= SCLKME;
 473                 break;
 474         default:
 475                 err = -ENODEV;
 476         }
 477
 478         return err;
 479 }
 480
 481 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 482         .startup        = omap_mcbsp_dai_startup,
 483         .shutdown       = omap_mcbsp_dai_shutdown,
 484         .trigger        = omap_mcbsp_dai_trigger,
 485         .hw_params      = omap_mcbsp_dai_hw_params,
 486         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 487         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 488         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 489 };
 490
 491 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 492 {                                                               \
 493         .name = "omap-mcbsp-dai-"#link_id,                      \
 494         .id = (link_id),                                        \
 495         .playback = {                                           \
 496                 .channels_min = 1,                              \
 497                 .channels_max = 2,                              \
 498                 .rates = OMAP_MCBSP_RATES,                      \
 499                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 500         },                                                      \
 501         .capture = {                                            \
 502                 .channels_min = 1,                              \
 503                 .channels_max = 2,                              \
 504                 .rates = OMAP_MCBSP_RATES,                      \
 505                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 506         },                                                      \
 507         .ops = &omap_mcbsp_dai_ops,                             \
 508         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 509 }
 510
 511 struct snd_soc_dai omap_mcbsp_dai[] = {
 512         OMAP_MCBSP_DAI_BUILDER(0),
 513         OMAP_MCBSP_DAI_BUILDER(1),
 514 #if NUM_LINKS >= 3
 515         OMAP_MCBSP_DAI_BUILDER(2),
 516 #endif
 517 #if NUM_LINKS == 5
 518         OMAP_MCBSP_DAI_BUILDER(3),
 519         OMAP_MCBSP_DAI_BUILDER(4),
 520 #endif
 521 };
 522
 523 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 524
 525 static int __init snd_omap_mcbsp_init(void)
 526 {
 527         return snd_soc_register_dais(omap_mcbsp_dai,
 528                                      ARRAY_SIZE(omap_mcbsp_dai));
 529 }
 530 module_init(snd_omap_mcbsp_init);
 531
 532 static void __exit snd_omap_mcbsp_exit(void)
 533 {
 534         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 535 }
 536 module_exit(snd_omap_mcbsp_exit);
 537
 538 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
 539 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 540 MODULE_LICENSE("GPL");