1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
30 #include <linux/if_ether.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/fc/fc_fs.h>
34 #include <scsi/fc/fc_fcoe.h>
35 #include <scsi/libfc.h>
36 #include <scsi/libfcoe.h>
39 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
40 * @rx_desc: advanced rx descriptor
42 * Returns : true if it is FCoE pkt
44 static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
48 p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info);
49 if (p & IXGBE_RXDADV_PKTTYPE_ETQF) {
50 p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK;
51 p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT;
52 return p == IXGBE_ETQF_FILTER_FCOE;
58 * ixgbe_fcoe_clear_ddp - clear the given ddp context
59 * @ddp - ptr to the ixgbe_fcoe_ddp
64 static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
75 * ixgbe_fcoe_ddp_put - free the ddp context for a given xid
76 * @netdev: the corresponding net_device
77 * @xid: the xid that corresponding ddp will be freed
79 * This is the implementation of net_device_ops.ndo_fcoe_ddp_done
80 * and it is expected to be called by ULD, i.e., FCP layer of libfc
81 * to release the corresponding ddp context when the I/O is done.
83 * Returns : data length already ddp-ed in bytes
85 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
88 struct ixgbe_fcoe *fcoe;
89 struct ixgbe_adapter *adapter;
90 struct ixgbe_fcoe_ddp *ddp;
95 if (xid >= IXGBE_FCOE_DDP_MAX)
98 adapter = netdev_priv(netdev);
99 fcoe = &adapter->fcoe;
100 ddp = &fcoe->ddp[xid];
105 /* if there an error, force to invalidate ddp context */
107 spin_lock_bh(&fcoe->lock);
108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0);
109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW,
110 (xid | IXGBE_FCFLTRW_WE));
111 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
112 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
113 (xid | IXGBE_FCDMARW_WE));
114 spin_unlock_bh(&fcoe->lock);
117 pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
119 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
120 ixgbe_fcoe_clear_ddp(ddp);
127 * ixgbe_fcoe_ddp_get - called to set up ddp context
128 * @netdev: the corresponding net_device
129 * @xid: the exchange id requesting ddp
130 * @sgl: the scatter-gather list for this request
131 * @sgc: the number of scatter-gather items
133 * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup
134 * and is expected to be called from ULD, e.g., FCP layer of libfc
135 * to set up ddp for the corresponding xid of the given sglist for
136 * the corresponding I/O.
138 * Returns : 1 for success and 0 for no ddp
140 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
141 struct scatterlist *sgl, unsigned int sgc)
143 struct ixgbe_adapter *adapter;
145 struct ixgbe_fcoe *fcoe;
146 struct ixgbe_fcoe_ddp *ddp;
147 struct scatterlist *sg;
148 unsigned int i, j, dmacount;
150 static const unsigned int bufflen = 4096;
151 unsigned int firstoff = 0;
152 unsigned int lastsize;
153 unsigned int thisoff = 0;
154 unsigned int thislen = 0;
155 u32 fcbuff, fcdmarw, fcfltrw;
161 adapter = netdev_priv(netdev);
162 if (xid >= IXGBE_FCOE_DDP_MAX) {
163 DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid);
167 fcoe = &adapter->fcoe;
169 DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid);
173 ddp = &fcoe->ddp[xid];
175 DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
176 xid, ddp->sgl, ddp->sgc);
179 ixgbe_fcoe_clear_ddp(ddp);
181 /* setup dma from scsi command sgl */
182 dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
184 DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid);
188 /* alloc the udl from our ddp pool */
189 ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp);
191 DPRINTK(DRV, ERR, "failed allocated ddp context\n");
192 goto out_noddp_unmap;
198 for_each_sg(sgl, sg, dmacount, i) {
199 addr = sg_dma_address(sg);
200 len = sg_dma_len(sg);
202 /* get the offset of length of current buffer */
203 thisoff = addr & ((dma_addr_t)bufflen - 1);
204 thislen = min((bufflen - thisoff), len);
206 * all but the 1st buffer (j == 0)
207 * must be aligned on bufflen
209 if ((j != 0) && (thisoff))
212 * all but the last buffer
213 * ((i == (dmacount - 1)) && (thislen == len))
214 * must end at bufflen
216 if (((i != (dmacount - 1)) || (thislen != len))
217 && ((thislen + thisoff) != bufflen))
220 ddp->udl[j] = (u64)(addr - thisoff);
221 /* only the first buffer may have none-zero offset */
227 /* max number of buffers allowed in one DDP context */
228 if (j > IXGBE_BUFFCNT_MAX) {
229 DPRINTK(DRV, ERR, "xid=%x:%d,%d,%d:addr=%llx "
230 "not enough descriptors\n",
231 xid, i, j, dmacount, (u64)addr);
236 /* only the last buffer may have non-full bufflen */
237 lastsize = thisoff + thislen;
239 fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
240 fcbuff |= (j << IXGBE_FCBUFF_BUFFCNT_SHIFT);
241 fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
242 fcbuff |= (IXGBE_FCBUFF_VALID);
245 fcdmarw |= IXGBE_FCDMARW_WE;
246 fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);
249 fcfltrw |= IXGBE_FCFLTRW_WE;
251 /* program DMA context */
253 spin_lock_bh(&fcoe->lock);
254 IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_32BIT_MASK);
255 IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
256 IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
257 IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
258 /* program filter context */
259 IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
260 IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
261 IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
262 spin_unlock_bh(&fcoe->lock);
267 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
268 ixgbe_fcoe_clear_ddp(ddp);
271 pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
276 * ixgbe_fcoe_ddp - check ddp status and mark it done
277 * @adapter: ixgbe adapter
278 * @rx_desc: advanced rx descriptor
279 * @skb: the skb holding the received data
281 * This checks ddp status.
283 * Returns : 0 for success and skb will not be delivered to ULD
285 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
286 union ixgbe_adv_rx_desc *rx_desc,
290 u32 sterr, fceofe, fcerr, fcstat;
292 struct ixgbe_fcoe *fcoe;
293 struct ixgbe_fcoe_ddp *ddp;
294 struct fc_frame_header *fh;
296 if (!ixgbe_rx_is_fcoe(rx_desc))
299 skb->ip_summed = CHECKSUM_UNNECESSARY;
300 sterr = le32_to_cpu(rx_desc->wb.upper.status_error);
301 fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR);
302 fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE);
303 if (fcerr == IXGBE_FCERR_BADCRC)
304 skb->ip_summed = CHECKSUM_NONE;
306 skb_reset_network_header(skb);
307 skb_set_transport_header(skb, skb_network_offset(skb) +
308 sizeof(struct fcoe_hdr));
309 fh = (struct fc_frame_header *)skb_transport_header(skb);
310 xid = be16_to_cpu(fh->fh_ox_id);
311 if (xid >= IXGBE_FCOE_DDP_MAX)
314 fcoe = &adapter->fcoe;
315 ddp = &fcoe->ddp[xid];
319 ddp->err = (fcerr | fceofe);
323 fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT);
325 /* update length of DDPed data */
326 ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
327 /* unmap the sg list when FCP_RSP is received */
328 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) {
329 pci_unmap_sg(adapter->pdev, ddp->sgl,
330 ddp->sgc, DMA_FROM_DEVICE);
334 /* return 0 to bypass going to ULD for DDPed data */
335 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
344 * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO)
345 * @adapter: ixgbe adapter
346 * @tx_ring: tx desc ring
347 * @skb: associated skb
348 * @tx_flags: tx flags
349 * @hdr_len: hdr_len to be returned
351 * This sets up large send offload for FCoE
353 * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error
355 int ixgbe_fso(struct ixgbe_adapter *adapter,
356 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
357 u32 tx_flags, u8 *hdr_len)
366 struct ixgbe_tx_buffer *tx_buffer_info;
367 struct ixgbe_adv_tx_context_desc *context_desc;
368 struct fc_frame_header *fh;
370 if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
371 DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
372 skb_shinfo(skb)->gso_type);
376 /* resets the header to point fcoe/fc */
377 skb_set_network_header(skb, skb->mac_len);
378 skb_set_transport_header(skb, skb->mac_len +
379 sizeof(struct fcoe_hdr));
381 /* sets up SOF and ORIS */
383 sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
386 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
389 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
390 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
395 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
398 DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof);
402 /* the first byte of the last dword is EOF */
403 skb_copy_bits(skb, skb->len - 4, &eof, 1);
404 /* sets up EOF and ORIE */
407 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
411 if (skb_is_gso(skb)) {
412 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
413 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE;
415 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T;
419 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI;
422 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A;
425 DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof);
429 /* sets up PARINC indicating data offset */
430 fh = (struct fc_frame_header *)skb_transport_header(skb);
431 if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
432 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC;
434 /* hdr_len includes fc_hdr if FCoE lso is enabled */
435 *hdr_len = sizeof(struct fcoe_crc_eof);
437 *hdr_len += (skb_transport_offset(skb) +
438 sizeof(struct fc_frame_header));
439 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
440 vlan_macip_lens = (skb_transport_offset(skb) +
441 sizeof(struct fc_frame_header));
442 vlan_macip_lens |= ((skb_transport_offset(skb) - 4)
443 << IXGBE_ADVTXD_MACLEN_SHIFT);
444 vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
446 /* type_tycmd and mss: set TUCMD.FCoE to enable offload */
447 type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT |
448 IXGBE_ADVTXT_TUCMD_FCOE;
450 mss = skb_shinfo(skb)->gso_size;
451 /* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */
452 mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) |
453 (1 << IXGBE_ADVTXD_IDX_SHIFT);
455 /* write context desc */
456 i = tx_ring->next_to_use;
457 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
458 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
459 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
460 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
461 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
463 tx_buffer_info = &tx_ring->tx_buffer_info[i];
464 tx_buffer_info->time_stamp = jiffies;
465 tx_buffer_info->next_to_watch = i;
468 if (i == tx_ring->count)
470 tx_ring->next_to_use = i;
472 return skb_is_gso(skb);
476 * ixgbe_configure_fcoe - configures registers for fcoe at start
477 * @adapter: ptr to ixgbe adapter
479 * This sets up FCoE related registers
483 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
485 int i, fcoe_q, fcoe_i;
486 struct ixgbe_hw *hw = &adapter->hw;
487 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
488 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
490 /* create the pool for ddp if not created yet */
492 /* allocate ddp pool */
493 fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp",
494 adapter->pdev, IXGBE_FCPTR_MAX,
495 IXGBE_FCPTR_ALIGN, PAGE_SIZE);
498 "failed to allocated FCoE DDP pool\n");
500 spin_lock_init(&fcoe->lock);
503 /* Enable L2 eth type filter for FCoE */
504 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
505 (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
506 if (adapter->ring_feature[RING_F_FCOE].indices) {
507 /* Use multiple rx queues for FCoE by redirection table */
508 for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
509 fcoe_i = f->mask + i % f->indices;
510 fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
511 fcoe_q = adapter->rx_ring[fcoe_i].reg_idx;
512 IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
514 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
515 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
517 /* Use single rx queue for FCoE */
519 fcoe_q = adapter->rx_ring[fcoe_i].reg_idx;
520 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
521 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
522 IXGBE_ETQS_QUEUE_EN |
523 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
526 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
527 IXGBE_FCRXCTRL_FCOELLI |
528 IXGBE_FCRXCTRL_FCCRCBO |
529 (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
533 * ixgbe_cleanup_fcoe - release all fcoe ddp context resources
534 * @adapter : ixgbe adapter
536 * Cleans up outstanding ddp context resources
540 void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter)
543 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
545 /* release ddp resource */
547 for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++)
548 ixgbe_fcoe_ddp_put(adapter->netdev, i);
549 pci_pool_destroy(fcoe->pool);