2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
11 * This file contains the implementation of hardware access methord for 20k2.
19 #include "ct20k2reg.h"
20 #include <linux/types.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
24 #include <linux/string.h>
25 #include <linux/kernel.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
29 #define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bits */
31 static u32 hw_read_20kx(struct hw *hw, u32 reg);
32 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
35 * Type definition block.
36 * The layout of control structures can be directly applied on 20k2 chip.
40 * SRC control block definitions.
43 /* SRC resource control block */
44 #define SRCCTL_STATE 0x00000007
45 #define SRCCTL_BM 0x00000008
46 #define SRCCTL_RSR 0x00000030
47 #define SRCCTL_SF 0x000001C0
48 #define SRCCTL_WR 0x00000200
49 #define SRCCTL_PM 0x00000400
50 #define SRCCTL_ROM 0x00001800
51 #define SRCCTL_VO 0x00002000
52 #define SRCCTL_ST 0x00004000
53 #define SRCCTL_IE 0x00008000
54 #define SRCCTL_ILSZ 0x000F0000
55 #define SRCCTL_BP 0x00100000
57 #define SRCCCR_CISZ 0x000007FF
58 #define SRCCCR_CWA 0x001FF800
59 #define SRCCCR_D 0x00200000
60 #define SRCCCR_RS 0x01C00000
61 #define SRCCCR_NAL 0x3E000000
62 #define SRCCCR_RA 0xC0000000
64 #define SRCCA_CA 0x0FFFFFFF
65 #define SRCCA_RS 0xE0000000
67 #define SRCSA_SA 0x0FFFFFFF
69 #define SRCLA_LA 0x0FFFFFFF
71 /* Mixer Parameter Ring ram Low and Hight register.
72 * Fixed-point value in 8.24 format for parameter channel */
73 #define MPRLH_PITCH 0xFFFFFFFF
75 /* SRC resource register dirty flags */
84 u16 czbfs:1; /* Clear Z-Buffers */
90 struct src_rsc_ctrl_blk {
97 union src_dirty dirty;
100 /* SRC manager control block */
101 union src_mgr_dirty {
117 struct src_mgr_ctrl_blk {
120 union src_mgr_dirty dirty;
123 /* SRCIMP manager control block */
124 #define SRCAIM_ARC 0x00000FFF
125 #define SRCAIM_NXT 0x00FF0000
126 #define SRCAIM_SRC 0xFF000000
133 /* SRCIMP manager register dirty flags */
134 union srcimp_mgr_dirty {
142 struct srcimp_mgr_ctrl_blk {
143 struct srcimap srcimap;
144 union srcimp_mgr_dirty dirty;
148 * Function implementation block.
151 static int src_get_rsc_ctrl_blk(void **rblk)
153 struct src_rsc_ctrl_blk *blk;
156 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
165 static int src_put_rsc_ctrl_blk(void *blk)
167 kfree((struct src_rsc_ctrl_blk *)blk);
172 static int src_set_state(void *blk, unsigned int state)
174 struct src_rsc_ctrl_blk *ctl = blk;
176 set_field(&ctl->ctl, SRCCTL_STATE, state);
177 ctl->dirty.bf.ctl = 1;
181 static int src_set_bm(void *blk, unsigned int bm)
183 struct src_rsc_ctrl_blk *ctl = blk;
185 set_field(&ctl->ctl, SRCCTL_BM, bm);
186 ctl->dirty.bf.ctl = 1;
190 static int src_set_rsr(void *blk, unsigned int rsr)
192 struct src_rsc_ctrl_blk *ctl = blk;
194 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
195 ctl->dirty.bf.ctl = 1;
199 static int src_set_sf(void *blk, unsigned int sf)
201 struct src_rsc_ctrl_blk *ctl = blk;
203 set_field(&ctl->ctl, SRCCTL_SF, sf);
204 ctl->dirty.bf.ctl = 1;
208 static int src_set_wr(void *blk, unsigned int wr)
210 struct src_rsc_ctrl_blk *ctl = blk;
212 set_field(&ctl->ctl, SRCCTL_WR, wr);
213 ctl->dirty.bf.ctl = 1;
217 static int src_set_pm(void *blk, unsigned int pm)
219 struct src_rsc_ctrl_blk *ctl = blk;
221 set_field(&ctl->ctl, SRCCTL_PM, pm);
222 ctl->dirty.bf.ctl = 1;
226 static int src_set_rom(void *blk, unsigned int rom)
228 struct src_rsc_ctrl_blk *ctl = blk;
230 set_field(&ctl->ctl, SRCCTL_ROM, rom);
231 ctl->dirty.bf.ctl = 1;
235 static int src_set_vo(void *blk, unsigned int vo)
237 struct src_rsc_ctrl_blk *ctl = blk;
239 set_field(&ctl->ctl, SRCCTL_VO, vo);
240 ctl->dirty.bf.ctl = 1;
244 static int src_set_st(void *blk, unsigned int st)
246 struct src_rsc_ctrl_blk *ctl = blk;
248 set_field(&ctl->ctl, SRCCTL_ST, st);
249 ctl->dirty.bf.ctl = 1;
253 static int src_set_ie(void *blk, unsigned int ie)
255 struct src_rsc_ctrl_blk *ctl = blk;
257 set_field(&ctl->ctl, SRCCTL_IE, ie);
258 ctl->dirty.bf.ctl = 1;
262 static int src_set_ilsz(void *blk, unsigned int ilsz)
264 struct src_rsc_ctrl_blk *ctl = blk;
266 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
267 ctl->dirty.bf.ctl = 1;
271 static int src_set_bp(void *blk, unsigned int bp)
273 struct src_rsc_ctrl_blk *ctl = blk;
275 set_field(&ctl->ctl, SRCCTL_BP, bp);
276 ctl->dirty.bf.ctl = 1;
280 static int src_set_cisz(void *blk, unsigned int cisz)
282 struct src_rsc_ctrl_blk *ctl = blk;
284 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
285 ctl->dirty.bf.ccr = 1;
289 static int src_set_ca(void *blk, unsigned int ca)
291 struct src_rsc_ctrl_blk *ctl = blk;
293 set_field(&ctl->ca, SRCCA_CA, ca);
294 ctl->dirty.bf.ca = 1;
298 static int src_set_sa(void *blk, unsigned int sa)
300 struct src_rsc_ctrl_blk *ctl = blk;
302 set_field(&ctl->sa, SRCSA_SA, sa);
303 ctl->dirty.bf.sa = 1;
307 static int src_set_la(void *blk, unsigned int la)
309 struct src_rsc_ctrl_blk *ctl = blk;
311 set_field(&ctl->la, SRCLA_LA, la);
312 ctl->dirty.bf.la = 1;
316 static int src_set_pitch(void *blk, unsigned int pitch)
318 struct src_rsc_ctrl_blk *ctl = blk;
320 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
321 ctl->dirty.bf.mpr = 1;
325 static int src_set_clear_zbufs(void *blk, unsigned int clear)
327 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
331 static int src_set_dirty(void *blk, unsigned int flags)
333 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
337 static int src_set_dirty_all(void *blk)
339 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
343 #define AR_SLOT_SIZE 4096
344 #define AR_SLOT_BLOCK_SIZE 16
345 #define AR_PTS_PITCH 6
346 #define AR_PARAM_SRC_OFFSET 0x60
348 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
350 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
351 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
355 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
357 struct src_rsc_ctrl_blk *ctl = blk;
360 if (ctl->dirty.bf.czbfs) {
361 /* Clear Z-Buffer registers */
362 for (i = 0; i < 8; i++)
363 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
365 for (i = 0; i < 4; i++)
366 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
368 for (i = 0; i < 8; i++)
369 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
371 ctl->dirty.bf.czbfs = 0;
373 if (ctl->dirty.bf.mpr) {
374 /* Take the parameter mixer resource in the same group as that
375 * the idx src is in for simplicity. Unlike src, all conjugate
376 * parameter mixer resources must be programmed for
377 * corresponding conjugate src resources. */
378 unsigned int pm_idx = src_param_pitch_mixer(idx);
379 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
380 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
381 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
382 ctl->dirty.bf.mpr = 0;
384 if (ctl->dirty.bf.sa) {
385 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
386 ctl->dirty.bf.sa = 0;
388 if (ctl->dirty.bf.la) {
389 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
390 ctl->dirty.bf.la = 0;
392 if (ctl->dirty.bf.ca) {
393 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
394 ctl->dirty.bf.ca = 0;
397 /* Write srccf register */
398 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
400 if (ctl->dirty.bf.ccr) {
401 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
402 ctl->dirty.bf.ccr = 0;
404 if (ctl->dirty.bf.ctl) {
405 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
406 ctl->dirty.bf.ctl = 0;
412 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
414 struct src_rsc_ctrl_blk *ctl = blk;
416 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
417 ctl->dirty.bf.ca = 0;
419 return get_field(ctl->ca, SRCCA_CA);
422 static unsigned int src_get_dirty(void *blk)
424 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
427 static unsigned int src_dirty_conj_mask(void)
432 static int src_mgr_enbs_src(void *blk, unsigned int idx)
434 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
435 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
436 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
440 static int src_mgr_enb_src(void *blk, unsigned int idx)
442 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
443 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
447 static int src_mgr_dsb_src(void *blk, unsigned int idx)
449 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
450 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
454 static int src_mgr_commit_write(struct hw *hw, void *blk)
456 struct src_mgr_ctrl_blk *ctl = blk;
458 unsigned int ret = 0;
460 if (ctl->dirty.bf.enbsa) {
462 ret = hw_read_20kx(hw, SRC_ENBSTAT);
464 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
465 ctl->dirty.bf.enbsa = 0;
467 for (i = 0; i < 8; i++) {
468 if ((ctl->dirty.data & (0x1 << i))) {
469 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
470 ctl->dirty.data &= ~(0x1 << i);
477 static int src_mgr_get_ctrl_blk(void **rblk)
479 struct src_mgr_ctrl_blk *blk;
482 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
491 static int src_mgr_put_ctrl_blk(void *blk)
493 kfree((struct src_mgr_ctrl_blk *)blk);
498 static int srcimp_mgr_get_ctrl_blk(void **rblk)
500 struct srcimp_mgr_ctrl_blk *blk;
503 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
512 static int srcimp_mgr_put_ctrl_blk(void *blk)
514 kfree((struct srcimp_mgr_ctrl_blk *)blk);
519 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
521 struct srcimp_mgr_ctrl_blk *ctl = blk;
523 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
524 ctl->dirty.bf.srcimap = 1;
528 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
530 struct srcimp_mgr_ctrl_blk *ctl = blk;
532 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
533 ctl->dirty.bf.srcimap = 1;
537 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
539 struct srcimp_mgr_ctrl_blk *ctl = blk;
541 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
542 ctl->dirty.bf.srcimap = 1;
546 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
548 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
549 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
553 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
555 struct srcimp_mgr_ctrl_blk *ctl = blk;
557 if (ctl->dirty.bf.srcimap) {
558 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
559 ctl->srcimap.srcaim);
560 ctl->dirty.bf.srcimap = 0;
567 * AMIXER control block definitions.
570 #define AMOPLO_M 0x00000003
571 #define AMOPLO_IV 0x00000004
572 #define AMOPLO_X 0x0003FFF0
573 #define AMOPLO_Y 0xFFFC0000
575 #define AMOPHI_SADR 0x000000FF
576 #define AMOPHI_SE 0x80000000
578 /* AMIXER resource register dirty flags */
588 /* AMIXER resource control block */
589 struct amixer_rsc_ctrl_blk {
592 union amixer_dirty dirty;
595 static int amixer_set_mode(void *blk, unsigned int mode)
597 struct amixer_rsc_ctrl_blk *ctl = blk;
599 set_field(&ctl->amoplo, AMOPLO_M, mode);
600 ctl->dirty.bf.amoplo = 1;
604 static int amixer_set_iv(void *blk, unsigned int iv)
606 struct amixer_rsc_ctrl_blk *ctl = blk;
608 set_field(&ctl->amoplo, AMOPLO_IV, iv);
609 ctl->dirty.bf.amoplo = 1;
613 static int amixer_set_x(void *blk, unsigned int x)
615 struct amixer_rsc_ctrl_blk *ctl = blk;
617 set_field(&ctl->amoplo, AMOPLO_X, x);
618 ctl->dirty.bf.amoplo = 1;
622 static int amixer_set_y(void *blk, unsigned int y)
624 struct amixer_rsc_ctrl_blk *ctl = blk;
626 set_field(&ctl->amoplo, AMOPLO_Y, y);
627 ctl->dirty.bf.amoplo = 1;
631 static int amixer_set_sadr(void *blk, unsigned int sadr)
633 struct amixer_rsc_ctrl_blk *ctl = blk;
635 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
636 ctl->dirty.bf.amophi = 1;
640 static int amixer_set_se(void *blk, unsigned int se)
642 struct amixer_rsc_ctrl_blk *ctl = blk;
644 set_field(&ctl->amophi, AMOPHI_SE, se);
645 ctl->dirty.bf.amophi = 1;
649 static int amixer_set_dirty(void *blk, unsigned int flags)
651 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
655 static int amixer_set_dirty_all(void *blk)
657 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
661 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
663 struct amixer_rsc_ctrl_blk *ctl = blk;
665 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
666 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
667 ctl->dirty.bf.amoplo = 0;
668 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
669 ctl->dirty.bf.amophi = 0;
675 static int amixer_get_y(void *blk)
677 struct amixer_rsc_ctrl_blk *ctl = blk;
679 return get_field(ctl->amoplo, AMOPLO_Y);
682 static unsigned int amixer_get_dirty(void *blk)
684 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
687 static int amixer_rsc_get_ctrl_blk(void **rblk)
689 struct amixer_rsc_ctrl_blk *blk;
692 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
701 static int amixer_rsc_put_ctrl_blk(void *blk)
703 kfree((struct amixer_rsc_ctrl_blk *)blk);
708 static int amixer_mgr_get_ctrl_blk(void **rblk)
715 static int amixer_mgr_put_ctrl_blk(void *blk)
721 * DAIO control block definitions.
724 /* Receiver Sample Rate Tracker Control register */
725 #define SRTCTL_SRCO 0x000000FF
726 #define SRTCTL_SRCM 0x0000FF00
727 #define SRTCTL_RSR 0x00030000
728 #define SRTCTL_DRAT 0x00300000
729 #define SRTCTL_EC 0x01000000
730 #define SRTCTL_ET 0x10000000
732 /* DAIO Receiver register dirty flags */
741 /* DAIO Receiver control block */
742 struct dai_ctrl_blk {
744 union dai_dirty dirty;
747 /* Audio Input Mapper RAM */
748 #define AIM_ARC 0x00000FFF
749 #define AIM_NXT 0x007F0000
756 /* Audio Transmitter Control and Status register */
757 #define ATXCTL_EN 0x00000001
758 #define ATXCTL_MODE 0x00000010
759 #define ATXCTL_CD 0x00000020
760 #define ATXCTL_RAW 0x00000100
761 #define ATXCTL_MT 0x00000200
762 #define ATXCTL_NUC 0x00003000
763 #define ATXCTL_BEN 0x00010000
764 #define ATXCTL_BMUX 0x00700000
765 #define ATXCTL_B24 0x01000000
766 #define ATXCTL_CPF 0x02000000
767 #define ATXCTL_RIV 0x10000000
768 #define ATXCTL_LIV 0x20000000
769 #define ATXCTL_RSAT 0x40000000
770 #define ATXCTL_LSAT 0x80000000
772 /* XDIF Transmitter register dirty flags */
781 /* XDIF Transmitter control block */
782 struct dao_ctrl_blk {
783 /* XDIF Transmitter Channel Status Low Register */
785 union dao_dirty dirty;
788 /* Audio Receiver Control register */
789 #define ARXCTL_EN 0x00000001
791 /* DAIO manager register dirty flags */
792 union daio_mgr_dirty {
802 /* DAIO manager control block */
803 struct daio_mgr_ctrl_blk {
804 struct daoimap daoimap;
805 unsigned int txctl[8];
806 unsigned int rxctl[8];
807 union daio_mgr_dirty dirty;
810 static int dai_srt_set_srco(void *blk, unsigned int src)
812 struct dai_ctrl_blk *ctl = blk;
814 set_field(&ctl->srt, SRTCTL_SRCO, src);
815 ctl->dirty.bf.srt = 1;
819 static int dai_srt_set_srcm(void *blk, unsigned int src)
821 struct dai_ctrl_blk *ctl = blk;
823 set_field(&ctl->srt, SRTCTL_SRCM, src);
824 ctl->dirty.bf.srt = 1;
828 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
830 struct dai_ctrl_blk *ctl = blk;
832 set_field(&ctl->srt, SRTCTL_RSR, rsr);
833 ctl->dirty.bf.srt = 1;
837 static int dai_srt_set_drat(void *blk, unsigned int drat)
839 struct dai_ctrl_blk *ctl = blk;
841 set_field(&ctl->srt, SRTCTL_DRAT, drat);
842 ctl->dirty.bf.srt = 1;
846 static int dai_srt_set_ec(void *blk, unsigned int ec)
848 struct dai_ctrl_blk *ctl = blk;
850 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
851 ctl->dirty.bf.srt = 1;
855 static int dai_srt_set_et(void *blk, unsigned int et)
857 struct dai_ctrl_blk *ctl = blk;
859 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
860 ctl->dirty.bf.srt = 1;
864 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
866 struct dai_ctrl_blk *ctl = blk;
868 if (ctl->dirty.bf.srt) {
869 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
870 ctl->dirty.bf.srt = 0;
876 static int dai_get_ctrl_blk(void **rblk)
878 struct dai_ctrl_blk *blk;
881 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
890 static int dai_put_ctrl_blk(void *blk)
892 kfree((struct dai_ctrl_blk *)blk);
897 static int dao_set_spos(void *blk, unsigned int spos)
899 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
900 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
904 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
906 struct dao_ctrl_blk *ctl = blk;
908 if (ctl->dirty.bf.atxcsl) {
911 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
914 ctl->dirty.bf.atxcsl = 0;
920 static int dao_get_spos(void *blk, unsigned int *spos)
922 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
926 static int dao_get_ctrl_blk(void **rblk)
928 struct dao_ctrl_blk *blk;
931 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
940 static int dao_put_ctrl_blk(void *blk)
942 kfree((struct dao_ctrl_blk *)blk);
947 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
949 struct daio_mgr_ctrl_blk *ctl = blk;
951 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
952 ctl->dirty.bf.arxctl |= (0x1 << idx);
956 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
958 struct daio_mgr_ctrl_blk *ctl = blk;
960 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
962 ctl->dirty.bf.arxctl |= (0x1 << idx);
966 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
968 struct daio_mgr_ctrl_blk *ctl = blk;
970 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
971 ctl->dirty.bf.atxctl |= (0x1 << idx);
975 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
977 struct daio_mgr_ctrl_blk *ctl = blk;
979 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
980 ctl->dirty.bf.atxctl |= (0x1 << idx);
984 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
986 struct daio_mgr_ctrl_blk *ctl = blk;
990 switch ((conf & 0x7)) {
992 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
995 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
998 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1001 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1007 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1009 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1011 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1012 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1013 ((conf >> 3) & 0x1) ? 0 : 0);
1014 ctl->dirty.bf.atxctl |= (0x1 << idx);
1022 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1024 struct daio_mgr_ctrl_blk *ctl = blk;
1026 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1027 ctl->dirty.bf.daoimap = 1;
1031 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1033 struct daio_mgr_ctrl_blk *ctl = blk;
1035 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1036 ctl->dirty.bf.daoimap = 1;
1040 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1042 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1043 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1047 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1049 struct daio_mgr_ctrl_blk *ctl = blk;
1050 unsigned int data = 0;
1053 for (i = 0; i < 8; i++) {
1054 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1055 data = ctl->txctl[i];
1056 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1057 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1060 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1061 data = ctl->rxctl[i];
1062 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1063 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1067 if (ctl->dirty.bf.daoimap) {
1068 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1070 ctl->dirty.bf.daoimap = 0;
1076 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1078 struct daio_mgr_ctrl_blk *blk;
1082 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1086 for (i = 0; i < 8; i++) {
1087 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1088 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1096 static int daio_mgr_put_ctrl_blk(void *blk)
1098 kfree((struct daio_mgr_ctrl_blk *)blk);
1103 /* Card hardware initialization block */
1105 unsigned int msr; /* master sample rate in rsrs */
1109 unsigned int msr; /* master sample rate in rsrs */
1110 unsigned char input; /* the input source of ADC */
1111 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1115 unsigned int msr; /* master sample rate in rsrs */
1119 unsigned long vm_pgt_phys;
1122 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1127 /* Program I2S with proper sample rate and enable the correct I2S
1128 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1129 if (1 == info->msr) {
1130 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1131 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1132 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1133 } else if (2 == info->msr) {
1134 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1135 /* Specify all playing 96khz
1139 * RTB [12:13] - 96kHz
1141 * RTC [20:21] - 96kHz
1143 * RTD [28:29] - 96kHz */
1144 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1145 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1147 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1151 for (i = 0; i < 8; i++) {
1153 /* 1st 3 channels are SPDIFs (SB0960) */
1159 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
1160 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
1162 /* Initialize the SPDIF Out Channel status registers.
1163 * The value specified here is based on the typical
1164 * values provided in the specification, namely: Clock
1165 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1166 * unspecified source number, Generation status = 1,
1167 * Category code = 0x12 (Digital Signal Mixer),
1168 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1169 * (indicating that we're transmitting digital audio,
1170 * and the Professional Use bit is 0. */
1172 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1173 0x02109204); /* Default to 48kHz */
1175 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1177 /* Next 5 channels are I2S (SB0960) */
1179 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
1180 if (2 == info->msr) {
1181 /* Four channels per sample period */
1184 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
1191 /* TRANSPORT operations */
1192 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1194 u32 vmctl = 0, data = 0;
1195 unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1198 /* Set up device page table */
1199 if ((~0UL) == info->vm_pgt_phys) {
1200 printk(KERN_ALERT "ctxfi: "
1201 "Wrong device page table page address!!!\n");
1205 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1206 ptp_phys_low = (u32)info->vm_pgt_phys;
1207 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1208 if (sizeof(void *) == 8) /* 64bit address */
1210 /* Write page table physical address to all PTPAL registers */
1211 for (i = 0; i < 64; i++) {
1212 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1213 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1215 /* Enable virtual memory transfer */
1216 hw_write_20kx(hw, VMEM_CTL, vmctl);
1217 /* Enable transport bus master and queueing of request */
1218 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1219 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1220 /* Enable transport ring */
1221 data = hw_read_20kx(hw, TRANSPORT_ENB);
1222 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1227 /* Card initialization */
1228 #define GCTL_AIE 0x00000001
1229 #define GCTL_UAA 0x00000002
1230 #define GCTL_DPC 0x00000004
1231 #define GCTL_DBP 0x00000008
1232 #define GCTL_ABP 0x00000010
1233 #define GCTL_TBP 0x00000020
1234 #define GCTL_SBP 0x00000040
1235 #define GCTL_FBP 0x00000080
1236 #define GCTL_ME 0x00000100
1237 #define GCTL_AID 0x00001000
1239 #define PLLCTL_SRC 0x00000007
1240 #define PLLCTL_SPE 0x00000008
1241 #define PLLCTL_RD 0x000000F0
1242 #define PLLCTL_FD 0x0001FF00
1243 #define PLLCTL_OD 0x00060000
1244 #define PLLCTL_B 0x00080000
1245 #define PLLCTL_AS 0x00100000
1246 #define PLLCTL_LF 0x03E00000
1247 #define PLLCTL_SPS 0x1C000000
1248 #define PLLCTL_AD 0x60000000
1250 #define PLLSTAT_CCS 0x00000007
1251 #define PLLSTAT_SPL 0x00000008
1252 #define PLLSTAT_CRD 0x000000F0
1253 #define PLLSTAT_CFD 0x0001FF00
1254 #define PLLSTAT_SL 0x00020000
1255 #define PLLSTAT_FAS 0x00040000
1256 #define PLLSTAT_B 0x00080000
1257 #define PLLSTAT_PD 0x00100000
1258 #define PLLSTAT_OCA 0x00200000
1259 #define PLLSTAT_NCA 0x00400000
1261 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1263 unsigned int pllenb;
1264 unsigned int pllctl;
1265 unsigned int pllstat;
1269 hw_write_20kx(hw, PLL_ENB, pllenb);
1270 pllctl = 0x20D00000;
1271 set_field(&pllctl, PLLCTL_FD, 16 - 4);
1272 hw_write_20kx(hw, PLL_CTL, pllctl);
1274 pllctl = hw_read_20kx(hw, PLL_CTL);
1275 set_field(&pllctl, PLLCTL_B, 0);
1277 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1278 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1279 } else { /* 44100 */
1280 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1281 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1283 hw_write_20kx(hw, PLL_CTL, pllctl);
1285 for (i = 0; i < 1000; i++) {
1286 pllstat = hw_read_20kx(hw, PLL_STAT);
1287 if (get_field(pllstat, PLLSTAT_PD))
1290 if (get_field(pllstat, PLLSTAT_B) !=
1291 get_field(pllctl, PLLCTL_B))
1294 if (get_field(pllstat, PLLSTAT_CCS) !=
1295 get_field(pllctl, PLLCTL_SRC))
1298 if (get_field(pllstat, PLLSTAT_CRD) !=
1299 get_field(pllctl, PLLCTL_RD))
1302 if (get_field(pllstat, PLLSTAT_CFD) !=
1303 get_field(pllctl, PLLCTL_FD))
1309 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1316 static int hw_auto_init(struct hw *hw)
1321 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1322 set_field(&gctl, GCTL_AIE, 0);
1323 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1324 set_field(&gctl, GCTL_AIE, 1);
1325 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1327 for (i = 0; i < 400000; i++) {
1328 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1329 if (get_field(gctl, GCTL_AID))
1332 if (!get_field(gctl, GCTL_AID)) {
1333 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1340 /* DAC operations */
1342 #define CS4382_MC1 0x1
1343 #define CS4382_MC2 0x2
1344 #define CS4382_MC3 0x3
1345 #define CS4382_FC 0x4
1346 #define CS4382_IC 0x5
1347 #define CS4382_XC1 0x6
1348 #define CS4382_VCA1 0x7
1349 #define CS4382_VCB1 0x8
1350 #define CS4382_XC2 0x9
1351 #define CS4382_VCA2 0xA
1352 #define CS4382_VCB2 0xB
1353 #define CS4382_XC3 0xC
1354 #define CS4382_VCA3 0xD
1355 #define CS4382_VCB3 0xE
1356 #define CS4382_XC4 0xF
1357 #define CS4382_VCA4 0x10
1358 #define CS4382_VCB4 0x11
1359 #define CS4382_CREV 0x12
1362 #define STATE_LOCKED 0x00
1363 #define STATE_UNLOCKED 0xAA
1364 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1365 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1367 #define I2C_STATUS_DCM 0x00000001
1368 #define I2C_STATUS_BC 0x00000006
1369 #define I2C_STATUS_APD 0x00000008
1370 #define I2C_STATUS_AB 0x00010000
1371 #define I2C_STATUS_DR 0x00800000
1373 #define I2C_ADDRESS_PTAD 0x0000FFFF
1374 #define I2C_ADDRESS_SLAD 0x007F0000
1376 struct REGS_CS4382 {
1377 u32 dwModeControl_1;
1378 u32 dwModeControl_2;
1379 u32 dwModeControl_3;
1381 u32 dwFilterControl;
1382 u32 dwInvertControl;
1384 u32 dwMixControl_P1;
1385 u32 dwVolControl_A1;
1386 u32 dwVolControl_B1;
1388 u32 dwMixControl_P2;
1389 u32 dwVolControl_A2;
1390 u32 dwVolControl_B2;
1392 u32 dwMixControl_P3;
1393 u32 dwVolControl_A3;
1394 u32 dwVolControl_B3;
1396 u32 dwMixControl_P4;
1397 u32 dwVolControl_A4;
1398 u32 dwVolControl_B4;
1401 static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
1403 static int I2CUnlockFullAccess(struct hw *hw)
1405 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1407 /* Send keys for forced BIOS mode */
1408 hw_write_20kx(hw, I2C_IF_WLOCK,
1409 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1410 hw_write_20kx(hw, I2C_IF_WLOCK,
1411 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1412 /* Check whether the chip is unlocked */
1413 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1419 static int I2CLockChip(struct hw *hw)
1422 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1423 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1424 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1430 static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
1433 unsigned int RegI2CStatus;
1434 unsigned int RegI2CAddress;
1436 err = I2CUnlockFullAccess(hw);
1440 m_bAddressSize = bAddressSize;
1441 m_bDataSize = bDataSize;
1442 m_bDeviceID = bDeviceID;
1445 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
1447 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1449 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1451 set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
1453 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1458 static int I2CUninit(struct hw *hw)
1460 unsigned int RegI2CStatus;
1461 unsigned int RegI2CAddress;
1464 set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1466 hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1468 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1470 set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
1472 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1474 return I2CLockChip(hw);
1477 static int I2CWaitDataReady(struct hw *hw)
1480 unsigned int ret = 0;
1483 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1484 } while ((!(ret & DATA_READY)) && --i);
1489 static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
1491 unsigned int RegI2CStatus;
1493 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1494 set_field(&RegI2CStatus, I2C_STATUS_BC,
1495 (4 == m_bAddressSize) ? 0 : m_bAddressSize);
1496 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1497 if (!I2CWaitDataReady(hw))
1500 hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
1501 if (!I2CWaitDataReady(hw))
1504 /* Force a read operation */
1505 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1506 if (!I2CWaitDataReady(hw))
1509 *pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
1514 static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1516 unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
1517 unsigned int RegI2CStatus;
1519 RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1521 set_field(&RegI2CStatus, I2C_STATUS_BC,
1522 (4 == (m_bAddressSize + m_bDataSize)) ?
1523 0 : (m_bAddressSize + m_bDataSize));
1525 hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1526 I2CWaitDataReady(hw);
1527 /* Dummy write to trigger the write oprtation */
1528 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1529 I2CWaitDataReady(hw);
1531 /* This is the real data */
1532 hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
1533 I2CWaitDataReady(hw);
1538 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1543 struct REGS_CS4382 cs4382_Read = {0};
1544 struct REGS_CS4382 cs4382_Def = {
1545 0x00000001, /* Mode Control 1 */
1546 0x00000000, /* Mode Control 2 */
1547 0x00000084, /* Mode Control 3 */
1548 0x00000000, /* Filter Control */
1549 0x00000000, /* Invert Control */
1550 0x00000024, /* Mixing Control Pair 1 */
1551 0x00000000, /* Vol Control A1 */
1552 0x00000000, /* Vol Control B1 */
1553 0x00000024, /* Mixing Control Pair 2 */
1554 0x00000000, /* Vol Control A2 */
1555 0x00000000, /* Vol Control B2 */
1556 0x00000024, /* Mixing Control Pair 3 */
1557 0x00000000, /* Vol Control A3 */
1558 0x00000000, /* Vol Control B3 */
1559 0x00000024, /* Mixing Control Pair 4 */
1560 0x00000000, /* Vol Control A4 */
1561 0x00000000 /* Vol Control B4 */
1564 /* Set DAC reset bit as output */
1565 dwData = hw_read_20kx(hw, GPIO_CTRL);
1567 hw_write_20kx(hw, GPIO_CTRL, dwData);
1569 err = I2CInit(hw, 0x18, 1, 1);
1573 for (i = 0; i < 2; i++) {
1574 /* Reset DAC twice just in-case the chip
1575 * didn't initialized properly */
1576 dwData = hw_read_20kx(hw, GPIO_DATA);
1577 /* GPIO data bit 1 */
1578 dwData &= 0xFFFFFFFD;
1579 hw_write_20kx(hw, GPIO_DATA, dwData);
1582 hw_write_20kx(hw, GPIO_DATA, dwData);
1585 /* Reset the 2nd time */
1586 dwData &= 0xFFFFFFFD;
1587 hw_write_20kx(hw, GPIO_DATA, dwData);
1590 hw_write_20kx(hw, GPIO_DATA, dwData);
1593 if (I2CRead(hw, CS4382_MC1, &cs4382_Read.dwModeControl_1))
1596 if (I2CRead(hw, CS4382_MC2, &cs4382_Read.dwModeControl_2))
1599 if (I2CRead(hw, CS4382_MC3, &cs4382_Read.dwModeControl_3))
1602 if (I2CRead(hw, CS4382_FC, &cs4382_Read.dwFilterControl))
1605 if (I2CRead(hw, CS4382_IC, &cs4382_Read.dwInvertControl))
1608 if (I2CRead(hw, CS4382_XC1, &cs4382_Read.dwMixControl_P1))
1611 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
1614 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
1617 if (I2CRead(hw, CS4382_XC2, &cs4382_Read.dwMixControl_P2))
1620 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
1623 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
1626 if (I2CRead(hw, CS4382_XC3, &cs4382_Read.dwMixControl_P3))
1629 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
1632 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
1635 if (I2CRead(hw, CS4382_XC4, &cs4382_Read.dwMixControl_P4))
1638 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
1641 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
1644 if (memcmp(&cs4382_Read, &cs4382_Def,
1645 sizeof(struct REGS_CS4382)))
1654 /* Note: Every I2C write must have some delay.
1655 * This is not a requirement but the delay works here... */
1656 I2CWrite(hw, CS4382_MC1, 0x80);
1657 I2CWrite(hw, CS4382_MC2, 0x10);
1658 if (1 == info->msr) {
1659 I2CWrite(hw, CS4382_XC1, 0x24);
1660 I2CWrite(hw, CS4382_XC2, 0x24);
1661 I2CWrite(hw, CS4382_XC3, 0x24);
1662 I2CWrite(hw, CS4382_XC4, 0x24);
1663 } else if (2 == info->msr) {
1664 I2CWrite(hw, CS4382_XC1, 0x25);
1665 I2CWrite(hw, CS4382_XC2, 0x25);
1666 I2CWrite(hw, CS4382_XC3, 0x25);
1667 I2CWrite(hw, CS4382_XC4, 0x25);
1669 I2CWrite(hw, CS4382_XC1, 0x26);
1670 I2CWrite(hw, CS4382_XC2, 0x26);
1671 I2CWrite(hw, CS4382_XC3, 0x26);
1672 I2CWrite(hw, CS4382_XC4, 0x26);
1682 /* ADC operations */
1683 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1684 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1686 #define WM8775_IC 0x0B
1687 #define WM8775_MMC 0x0C
1688 #define WM8775_AADCL 0x0E
1689 #define WM8775_AADCR 0x0F
1690 #define WM8775_ADCMC 0x15
1691 #define WM8775_RESET 0x17
1693 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1697 data = hw_read_20kx(hw, GPIO_DATA);
1700 data = (data & (0x1 << 14)) ? 1 : 0;
1703 data = (data & (0x1 << 14)) ? 0 : 1;
1711 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1715 data = hw_read_20kx(hw, GPIO_DATA);
1718 data |= (0x1 << 14);
1719 hw_write_20kx(hw, GPIO_DATA, data);
1720 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1721 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1722 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1723 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1724 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1725 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1728 data &= ~(0x1 << 14);
1729 hw_write_20kx(hw, GPIO_DATA, data);
1730 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1731 MAKE_WM8775_DATA(0x102)); /* Line-in */
1732 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1733 MAKE_WM8775_DATA(0xCF)); /* No boost */
1734 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1735 MAKE_WM8775_DATA(0xCF)); /* No boost */
1744 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1747 u32 dwMux = 2, dwData = 0, dwCtl = 0;
1749 /* Set ADC reset bit as output */
1750 dwData = hw_read_20kx(hw, GPIO_CTRL);
1751 dwData |= (0x1 << 15);
1752 hw_write_20kx(hw, GPIO_CTRL, dwData);
1754 /* Initialize I2C */
1755 err = I2CInit(hw, 0x1A, 1, 1);
1757 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1761 /* Make ADC in normal operation */
1762 dwData = hw_read_20kx(hw, GPIO_DATA);
1763 dwData &= ~(0x1 << 15);
1765 dwData |= (0x1 << 15);
1766 hw_write_20kx(hw, GPIO_DATA, dwData);
1769 /* Set the master mode (256fs) */
1770 if (1 == info->msr) {
1771 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1772 MAKE_WM8775_DATA(0x02));
1773 } else if (2 == info->msr) {
1774 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1775 MAKE_WM8775_DATA(0x0A));
1777 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1778 "rate (msr %d)!!!\n", info->msr);
1783 /* Configure GPIO bit 14 change to line-in/mic-in */
1784 dwCtl = hw_read_20kx(hw, GPIO_CTRL);
1786 hw_write_20kx(hw, GPIO_CTRL, dwCtl);
1788 /* Check using Mic-in or Line-in */
1789 dwData = hw_read_20kx(hw, GPIO_DATA);
1792 /* Configures GPIO data to select Mic-in */
1794 hw_write_20kx(hw, GPIO_DATA, dwData);
1796 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1797 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1798 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1799 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1800 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1801 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1802 } else if (dwMux == 2) {
1803 /* Configures GPIO data to select Line-in */
1804 dwData &= ~(0x1<<14);
1805 hw_write_20kx(hw, GPIO_DATA, dwData);
1808 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1809 MAKE_WM8775_DATA(0x102)); /* Line-in */
1810 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1811 MAKE_WM8775_DATA(0xCF)); /* No boost */
1812 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1813 MAKE_WM8775_DATA(0xCF)); /* No boost */
1815 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
1827 static int hw_have_digit_io_switch(struct hw *hw)
1832 static int hw_card_start(struct hw *hw)
1835 struct pci_dev *pci = hw->pci;
1837 unsigned int dma_mask = 0;
1839 err = pci_enable_device(pci);
1843 /* Set DMA transfer mask */
1844 dma_mask = CT_XFI_DMA_MASK;
1845 if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1846 pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1847 printk(KERN_ERR "ctxfi: architecture does not support PCI "
1848 "busmaster DMA with mask 0x%x\n", dma_mask);
1853 err = pci_request_regions(pci, "XFi");
1857 hw->io_base = pci_resource_start(hw->pci, 2);
1858 hw->mem_base = (unsigned long)ioremap(hw->io_base,
1859 pci_resource_len(hw->pci, 2));
1860 if (NULL == (void *)hw->mem_base) {
1865 /* Switch to 20k2 mode from UAA mode. */
1866 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1867 set_field(&gctl, GCTL_UAA, 0);
1868 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1870 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1871 atc->chip_details->nm_card, hw))) {
1877 pci_set_master(pci);
1882 iounmap((void *)hw->mem_base);
1883 hw->mem_base = (unsigned long)NULL;*/
1885 pci_release_regions(pci);
1888 pci_disable_device(pci);
1892 static int hw_card_stop(struct hw *hw)
1894 /* TODO: Disable interrupt and so on... */
1898 static int hw_card_shutdown(struct hw *hw)
1901 free_irq(hw->irq, hw);
1905 if (NULL != ((void *)hw->mem_base))
1906 iounmap((void *)hw->mem_base);
1908 hw->mem_base = (unsigned long)NULL;
1911 pci_release_regions(hw->pci);
1915 pci_disable_device(hw->pci);
1920 static int hw_card_init(struct hw *hw, struct card_conf *info)
1925 struct dac_conf dac_info = {0};
1926 struct adc_conf adc_info = {0};
1927 struct daio_conf daio_info = {0};
1928 struct trn_conf trn_info = {0};
1930 /* Get PCI io port/memory base address and
1931 * do 20kx core switch if needed. */
1933 err = hw_card_start(hw);
1939 err = hw_pll_init(hw, info->rsr);
1943 /* kick off auto-init */
1944 err = hw_auto_init(hw);
1948 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1949 set_field(&gctl, GCTL_DBP, 1);
1950 set_field(&gctl, GCTL_TBP, 1);
1951 set_field(&gctl, GCTL_FBP, 1);
1952 set_field(&gctl, GCTL_DPC, 0);
1953 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1955 /* Reset all global pending interrupts */
1956 hw_write_20kx(hw, INTERRUPT_GIE, 0);
1957 /* Reset all SRC pending interrupts */
1958 hw_write_20kx(hw, SRC_IP, 0);
1960 /* TODO: detect the card ID and configure GPIO accordingly. */
1961 /* Configures GPIO (0xD802 0x98028) */
1962 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1963 /* Configures GPIO (SB0880) */
1964 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1965 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1967 /* Enable audio ring */
1968 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1970 trn_info.vm_pgt_phys = info->vm_pgt_phys;
1971 err = hw_trn_init(hw, &trn_info);
1975 daio_info.msr = info->msr;
1976 err = hw_daio_init(hw, &daio_info);
1980 dac_info.msr = info->msr;
1981 err = hw_dac_init(hw, &dac_info);
1985 adc_info.msr = info->msr;
1986 adc_info.input = ADC_LINEIN;
1987 adc_info.mic20db = 0;
1988 err = hw_adc_init(hw, &adc_info);
1992 data = hw_read_20kx(hw, SRC_MCTL);
1993 data |= 0x1; /* Enables input from the audio ring */
1994 hw_write_20kx(hw, SRC_MCTL, data);
1999 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2001 return readl((void *)(hw->mem_base + reg));
2004 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2006 writel(data, (void *)(hw->mem_base + reg));
2009 int create_20k2_hw_obj(struct hw **rhw)
2014 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2019 hw->mem_base = (unsigned long)NULL;
2022 hw->card_init = hw_card_init;
2023 hw->card_stop = hw_card_stop;
2024 hw->pll_init = hw_pll_init;
2025 hw->is_adc_source_selected = hw_is_adc_input_selected;
2026 hw->select_adc_source = hw_adc_input_select;
2027 hw->have_digit_io_switch = hw_have_digit_io_switch;
2029 hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2030 hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2031 hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2032 hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2033 hw->src_set_state = src_set_state;
2034 hw->src_set_bm = src_set_bm;
2035 hw->src_set_rsr = src_set_rsr;
2036 hw->src_set_sf = src_set_sf;
2037 hw->src_set_wr = src_set_wr;
2038 hw->src_set_pm = src_set_pm;
2039 hw->src_set_rom = src_set_rom;
2040 hw->src_set_vo = src_set_vo;
2041 hw->src_set_st = src_set_st;
2042 hw->src_set_ie = src_set_ie;
2043 hw->src_set_ilsz = src_set_ilsz;
2044 hw->src_set_bp = src_set_bp;
2045 hw->src_set_cisz = src_set_cisz;
2046 hw->src_set_ca = src_set_ca;
2047 hw->src_set_sa = src_set_sa;
2048 hw->src_set_la = src_set_la;
2049 hw->src_set_pitch = src_set_pitch;
2050 hw->src_set_dirty = src_set_dirty;
2051 hw->src_set_clear_zbufs = src_set_clear_zbufs;
2052 hw->src_set_dirty_all = src_set_dirty_all;
2053 hw->src_commit_write = src_commit_write;
2054 hw->src_get_ca = src_get_ca;
2055 hw->src_get_dirty = src_get_dirty;
2056 hw->src_dirty_conj_mask = src_dirty_conj_mask;
2057 hw->src_mgr_enbs_src = src_mgr_enbs_src;
2058 hw->src_mgr_enb_src = src_mgr_enb_src;
2059 hw->src_mgr_dsb_src = src_mgr_dsb_src;
2060 hw->src_mgr_commit_write = src_mgr_commit_write;
2062 hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2063 hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2064 hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2065 hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2066 hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2067 hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2068 hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2070 hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2071 hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2072 hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2073 hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2074 hw->amixer_set_mode = amixer_set_mode;
2075 hw->amixer_set_iv = amixer_set_iv;
2076 hw->amixer_set_x = amixer_set_x;
2077 hw->amixer_set_y = amixer_set_y;
2078 hw->amixer_set_sadr = amixer_set_sadr;
2079 hw->amixer_set_se = amixer_set_se;
2080 hw->amixer_set_dirty = amixer_set_dirty;
2081 hw->amixer_set_dirty_all = amixer_set_dirty_all;
2082 hw->amixer_commit_write = amixer_commit_write;
2083 hw->amixer_get_y = amixer_get_y;
2084 hw->amixer_get_dirty = amixer_get_dirty;
2086 hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2087 hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2088 hw->dai_srt_set_srco = dai_srt_set_srco;
2089 hw->dai_srt_set_srcm = dai_srt_set_srcm;
2090 hw->dai_srt_set_rsr = dai_srt_set_rsr;
2091 hw->dai_srt_set_drat = dai_srt_set_drat;
2092 hw->dai_srt_set_ec = dai_srt_set_ec;
2093 hw->dai_srt_set_et = dai_srt_set_et;
2094 hw->dai_commit_write = dai_commit_write;
2096 hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2097 hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2098 hw->dao_set_spos = dao_set_spos;
2099 hw->dao_commit_write = dao_commit_write;
2100 hw->dao_get_spos = dao_get_spos;
2102 hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2103 hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2104 hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2105 hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2106 hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2107 hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2108 hw->daio_mgr_dao_init = daio_mgr_dao_init;
2109 hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2110 hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2111 hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2112 hw->daio_mgr_commit_write = daio_mgr_commit_write;
2119 int destroy_20k2_hw_obj(struct hw *hw)
2122 hw_card_shutdown(hw);