git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 /* We use the hw_value as an index into our private channel structure */
  32
  33 #define CHAN2G(_freq, _idx)  { \
  34         .center_freq = (_freq), \
  35         .hw_value = (_idx), \
  36         .max_power = 30, \
  37 }
  38
  39 #define CHAN5G(_freq, _idx) { \
  40         .band = IEEE80211_BAND_5GHZ, \
  41         .center_freq = (_freq), \
  42         .hw_value = (_idx), \
  43         .max_power = 30, \
  44 }
  45
  46 /* Some 2 GHz radios are actually tunable on 2312-2732
  47  * on 5 MHz steps, we support the channels which we know
  48  * we have calibration data for all cards though to make
  49  * this static */
  50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  51         CHAN2G(2412, 0), /* Channel 1 */
  52         CHAN2G(2417, 1), /* Channel 2 */
  53         CHAN2G(2422, 2), /* Channel 3 */
  54         CHAN2G(2427, 3), /* Channel 4 */
  55         CHAN2G(2432, 4), /* Channel 5 */
  56         CHAN2G(2437, 5), /* Channel 6 */
  57         CHAN2G(2442, 6), /* Channel 7 */
  58         CHAN2G(2447, 7), /* Channel 8 */
  59         CHAN2G(2452, 8), /* Channel 9 */
  60         CHAN2G(2457, 9), /* Channel 10 */
  61         CHAN2G(2462, 10), /* Channel 11 */
  62         CHAN2G(2467, 11), /* Channel 12 */
  63         CHAN2G(2472, 12), /* Channel 13 */
  64         CHAN2G(2484, 13), /* Channel 14 */
  65 };
  66
  67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  68  * on 5 MHz steps, we support the channels which we know
  69  * we have calibration data for all cards though to make
  70  * this static */
  71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  72         /* _We_ call this UNII 1 */
  73         CHAN5G(5180, 14), /* Channel 36 */
  74         CHAN5G(5200, 15), /* Channel 40 */
  75         CHAN5G(5220, 16), /* Channel 44 */
  76         CHAN5G(5240, 17), /* Channel 48 */
  77         /* _We_ call this UNII 2 */
  78         CHAN5G(5260, 18), /* Channel 52 */
  79         CHAN5G(5280, 19), /* Channel 56 */
  80         CHAN5G(5300, 20), /* Channel 60 */
  81         CHAN5G(5320, 21), /* Channel 64 */
  82         /* _We_ call this "Middle band" */
  83         CHAN5G(5500, 22), /* Channel 100 */
  84         CHAN5G(5520, 23), /* Channel 104 */
  85         CHAN5G(5540, 24), /* Channel 108 */
  86         CHAN5G(5560, 25), /* Channel 112 */
  87         CHAN5G(5580, 26), /* Channel 116 */
  88         CHAN5G(5600, 27), /* Channel 120 */
  89         CHAN5G(5620, 28), /* Channel 124 */
  90         CHAN5G(5640, 29), /* Channel 128 */
  91         CHAN5G(5660, 30), /* Channel 132 */
  92         CHAN5G(5680, 31), /* Channel 136 */
  93         CHAN5G(5700, 32), /* Channel 140 */
  94         /* _We_ call this UNII 3 */
  95         CHAN5G(5745, 33), /* Channel 149 */
  96         CHAN5G(5765, 34), /* Channel 153 */
  97         CHAN5G(5785, 35), /* Channel 157 */
  98         CHAN5G(5805, 36), /* Channel 161 */
  99         CHAN5G(5825, 37), /* Channel 165 */
 100 };
 101
 102 static void ath_cache_conf_rate(struct ath_softc *sc,
 103                                 struct ieee80211_conf *conf)
 104 {
 105         switch (conf->channel->band) {
 106         case IEEE80211_BAND_2GHZ:
 107                 if (conf_is_ht20(conf))
 108                         sc->cur_rate_table =
 109                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 110                 else if (conf_is_ht40_minus(conf))
 111                         sc->cur_rate_table =
 112                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 113                 else if (conf_is_ht40_plus(conf))
 114                         sc->cur_rate_table =
 115                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 116                 else
 117                         sc->cur_rate_table =
 118                           sc->hw_rate_table[ATH9K_MODE_11G];
 119                 break;
 120         case IEEE80211_BAND_5GHZ:
 121                 if (conf_is_ht20(conf))
 122                         sc->cur_rate_table =
 123                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 124                 else if (conf_is_ht40_minus(conf))
 125                         sc->cur_rate_table =
 126                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 127                 else if (conf_is_ht40_plus(conf))
 128                         sc->cur_rate_table =
 129                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 130                 else
 131                         sc->cur_rate_table =
 132                           sc->hw_rate_table[ATH9K_MODE_11A];
 133                 break;
 134         default:
 135                 BUG_ON(1);
 136                 break;
 137         }
 138 }
 139
 140 static void ath_update_txpow(struct ath_softc *sc)
 141 {
 142         struct ath_hal *ah = sc->sc_ah;
 143         u32 txpow;
 144
 145         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 146                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 147                 /* read back in case value is clamped */
 148                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 149                 sc->sc_curtxpow = txpow;
 150         }
 151 }
 152
 153 static u8 parse_mpdudensity(u8 mpdudensity)
 154 {
 155         /*
 156          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 157          *   0 for no restriction
 158          *   1 for 1/4 us
 159          *   2 for 1/2 us
 160          *   3 for 1 us
 161          *   4 for 2 us
 162          *   5 for 4 us
 163          *   6 for 8 us
 164          *   7 for 16 us
 165          */
 166         switch (mpdudensity) {
 167         case 0:
 168                 return 0;
 169         case 1:
 170         case 2:
 171         case 3:
 172                 /* Our lower layer calculations limit our precision to
 173                    1 microsecond */
 174                 return 1;
 175         case 4:
 176                 return 2;
 177         case 5:
 178                 return 4;
 179         case 6:
 180                 return 8;
 181         case 7:
 182                 return 16;
 183         default:
 184                 return 0;
 185         }
 186 }
 187
 188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 189 {
 190         struct ath_rate_table *rate_table = NULL;
 191         struct ieee80211_supported_band *sband;
 192         struct ieee80211_rate *rate;
 193         int i, maxrates;
 194
 195         switch (band) {
 196         case IEEE80211_BAND_2GHZ:
 197                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 198                 break;
 199         case IEEE80211_BAND_5GHZ:
 200                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         if (rate_table == NULL)
 207                 return;
 208
 209         sband = &sc->sbands[band];
 210         rate = sc->rates[band];
 211
 212         if (rate_table->rate_cnt > ATH_RATE_MAX)
 213                 maxrates = ATH_RATE_MAX;
 214         else
 215                 maxrates = rate_table->rate_cnt;
 216
 217         for (i = 0; i < maxrates; i++) {
 218                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 219                 rate[i].hw_value = rate_table->info[i].ratecode;
 220                 if (rate_table->info[i].short_preamble) {
 221                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 222                                 rate_table->info[i].short_preamble;
 223                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 224                 }
 225                 sband->n_bitrates++;
 226
 227                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 228                         rate[i].bitrate / 10, rate[i].hw_value);
 229         }
 230 }
 231
 232 /*
 233  * Set/change channels.  If the channel is really being changed, it's done
 234  * by reseting the chip.  To accomplish this we must first cleanup any pending
 235  * DMA, then restart stuff.
 236 */
 237 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 238 {
 239         struct ath_hal *ah = sc->sc_ah;
 240         bool fastcc = true, stopped;
 241         struct ieee80211_hw *hw = sc->hw;
 242         struct ieee80211_channel *channel = hw->conf.channel;
 243         int r;
 244
 245         if (sc->sc_flags & SC_OP_INVALID)
 246                 return -EIO;
 247
 248         ath9k_ps_wakeup(sc);
 249
 250         /*
 251          * This is only performed if the channel settings have
 252          * actually changed.
 253          *
 254          * To switch channels clear any pending DMA operations;
 255          * wait long enough for the RX fifo to drain, reset the
 256          * hardware at the new frequency, and then re-enable
 257          * the relevant bits of the h/w.
 258          */
 259         ath9k_hw_set_interrupts(ah, 0);
 260         ath_drain_all_txq(sc, false);
 261         stopped = ath_stoprecv(sc);
 262
 263         /* XXX: do not flush receive queue here. We don't want
 264          * to flush data frames already in queue because of
 265          * changing channel. */
 266
 267         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 268                 fastcc = false;
 269
 270         DPRINTF(sc, ATH_DBG_CONFIG,
 271                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 272                 sc->sc_ah->ah_curchan->channel,
 273                 channel->center_freq, sc->tx_chan_width);
 274
 275         spin_lock_bh(&sc->sc_resetlock);
 276
 277         r = ath9k_hw_reset(ah, hchan, fastcc);
 278         if (r) {
 279                 DPRINTF(sc, ATH_DBG_FATAL,
 280                         "Unable to reset channel (%u Mhz) "
 281                         "reset status %u\n",
 282                         channel->center_freq, r);
 283                 spin_unlock_bh(&sc->sc_resetlock);
 284                 return r;
 285         }
 286         spin_unlock_bh(&sc->sc_resetlock);
 287
 288         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 289         sc->sc_flags &= ~SC_OP_FULL_RESET;
 290
 291         if (ath_startrecv(sc) != 0) {
 292                 DPRINTF(sc, ATH_DBG_FATAL,
 293                         "Unable to restart recv logic\n");
 294                 return -EIO;
 295         }
 296
 297         ath_cache_conf_rate(sc, &hw->conf);
 298         ath_update_txpow(sc);
 299         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 300         ath9k_ps_restore(sc);
 301         return 0;
 302 }
 303
 304 /*
 305  *  This routine performs the periodic noise floor calibration function
 306  *  that is used to adjust and optimize the chip performance.  This
 307  *  takes environmental changes (location, temperature) into account.
 308  *  When the task is complete, it reschedules itself depending on the
 309  *  appropriate interval that was calculated.
 310  */
 311 static void ath_ani_calibrate(unsigned long data)
 312 {
 313         struct ath_softc *sc;
 314         struct ath_hal *ah;
 315         bool longcal = false;
 316         bool shortcal = false;
 317         bool aniflag = false;
 318         unsigned int timestamp = jiffies_to_msecs(jiffies);
 319         u32 cal_interval;
 320
 321         sc = (struct ath_softc *)data;
 322         ah = sc->sc_ah;
 323
 324         /*
 325         * don't calibrate when we're scanning.
 326         * we are most likely not on our home channel.
 327         */
 328         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 329                 return;
 330
 331         /* Long calibration runs independently of short calibration. */
 332         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 333                 longcal = true;
 334                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 335                 sc->sc_ani.sc_longcal_timer = timestamp;
 336         }
 337
 338         /* Short calibration applies only while sc_caldone is false */
 339         if (!sc->sc_ani.sc_caldone) {
 340                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 341                     ATH_SHORT_CALINTERVAL) {
 342                         shortcal = true;
 343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 344                         sc->sc_ani.sc_shortcal_timer = timestamp;
 345                         sc->sc_ani.sc_resetcal_timer = timestamp;
 346                 }
 347         } else {
 348                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 349                     ATH_RESTART_CALINTERVAL) {
 350                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 351                         if (sc->sc_ani.sc_caldone)
 352                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 353                 }
 354         }
 355
 356         /* Verify whether we must check ANI */
 357         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 358            ATH_ANI_POLLINTERVAL) {
 359                 aniflag = true;
 360                 sc->sc_ani.sc_checkani_timer = timestamp;
 361         }
 362
 363         /* Skip all processing if there's nothing to do. */
 364         if (longcal || shortcal || aniflag) {
 365                 /* Call ANI routine if necessary */
 366                 if (aniflag)
 367                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 368                                              ah->ah_curchan);
 369
 370                 /* Perform calibration if necessary */
 371                 if (longcal || shortcal) {
 372                         bool iscaldone = false;
 373
 374                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 375                                                sc->sc_rx_chainmask, longcal,
 376                                                &iscaldone)) {
 377                                 if (longcal)
 378                                         sc->sc_ani.sc_noise_floor =
 379                                                 ath9k_hw_getchan_noise(ah,
 380                                                                ah->ah_curchan);
 381
 382                                 DPRINTF(sc, ATH_DBG_ANI,
 383                                         "calibrate chan %u/%x nf: %d\n",
 384                                         ah->ah_curchan->channel,
 385                                         ah->ah_curchan->channelFlags,
 386                                         sc->sc_ani.sc_noise_floor);
 387                         } else {
 388                                 DPRINTF(sc, ATH_DBG_ANY,
 389                                         "calibrate chan %u/%x failed\n",
 390                                         ah->ah_curchan->channel,
 391                                         ah->ah_curchan->channelFlags);
 392                         }
 393                         sc->sc_ani.sc_caldone = iscaldone;
 394                 }
 395         }
 396
 397         /*
 398         * Set timer interval based on previous results.
 399         * The interval must be the shortest necessary to satisfy ANI,
 400         * short calibration and long calibration.
 401         */
 402         cal_interval = ATH_LONG_CALINTERVAL;
 403         if (sc->sc_ah->ah_config.enable_ani)
 404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 405         if (!sc->sc_ani.sc_caldone)
 406                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 407
 408         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 409 }
 410
 411 /*
 412  * Update tx/rx chainmask. For legacy association,
 413  * hard code chainmask to 1x1, for 11n association, use
 414  * the chainmask configuration, for bt coexistence, use
 415  * the chainmask configuration even in legacy mode.
 416  */
 417 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 418 {
 419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 420         if (is_ht ||
 421             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 422                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 423                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 424         } else {
 425                 sc->sc_tx_chainmask = 1;
 426                 sc->sc_rx_chainmask = 1;
 427         }
 428
 429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 430                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 431 }
 432
 433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 434 {
 435         struct ath_node *an;
 436
 437         an = (struct ath_node *)sta->drv_priv;
 438
 439         if (sc->sc_flags & SC_OP_TXAGGR)
 440                 ath_tx_node_init(sc, an);
 441
 442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 443                              sta->ht_cap.ampdu_factor);
 444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 445 }
 446
 447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 448 {
 449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 450
 451         if (sc->sc_flags & SC_OP_TXAGGR)
 452                 ath_tx_node_cleanup(sc, an);
 453 }
 454
 455 static void ath9k_tasklet(unsigned long data)
 456 {
 457         struct ath_softc *sc = (struct ath_softc *)data;
 458         u32 status = sc->sc_intrstatus;
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 /* need a chip reset */
 462                 ath_reset(sc, false);
 463                 return;
 464         } else {
 465
 466                 if (status &
 467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 468                         spin_lock_bh(&sc->rx.rxflushlock);
 469                         ath_rx_tasklet(sc, 0);
 470                         spin_unlock_bh(&sc->rx.rxflushlock);
 471                 }
 472                 /* XXX: optimize this */
 473                 if (status & ATH9K_INT_TX)
 474                         ath_tx_tasklet(sc);
 475         }
 476
 477         /* re-enable hardware interrupt */
 478         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 479 }
 480
 481 irqreturn_t ath_isr(int irq, void *dev)
 482 {
 483         struct ath_softc *sc = dev;
 484         struct ath_hal *ah = sc->sc_ah;
 485         enum ath9k_int status;
 486         bool sched = false;
 487
 488         do {
 489                 if (sc->sc_flags & SC_OP_INVALID) {
 490                         /*
 491                          * The hardware is not ready/present, don't
 492                          * touch anything. Note this can happen early
 493                          * on if the IRQ is shared.
 494                          */
 495                         return IRQ_NONE;
 496                 }
 497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 498                         return IRQ_NONE;
 499                 }
 500
 501                 /*
 502                  * Figure out the reason(s) for the interrupt.  Note
 503                  * that the hal returns a pseudo-ISR that may include
 504                  * bits we haven't explicitly enabled so we mask the
 505                  * value to insure we only process bits we requested.
 506                  */
 507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 508
 509                 status &= sc->sc_imask; /* discard unasked-for bits */
 510
 511                 /*
 512                  * If there are no status bits set, then this interrupt was not
 513                  * for me (should have been caught above).
 514                  */
 515                 if (!status)
 516                         return IRQ_NONE;
 517
 518                 sc->sc_intrstatus = status;
 519
 520                 if (status & ATH9K_INT_FATAL) {
 521                         /* need a chip reset */
 522                         sched = true;
 523                 } else if (status & ATH9K_INT_RXORN) {
 524                         /* need a chip reset */
 525                         sched = true;
 526                 } else {
 527                         if (status & ATH9K_INT_SWBA) {
 528                                 /* schedule a tasklet for beacon handling */
 529                                 tasklet_schedule(&sc->bcon_tasklet);
 530                         }
 531                         if (status & ATH9K_INT_RXEOL) {
 532                                 /*
 533                                  * NB: the hardware should re-read the link when
 534                                  *     RXE bit is written, but it doesn't work
 535                                  *     at least on older hardware revs.
 536                                  */
 537                                 sched = true;
 538                         }
 539
 540                         if (status & ATH9K_INT_TXURN)
 541                                 /* bump tx trigger level */
 542                                 ath9k_hw_updatetxtriglevel(ah, true);
 543                         /* XXX: optimize this */
 544                         if (status & ATH9K_INT_RX)
 545                                 sched = true;
 546                         if (status & ATH9K_INT_TX)
 547                                 sched = true;
 548                         if (status & ATH9K_INT_BMISS)
 549                                 sched = true;
 550                         /* carrier sense timeout */
 551                         if (status & ATH9K_INT_CST)
 552                                 sched = true;
 553                         if (status & ATH9K_INT_MIB) {
 554                                 /*
 555                                  * Disable interrupts until we service the MIB
 556                                  * interrupt; otherwise it will continue to
 557                                  * fire.
 558                                  */
 559                                 ath9k_hw_set_interrupts(ah, 0);
 560                                 /*
 561                                  * Let the hal handle the event. We assume
 562                                  * it will clear whatever condition caused
 563                                  * the interrupt.
 564                                  */
 565                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 566                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 567                         }
 568                         if (status & ATH9K_INT_TIM_TIMER) {
 569                                 if (!(ah->ah_caps.hw_caps &
 570                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 571                                         /* Clear RxAbort bit so that we can
 572                                          * receive frames */
 573                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 574                                         ath9k_hw_setrxabort(ah, 0);
 575                                         sched = true;
 576                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 577                                 }
 578                         }
 579                 }
 580         } while (0);
 581
 582         ath_debug_stat_interrupt(sc, status);
 583
 584         if (sched) {
 585                 /* turn off every interrupt except SWBA */
 586                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 587                 tasklet_schedule(&sc->intr_tq);
 588         }
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 static u32 ath_get_extchanmode(struct ath_softc *sc,
 594                                struct ieee80211_channel *chan,
 595                                enum nl80211_channel_type channel_type)
 596 {
 597         u32 chanmode = 0;
 598
 599         switch (chan->band) {
 600         case IEEE80211_BAND_2GHZ:
 601                 switch(channel_type) {
 602                 case NL80211_CHAN_NO_HT:
 603                 case NL80211_CHAN_HT20:
 604                         chanmode = CHANNEL_G_HT20;
 605                         break;
 606                 case NL80211_CHAN_HT40PLUS:
 607                         chanmode = CHANNEL_G_HT40PLUS;
 608                         break;
 609                 case NL80211_CHAN_HT40MINUS:
 610                         chanmode = CHANNEL_G_HT40MINUS;
 611                         break;
 612                 }
 613                 break;
 614         case IEEE80211_BAND_5GHZ:
 615                 switch(channel_type) {
 616                 case NL80211_CHAN_NO_HT:
 617                 case NL80211_CHAN_HT20:
 618                         chanmode = CHANNEL_A_HT20;
 619                         break;
 620                 case NL80211_CHAN_HT40PLUS:
 621                         chanmode = CHANNEL_A_HT40PLUS;
 622                         break;
 623                 case NL80211_CHAN_HT40MINUS:
 624                         chanmode = CHANNEL_A_HT40MINUS;
 625                         break;
 626                 }
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         return chanmode;
 633 }
 634
 635 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 636                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 637 {
 638         bool status;
 639
 640         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 641                 keyix, hk, mac, false);
 642
 643         return status != false;
 644 }
 645
 646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 647                            struct ath9k_keyval *hk,
 648                            const u8 *addr)
 649 {
 650         const u8 *key_rxmic;
 651         const u8 *key_txmic;
 652
 653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 655
 656         if (addr == NULL) {
 657                 /* Group key installation */
 658                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 659                 return ath_keyset(sc, keyix, hk, addr);
 660         }
 661         if (!sc->sc_splitmic) {
 662                 /*
 663                  * data key goes at first index,
 664                  * the hal handles the MIC keys at index+64.
 665                  */
 666                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 668                 return ath_keyset(sc, keyix, hk, addr);
 669         }
 670         /*
 671          * TX key goes at first index, RX key at +32.
 672          * The hal handles the MIC keys at index+64.
 673          */
 674         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 675         if (!ath_keyset(sc, keyix, hk, NULL)) {
 676                 /* Txmic entry failed. No need to proceed further */
 677                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 678                         "Setting TX MIC Key Failed\n");
 679                 return 0;
 680         }
 681
 682         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 683         /* XXX delete tx key on failure? */
 684         return ath_keyset(sc, keyix + 32, hk, addr);
 685 }
 686
 687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 688 {
 689         int i;
 690
 691         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 692                 if (test_bit(i, sc->sc_keymap) ||
 693                     test_bit(i + 64, sc->sc_keymap))
 694                         continue; /* At least one part of TKIP key allocated */
 695                 if (sc->sc_splitmic &&
 696                     (test_bit(i + 32, sc->sc_keymap) ||
 697                      test_bit(i + 64 + 32, sc->sc_keymap)))
 698                         continue; /* At least one part of TKIP key allocated */
 699
 700                 /* Found a free slot for a TKIP key */
 701                 return i;
 702         }
 703         return -1;
 704 }
 705
 706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 707 {
 708         int i;
 709
 710         /* First, try to find slots that would not be available for TKIP. */
 711         if (sc->sc_splitmic) {
 712                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 713                         if (!test_bit(i, sc->sc_keymap) &&
 714                             (test_bit(i + 32, sc->sc_keymap) ||
 715                              test_bit(i + 64, sc->sc_keymap) ||
 716                              test_bit(i + 64 + 32, sc->sc_keymap)))
 717                                 return i;
 718                         if (!test_bit(i + 32, sc->sc_keymap) &&
 719                             (test_bit(i, sc->sc_keymap) ||
 720                              test_bit(i + 64, sc->sc_keymap) ||
 721                              test_bit(i + 64 + 32, sc->sc_keymap)))
 722                                 return i + 32;
 723                         if (!test_bit(i + 64, sc->sc_keymap) &&
 724                             (test_bit(i , sc->sc_keymap) ||
 725                              test_bit(i + 32, sc->sc_keymap) ||
 726                              test_bit(i + 64 + 32, sc->sc_keymap)))
 727                                 return i + 64;
 728                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 729                             (test_bit(i, sc->sc_keymap) ||
 730                              test_bit(i + 32, sc->sc_keymap) ||
 731                              test_bit(i + 64, sc->sc_keymap)))
 732                                 return i + 64 + 32;
 733                 }
 734         } else {
 735                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 736                         if (!test_bit(i, sc->sc_keymap) &&
 737                             test_bit(i + 64, sc->sc_keymap))
 738                                 return i;
 739                         if (test_bit(i, sc->sc_keymap) &&
 740                             !test_bit(i + 64, sc->sc_keymap))
 741                                 return i + 64;
 742                 }
 743         }
 744
 745         /* No partially used TKIP slots, pick any available slot */
 746         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 747                 /* Do not allow slots that could be needed for TKIP group keys
 748                  * to be used. This limitation could be removed if we know that
 749                  * TKIP will not be used. */
 750                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 751                         continue;
 752                 if (sc->sc_splitmic) {
 753                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 754                                 continue;
 755                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                 }
 758
 759                 if (!test_bit(i, sc->sc_keymap))
 760                         return i; /* Found a free slot for a key */
 761         }
 762
 763         /* No free slot found */
 764         return -1;
 765 }
 766
 767 static int ath_key_config(struct ath_softc *sc,
 768                           struct ieee80211_sta *sta,
 769                           struct ieee80211_key_conf *key)
 770 {
 771         struct ath9k_keyval hk;
 772         const u8 *mac = NULL;
 773         int ret = 0;
 774         int idx;
 775
 776         memset(&hk, 0, sizeof(hk));
 777
 778         switch (key->alg) {
 779         case ALG_WEP:
 780                 hk.kv_type = ATH9K_CIPHER_WEP;
 781                 break;
 782         case ALG_TKIP:
 783                 hk.kv_type = ATH9K_CIPHER_TKIP;
 784                 break;
 785         case ALG_CCMP:
 786                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 787                 break;
 788         default:
 789                 return -EOPNOTSUPP;
 790         }
 791
 792         hk.kv_len = key->keylen;
 793         memcpy(hk.kv_val, key->key, key->keylen);
 794
 795         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 796                 /* For now, use the default keys for broadcast keys. This may
 797                  * need to change with virtual interfaces. */
 798                 idx = key->keyidx;
 799         } else if (key->keyidx) {
 800                 struct ieee80211_vif *vif;
 801
 802                 if (WARN_ON(!sta))
 803                         return -EOPNOTSUPP;
 804                 mac = sta->addr;
 805
 806                 vif = sc->sc_vaps[0];
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 828         else
 829                 ret = ath_keyset(sc, idx, &hk, mac);
 830
 831         if (!ret)
 832                 return -EIO;
 833
 834         set_bit(idx, sc->sc_keymap);
 835         if (key->alg == ALG_TKIP) {
 836                 set_bit(idx + 64, sc->sc_keymap);
 837                 if (sc->sc_splitmic) {
 838                         set_bit(idx + 32, sc->sc_keymap);
 839                         set_bit(idx + 64 + 32, sc->sc_keymap);
 840                 }
 841         }
 842
 843         return idx;
 844 }
 845
 846 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 847 {
 848         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 849         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 850                 return;
 851
 852         clear_bit(key->hw_key_idx, sc->sc_keymap);
 853         if (key->alg != ALG_TKIP)
 854                 return;
 855
 856         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 857         if (sc->sc_splitmic) {
 858                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 859                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 860         }
 861 }
 862
 863 static void setup_ht_cap(struct ath_softc *sc,
 864                          struct ieee80211_sta_ht_cap *ht_info)
 865 {
 866 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 867 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 868
 869         ht_info->ht_supported = true;
 870         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 871                        IEEE80211_HT_CAP_SM_PS |
 872                        IEEE80211_HT_CAP_SGI_40 |
 873                        IEEE80211_HT_CAP_DSSSCCK40;
 874
 875         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 876         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 877
 878         /* set up supported mcs set */
 879         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 880
 881         switch(sc->sc_rx_chainmask) {
 882         case 1:
 883                 ht_info->mcs.rx_mask[0] = 0xff;
 884                 break;
 885         case 3:
 886         case 5:
 887         case 7:
 888         default:
 889                 ht_info->mcs.rx_mask[0] = 0xff;
 890                 ht_info->mcs.rx_mask[1] = 0xff;
 891                 break;
 892         }
 893
 894         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 895 }
 896
 897 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 898                                  struct ieee80211_vif *vif,
 899                                  struct ieee80211_bss_conf *bss_conf)
 900 {
 901         struct ath_vap *avp = (void *)vif->drv_priv;
 902
 903         if (bss_conf->assoc) {
 904                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 905                         bss_conf->aid, sc->sc_curbssid);
 906
 907                 /* New association, store aid */
 908                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 909                         sc->sc_curaid = bss_conf->aid;
 910                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 911                                                sc->sc_curaid);
 912                 }
 913
 914                 /* Configure the beacon */
 915                 ath_beacon_config(sc, 0);
 916                 sc->sc_flags |= SC_OP_BEACONS;
 917
 918                 /* Reset rssi stats */
 919                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 922                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 923
 924                 /* Start ANI */
 925                 mod_timer(&sc->sc_ani.timer,
 926                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 927
 928         } else {
 929                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 930                 sc->sc_curaid = 0;
 931         }
 932 }
 933
 934 /********************************/
 935 /*       LED functions          */
 936 /********************************/
 937
 938 static void ath_led_blink_work(struct work_struct *work)
 939 {
 940         struct ath_softc *sc = container_of(work, struct ath_softc,
 941                                             ath_led_blink_work.work);
 942
 943         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 944                 return;
 945         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 946                           (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 947
 948         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 949                            (sc->sc_flags & SC_OP_LED_ON) ?
 950                            msecs_to_jiffies(sc->led_off_duration) :
 951                            msecs_to_jiffies(sc->led_on_duration));
 952
 953         sc->led_on_duration =
 954                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
 955         sc->led_off_duration =
 956                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
 957         sc->led_on_cnt = sc->led_off_cnt = 0;
 958         if (sc->sc_flags & SC_OP_LED_ON)
 959                 sc->sc_flags &= ~SC_OP_LED_ON;
 960         else
 961                 sc->sc_flags |= SC_OP_LED_ON;
 962 }
 963
 964 static void ath_led_brightness(struct led_classdev *led_cdev,
 965                                enum led_brightness brightness)
 966 {
 967         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 968         struct ath_softc *sc = led->sc;
 969
 970         switch (brightness) {
 971         case LED_OFF:
 972                 if (led->led_type == ATH_LED_ASSOC ||
 973                     led->led_type == ATH_LED_RADIO) {
 974                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 975                                 (led->led_type == ATH_LED_RADIO));
 976                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 977                         if (led->led_type == ATH_LED_RADIO)
 978                                 sc->sc_flags &= ~SC_OP_LED_ON;
 979                 } else {
 980                         sc->led_off_cnt++;
 981                 }
 982                 break;
 983         case LED_FULL:
 984                 if (led->led_type == ATH_LED_ASSOC) {
 985                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 986                         queue_delayed_work(sc->hw->workqueue,
 987                                            &sc->ath_led_blink_work, 0);
 988                 } else if (led->led_type == ATH_LED_RADIO) {
 989                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 990                         sc->sc_flags |= SC_OP_LED_ON;
 991                 } else {
 992                         sc->led_on_cnt++;
 993                 }
 994                 break;
 995         default:
 996                 break;
 997         }
 998 }
 999
1000 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1001                             char *trigger)
1002 {
1003         int ret;
1004
1005         led->sc = sc;
1006         led->led_cdev.name = led->name;
1007         led->led_cdev.default_trigger = trigger;
1008         led->led_cdev.brightness_set = ath_led_brightness;
1009
1010         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1011         if (ret)
1012                 DPRINTF(sc, ATH_DBG_FATAL,
1013                         "Failed to register led:%s", led->name);
1014         else
1015                 led->registered = 1;
1016         return ret;
1017 }
1018
1019 static void ath_unregister_led(struct ath_led *led)
1020 {
1021         if (led->registered) {
1022                 led_classdev_unregister(&led->led_cdev);
1023                 led->registered = 0;
1024         }
1025 }
1026
1027 static void ath_deinit_leds(struct ath_softc *sc)
1028 {
1029         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1030         ath_unregister_led(&sc->assoc_led);
1031         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1032         ath_unregister_led(&sc->tx_led);
1033         ath_unregister_led(&sc->rx_led);
1034         ath_unregister_led(&sc->radio_led);
1035         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1036 }
1037
1038 static void ath_init_leds(struct ath_softc *sc)
1039 {
1040         char *trigger;
1041         int ret;
1042
1043         /* Configure gpio 1 for output */
1044         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1045                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1046         /* LED off, active low */
1047         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1048
1049         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1050
1051         trigger = ieee80211_get_radio_led_name(sc->hw);
1052         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1053                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1054         ret = ath_register_led(sc, &sc->radio_led, trigger);
1055         sc->radio_led.led_type = ATH_LED_RADIO;
1056         if (ret)
1057                 goto fail;
1058
1059         trigger = ieee80211_get_assoc_led_name(sc->hw);
1060         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1061                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1062         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1063         sc->assoc_led.led_type = ATH_LED_ASSOC;
1064         if (ret)
1065                 goto fail;
1066
1067         trigger = ieee80211_get_tx_led_name(sc->hw);
1068         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1069                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1070         ret = ath_register_led(sc, &sc->tx_led, trigger);
1071         sc->tx_led.led_type = ATH_LED_TX;
1072         if (ret)
1073                 goto fail;
1074
1075         trigger = ieee80211_get_rx_led_name(sc->hw);
1076         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1077                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1078         ret = ath_register_led(sc, &sc->rx_led, trigger);
1079         sc->rx_led.led_type = ATH_LED_RX;
1080         if (ret)
1081                 goto fail;
1082
1083         return;
1084
1085 fail:
1086         ath_deinit_leds(sc);
1087 }
1088
1089 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1090
1091 /*******************/
1092 /*      Rfkill     */
1093 /*******************/
1094
1095 static void ath_radio_enable(struct ath_softc *sc)
1096 {
1097         struct ath_hal *ah = sc->sc_ah;
1098         struct ieee80211_channel *channel = sc->hw->conf.channel;
1099         int r;
1100
1101         ath9k_ps_wakeup(sc);
1102         spin_lock_bh(&sc->sc_resetlock);
1103
1104         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1105
1106         if (r) {
1107                 DPRINTF(sc, ATH_DBG_FATAL,
1108                         "Unable to reset channel %u (%uMhz) ",
1109                         "reset status %u\n",
1110                         channel->center_freq, r);
1111         }
1112         spin_unlock_bh(&sc->sc_resetlock);
1113
1114         ath_update_txpow(sc);
1115         if (ath_startrecv(sc) != 0) {
1116                 DPRINTF(sc, ATH_DBG_FATAL,
1117                         "Unable to restart recv logic\n");
1118                 return;
1119         }
1120
1121         if (sc->sc_flags & SC_OP_BEACONS)
1122                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1123
1124         /* Re-Enable  interrupts */
1125         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1126
1127         /* Enable LED */
1128         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1129                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1130         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1131
1132         ieee80211_wake_queues(sc->hw);
1133         ath9k_ps_restore(sc);
1134 }
1135
1136 static void ath_radio_disable(struct ath_softc *sc)
1137 {
1138         struct ath_hal *ah = sc->sc_ah;
1139         struct ieee80211_channel *channel = sc->hw->conf.channel;
1140         int r;
1141
1142         ath9k_ps_wakeup(sc);
1143         ieee80211_stop_queues(sc->hw);
1144
1145         /* Disable LED */
1146         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1147         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1148
1149         /* Disable interrupts */
1150         ath9k_hw_set_interrupts(ah, 0);
1151
1152         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1153         ath_stoprecv(sc);               /* turn off frame recv */
1154         ath_flushrecv(sc);              /* flush recv queue */
1155
1156         spin_lock_bh(&sc->sc_resetlock);
1157         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1158         if (r) {
1159                 DPRINTF(sc, ATH_DBG_FATAL,
1160                         "Unable to reset channel %u (%uMhz) "
1161                         "reset status %u\n",
1162                         channel->center_freq, r);
1163         }
1164         spin_unlock_bh(&sc->sc_resetlock);
1165
1166         ath9k_hw_phy_disable(ah);
1167         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1168         ath9k_ps_restore(sc);
1169 }
1170
1171 static bool ath_is_rfkill_set(struct ath_softc *sc)
1172 {
1173         struct ath_hal *ah = sc->sc_ah;
1174
1175         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1176                                   ah->ah_rfkill_polarity;
1177 }
1178
1179 /* h/w rfkill poll function */
1180 static void ath_rfkill_poll(struct work_struct *work)
1181 {
1182         struct ath_softc *sc = container_of(work, struct ath_softc,
1183                                             rf_kill.rfkill_poll.work);
1184         bool radio_on;
1185
1186         if (sc->sc_flags & SC_OP_INVALID)
1187                 return;
1188
1189         radio_on = !ath_is_rfkill_set(sc);
1190
1191         /*
1192          * enable/disable radio only when there is a
1193          * state change in RF switch
1194          */
1195         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1196                 enum rfkill_state state;
1197
1198                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1199                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1200                                 : RFKILL_STATE_HARD_BLOCKED;
1201                 } else if (radio_on) {
1202                         ath_radio_enable(sc);
1203                         state = RFKILL_STATE_UNBLOCKED;
1204                 } else {
1205                         ath_radio_disable(sc);
1206                         state = RFKILL_STATE_HARD_BLOCKED;
1207                 }
1208
1209                 if (state == RFKILL_STATE_HARD_BLOCKED)
1210                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1211                 else
1212                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1213
1214                 rfkill_force_state(sc->rf_kill.rfkill, state);
1215         }
1216
1217         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1218                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1219 }
1220
1221 /* s/w rfkill handler */
1222 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1223 {
1224         struct ath_softc *sc = data;
1225
1226         switch (state) {
1227         case RFKILL_STATE_SOFT_BLOCKED:
1228                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1229                     SC_OP_RFKILL_SW_BLOCKED)))
1230                         ath_radio_disable(sc);
1231                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1232                 return 0;
1233         case RFKILL_STATE_UNBLOCKED:
1234                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1235                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1236                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1237                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1238                                         "radio as it is disabled by h/w\n");
1239                                 return -EPERM;
1240                         }
1241                         ath_radio_enable(sc);
1242                 }
1243                 return 0;
1244         default:
1245                 return -EINVAL;
1246         }
1247 }
1248
1249 /* Init s/w rfkill */
1250 static int ath_init_sw_rfkill(struct ath_softc *sc)
1251 {
1252         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1253                                              RFKILL_TYPE_WLAN);
1254         if (!sc->rf_kill.rfkill) {
1255                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1256                 return -ENOMEM;
1257         }
1258
1259         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1260                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1261         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1262         sc->rf_kill.rfkill->data = sc;
1263         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1264         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1265         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1266
1267         return 0;
1268 }
1269
1270 /* Deinitialize rfkill */
1271 static void ath_deinit_rfkill(struct ath_softc *sc)
1272 {
1273         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1274                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1275
1276         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1277                 rfkill_unregister(sc->rf_kill.rfkill);
1278                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1279                 sc->rf_kill.rfkill = NULL;
1280         }
1281 }
1282
1283 static int ath_start_rfkill_poll(struct ath_softc *sc)
1284 {
1285         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1286                 queue_delayed_work(sc->hw->workqueue,
1287                                    &sc->rf_kill.rfkill_poll, 0);
1288
1289         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1290                 if (rfkill_register(sc->rf_kill.rfkill)) {
1291                         DPRINTF(sc, ATH_DBG_FATAL,
1292                                 "Unable to register rfkill\n");
1293                         rfkill_free(sc->rf_kill.rfkill);
1294
1295                         /* Deinitialize the device */
1296                         ath_cleanup(sc);
1297                         return -EIO;
1298                 } else {
1299                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1300                 }
1301         }
1302
1303         return 0;
1304 }
1305 #endif /* CONFIG_RFKILL */
1306
1307 void ath_cleanup(struct ath_softc *sc)
1308 {
1309         ath_detach(sc);
1310         free_irq(sc->irq, sc);
1311         ath_bus_cleanup(sc);
1312         ieee80211_free_hw(sc->hw);
1313 }
1314
1315 void ath_detach(struct ath_softc *sc)
1316 {
1317         struct ieee80211_hw *hw = sc->hw;
1318         int i = 0;
1319
1320         ath9k_ps_wakeup(sc);
1321
1322         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1323
1324 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1325         ath_deinit_rfkill(sc);
1326 #endif
1327         ath_deinit_leds(sc);
1328
1329         ieee80211_unregister_hw(hw);
1330         ath_rx_cleanup(sc);
1331         ath_tx_cleanup(sc);
1332
1333         tasklet_kill(&sc->intr_tq);
1334         tasklet_kill(&sc->bcon_tasklet);
1335
1336         if (!(sc->sc_flags & SC_OP_INVALID))
1337                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1338
1339         /* cleanup tx queues */
1340         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1341                 if (ATH_TXQ_SETUP(sc, i))
1342                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1343
1344         ath9k_hw_detach(sc->sc_ah);
1345         ath9k_exit_debug(sc);
1346         ath9k_ps_restore(sc);
1347 }
1348
1349 static int ath_init(u16 devid, struct ath_softc *sc)
1350 {
1351         struct ath_hal *ah = NULL;
1352         int status;
1353         int error = 0, i;
1354         int csz = 0;
1355
1356         /* XXX: hardware will not be ready until ath_open() being called */
1357         sc->sc_flags |= SC_OP_INVALID;
1358
1359         if (ath9k_init_debug(sc) < 0)
1360                 printk(KERN_ERR "Unable to create debugfs files\n");
1361
1362         spin_lock_init(&sc->sc_resetlock);
1363         mutex_init(&sc->mutex);
1364         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1365         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1366                      (unsigned long)sc);
1367
1368         /*
1369          * Cache line size is used to size and align various
1370          * structures used to communicate with the hardware.
1371          */
1372         ath_read_cachesize(sc, &csz);
1373         /* XXX assert csz is non-zero */
1374         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1375
1376         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1377         if (ah == NULL) {
1378                 DPRINTF(sc, ATH_DBG_FATAL,
1379                         "Unable to attach hardware; HAL status %d\n", status);
1380                 error = -ENXIO;
1381                 goto bad;
1382         }
1383         sc->sc_ah = ah;
1384
1385         /* Get the hardware key cache size. */
1386         sc->sc_keymax = ah->ah_caps.keycache_size;
1387         if (sc->sc_keymax > ATH_KEYMAX) {
1388                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1389                         "Warning, using only %u entries in %u key cache\n",
1390                         ATH_KEYMAX, sc->sc_keymax);
1391                 sc->sc_keymax = ATH_KEYMAX;
1392         }
1393
1394         /*
1395          * Reset the key cache since some parts do not
1396          * reset the contents on initial power up.
1397          */
1398         for (i = 0; i < sc->sc_keymax; i++)
1399                 ath9k_hw_keyreset(ah, (u16) i);
1400
1401         if (ath9k_regd_init(sc->sc_ah))
1402                 goto bad;
1403
1404         /* default to MONITOR mode */
1405         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1406
1407         /* Setup rate tables */
1408
1409         ath_rate_attach(sc);
1410         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1411         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1412
1413         /*
1414          * Allocate hardware transmit queues: one queue for
1415          * beacon frames and one data queue for each QoS
1416          * priority.  Note that the hal handles reseting
1417          * these queues at the needed time.
1418          */
1419         sc->beacon.beaconq = ath_beaconq_setup(ah);
1420         if (sc->beacon.beaconq == -1) {
1421                 DPRINTF(sc, ATH_DBG_FATAL,
1422                         "Unable to setup a beacon xmit queue\n");
1423                 error = -EIO;
1424                 goto bad2;
1425         }
1426         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1427         if (sc->beacon.cabq == NULL) {
1428                 DPRINTF(sc, ATH_DBG_FATAL,
1429                         "Unable to setup CAB xmit queue\n");
1430                 error = -EIO;
1431                 goto bad2;
1432         }
1433
1434         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1435         ath_cabq_update(sc);
1436
1437         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1438                 sc->tx.hwq_map[i] = -1;
1439
1440         /* Setup data queues */
1441         /* NB: ensure BK queue is the lowest priority h/w queue */
1442         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1443                 DPRINTF(sc, ATH_DBG_FATAL,
1444                         "Unable to setup xmit queue for BK traffic\n");
1445                 error = -EIO;
1446                 goto bad2;
1447         }
1448
1449         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1450                 DPRINTF(sc, ATH_DBG_FATAL,
1451                         "Unable to setup xmit queue for BE traffic\n");
1452                 error = -EIO;
1453                 goto bad2;
1454         }
1455         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1456                 DPRINTF(sc, ATH_DBG_FATAL,
1457                         "Unable to setup xmit queue for VI traffic\n");
1458                 error = -EIO;
1459                 goto bad2;
1460         }
1461         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1462                 DPRINTF(sc, ATH_DBG_FATAL,
1463                         "Unable to setup xmit queue for VO traffic\n");
1464                 error = -EIO;
1465                 goto bad2;
1466         }
1467
1468         /* Initializes the noise floor to a reasonable default value.
1469          * Later on this will be updated during ANI processing. */
1470
1471         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1472         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1473
1474         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475                                    ATH9K_CIPHER_TKIP, NULL)) {
1476                 /*
1477                  * Whether we should enable h/w TKIP MIC.
1478                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1479                  * report WMM capable, so it's always safe to turn on
1480                  * TKIP MIC in this case.
1481                  */
1482                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1483                                        0, 1, NULL);
1484         }
1485
1486         /*
1487          * Check whether the separate key cache entries
1488          * are required to handle both tx+rx MIC keys.
1489          * With split mic keys the number of stations is limited
1490          * to 27 otherwise 59.
1491          */
1492         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493                                    ATH9K_CIPHER_TKIP, NULL)
1494             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1495                                       ATH9K_CIPHER_MIC, NULL)
1496             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1497                                       0, NULL))
1498                 sc->sc_splitmic = 1;
1499
1500         /* turn on mcast key search if possible */
1501         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1502                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1503                                              1, NULL);
1504
1505         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1506
1507         /* 11n Capabilities */
1508         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1509                 sc->sc_flags |= SC_OP_TXAGGR;
1510                 sc->sc_flags |= SC_OP_RXAGGR;
1511         }
1512
1513         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1514         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1515
1516         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1517         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1518
1519         ath9k_hw_getmac(ah, sc->sc_myaddr);
1520         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1521                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1522                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1523                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1524         }
1525
1526         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1527
1528         /* initialize beacon slots */
1529         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1530                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1531
1532         /* save MISC configurations */
1533         sc->sc_config.swBeaconProcess = 1;
1534
1535         /* setup channels and rates */
1536
1537         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1538         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1539                 sc->rates[IEEE80211_BAND_2GHZ];
1540         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1541         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1542                 ARRAY_SIZE(ath9k_2ghz_chantable);
1543
1544         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1545                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1546                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1547                         sc->rates[IEEE80211_BAND_5GHZ];
1548                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1549                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1550                         ARRAY_SIZE(ath9k_5ghz_chantable);
1551         }
1552
1553         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1554                 ath9k_hw_btcoex_enable(sc->sc_ah);
1555
1556         return 0;
1557 bad2:
1558         /* cleanup tx queues */
1559         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1560                 if (ATH_TXQ_SETUP(sc, i))
1561                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1562 bad:
1563         if (ah)
1564                 ath9k_hw_detach(ah);
1565
1566         return error;
1567 }
1568
1569 int ath_attach(u16 devid, struct ath_softc *sc)
1570 {
1571         struct ieee80211_hw *hw = sc->hw;
1572         int error = 0;
1573
1574         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1575
1576         error = ath_init(devid, sc);
1577         if (error != 0)
1578                 return error;
1579
1580         /* get mac address from hardware and set in mac80211 */
1581
1582         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1583
1584         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1585                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1586                 IEEE80211_HW_SIGNAL_DBM |
1587                 IEEE80211_HW_AMPDU_AGGREGATION |
1588                 IEEE80211_HW_SUPPORTS_PS |
1589                 IEEE80211_HW_PS_NULLFUNC_STACK;
1590
1591         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1592                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1593
1594         hw->wiphy->interface_modes =
1595                 BIT(NL80211_IFTYPE_AP) |
1596                 BIT(NL80211_IFTYPE_STATION) |
1597                 BIT(NL80211_IFTYPE_ADHOC);
1598
1599         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1600         hw->wiphy->strict_regulatory = true;
1601
1602         hw->queues = 4;
1603         hw->max_rates = 4;
1604         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1605         hw->sta_data_size = sizeof(struct ath_node);
1606         hw->vif_data_size = sizeof(struct ath_vap);
1607
1608         hw->rate_control_algorithm = "ath9k_rate_control";
1609
1610         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1611                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1612                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1613                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1614         }
1615
1616         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1617         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1618                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1619                         &sc->sbands[IEEE80211_BAND_5GHZ];
1620
1621         /* initialize tx/rx engine */
1622         error = ath_tx_init(sc, ATH_TXBUF);
1623         if (error != 0)
1624                 goto detach;
1625
1626         error = ath_rx_init(sc, ATH_RXBUF);
1627         if (error != 0)
1628                 goto detach;
1629
1630 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1631         /* Initialze h/w Rfkill */
1632         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1633                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1634
1635         /* Initialize s/w rfkill */
1636         if (ath_init_sw_rfkill(sc))
1637                 goto detach;
1638 #endif
1639
1640         if (ath9k_is_world_regd(sc->sc_ah)) {
1641                 /* Anything applied here (prior to wiphy registratoin) gets
1642                  * saved on the wiphy orig_* parameters */
1643                 const struct ieee80211_regdomain *regd =
1644                         ath9k_world_regdomain(sc->sc_ah);
1645                 hw->wiphy->custom_regulatory = true;
1646                 hw->wiphy->strict_regulatory = false;
1647                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1648                 ath9k_reg_apply_radar_flags(hw->wiphy);
1649                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1650         } else {
1651                 /* This gets applied in the case of the absense of CRDA,
1652                  * its our own custom world regulatory domain, similar to
1653                  * cfg80211's but we enable passive scanning */
1654                 const struct ieee80211_regdomain *regd =
1655                         ath9k_default_world_regdomain();
1656                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1657                 ath9k_reg_apply_radar_flags(hw->wiphy);
1658                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1659         }
1660
1661         error = ieee80211_register_hw(hw);
1662
1663         if (!ath9k_is_world_regd(sc->sc_ah))
1664                 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1665
1666         /* Initialize LED control */
1667         ath_init_leds(sc);
1668
1669
1670         return 0;
1671 detach:
1672         ath_detach(sc);
1673         return error;
1674 }
1675
1676 int ath_reset(struct ath_softc *sc, bool retry_tx)
1677 {
1678         struct ath_hal *ah = sc->sc_ah;
1679         struct ieee80211_hw *hw = sc->hw;
1680         int r;
1681
1682         ath9k_hw_set_interrupts(ah, 0);
1683         ath_drain_all_txq(sc, retry_tx);
1684         ath_stoprecv(sc);
1685         ath_flushrecv(sc);
1686
1687         spin_lock_bh(&sc->sc_resetlock);
1688         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1689         if (r)
1690                 DPRINTF(sc, ATH_DBG_FATAL,
1691                         "Unable to reset hardware; reset status %u\n", r);
1692         spin_unlock_bh(&sc->sc_resetlock);
1693
1694         if (ath_startrecv(sc) != 0)
1695                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1696
1697         /*
1698          * We may be doing a reset in response to a request
1699          * that changes the channel so update any state that
1700          * might change as a result.
1701          */
1702         ath_cache_conf_rate(sc, &hw->conf);
1703
1704         ath_update_txpow(sc);
1705
1706         if (sc->sc_flags & SC_OP_BEACONS)
1707                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1708
1709         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1710
1711         if (retry_tx) {
1712                 int i;
1713                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1714                         if (ATH_TXQ_SETUP(sc, i)) {
1715                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1716                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1717                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1718                         }
1719                 }
1720         }
1721
1722         return r;
1723 }
1724
1725 /*
1726  *  This function will allocate both the DMA descriptor structure, and the
1727  *  buffers it contains.  These are used to contain the descriptors used
1728  *  by the system.
1729 */
1730 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1731                       struct list_head *head, const char *name,
1732                       int nbuf, int ndesc)
1733 {
1734 #define DS2PHYS(_dd, _ds)                                               \
1735         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1736 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1737 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1738
1739         struct ath_desc *ds;
1740         struct ath_buf *bf;
1741         int i, bsize, error;
1742
1743         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1744                 name, nbuf, ndesc);
1745
1746         /* ath_desc must be a multiple of DWORDs */
1747         if ((sizeof(struct ath_desc) % 4) != 0) {
1748                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1749                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1750                 error = -ENOMEM;
1751                 goto fail;
1752         }
1753
1754         dd->dd_name = name;
1755         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1756
1757         /*
1758          * Need additional DMA memory because we can't use
1759          * descriptors that cross the 4K page boundary. Assume
1760          * one skipped descriptor per 4K page.
1761          */
1762         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1763                 u32 ndesc_skipped =
1764                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1765                 u32 dma_len;
1766
1767                 while (ndesc_skipped) {
1768                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1769                         dd->dd_desc_len += dma_len;
1770
1771                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1772                 };
1773         }
1774
1775         /* allocate descriptors */
1776         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1777                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1778         if (dd->dd_desc == NULL) {
1779                 error = -ENOMEM;
1780                 goto fail;
1781         }
1782         ds = dd->dd_desc;
1783         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1784                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1785                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1786
1787         /* allocate buffers */
1788         bsize = sizeof(struct ath_buf) * nbuf;
1789         bf = kmalloc(bsize, GFP_KERNEL);
1790         if (bf == NULL) {
1791                 error = -ENOMEM;
1792                 goto fail2;
1793         }
1794         memset(bf, 0, bsize);
1795         dd->dd_bufptr = bf;
1796
1797         INIT_LIST_HEAD(head);
1798         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1799                 bf->bf_desc = ds;
1800                 bf->bf_daddr = DS2PHYS(dd, ds);
1801
1802                 if (!(sc->sc_ah->ah_caps.hw_caps &
1803                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1804                         /*
1805                          * Skip descriptor addresses which can cause 4KB
1806                          * boundary crossing (addr + length) with a 32 dword
1807                          * descriptor fetch.
1808                          */
1809                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1810                                 ASSERT((caddr_t) bf->bf_desc <
1811                                        ((caddr_t) dd->dd_desc +
1812                                         dd->dd_desc_len));
1813
1814                                 ds += ndesc;
1815                                 bf->bf_desc = ds;
1816                                 bf->bf_daddr = DS2PHYS(dd, ds);
1817                         }
1818                 }
1819                 list_add_tail(&bf->list, head);
1820         }
1821         return 0;
1822 fail2:
1823         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1824                           dd->dd_desc_paddr);
1825 fail:
1826         memset(dd, 0, sizeof(*dd));
1827         return error;
1828 #undef ATH_DESC_4KB_BOUND_CHECK
1829 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1830 #undef DS2PHYS
1831 }
1832
1833 void ath_descdma_cleanup(struct ath_softc *sc,
1834                          struct ath_descdma *dd,
1835                          struct list_head *head)
1836 {
1837         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1838                           dd->dd_desc_paddr);
1839
1840         INIT_LIST_HEAD(head);
1841         kfree(dd->dd_bufptr);
1842         memset(dd, 0, sizeof(*dd));
1843 }
1844
1845 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1846 {
1847         int qnum;
1848
1849         switch (queue) {
1850         case 0:
1851                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1852                 break;
1853         case 1:
1854                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1855                 break;
1856         case 2:
1857                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1858                 break;
1859         case 3:
1860                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1861                 break;
1862         default:
1863                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1864                 break;
1865         }
1866
1867         return qnum;
1868 }
1869
1870 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1871 {
1872         int qnum;
1873
1874         switch (queue) {
1875         case ATH9K_WME_AC_VO:
1876                 qnum = 0;
1877                 break;
1878         case ATH9K_WME_AC_VI:
1879                 qnum = 1;
1880                 break;
1881         case ATH9K_WME_AC_BE:
1882                 qnum = 2;
1883                 break;
1884         case ATH9K_WME_AC_BK:
1885                 qnum = 3;
1886                 break;
1887         default:
1888                 qnum = -1;
1889                 break;
1890         }
1891
1892         return qnum;
1893 }
1894
1895 /* XXX: Remove me once we don't depend on ath9k_channel for all
1896  * this redundant data */
1897 static void ath9k_update_ichannel(struct ath_softc *sc,
1898                           struct ath9k_channel *ichan)
1899 {
1900         struct ieee80211_hw *hw = sc->hw;
1901         struct ieee80211_channel *chan = hw->conf.channel;
1902         struct ieee80211_conf *conf = &hw->conf;
1903
1904         ichan->channel = chan->center_freq;
1905         ichan->chan = chan;
1906
1907         if (chan->band == IEEE80211_BAND_2GHZ) {
1908                 ichan->chanmode = CHANNEL_G;
1909                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1910         } else {
1911                 ichan->chanmode = CHANNEL_A;
1912                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1913         }
1914
1915         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1916
1917         if (conf_is_ht(conf)) {
1918                 if (conf_is_ht40(conf))
1919                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1920
1921                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1922                                             conf->channel_type);
1923         }
1924 }
1925
1926 /**********************/
1927 /* mac80211 callbacks */
1928 /**********************/
1929
1930 static int ath9k_start(struct ieee80211_hw *hw)
1931 {
1932         struct ath_softc *sc = hw->priv;
1933         struct ieee80211_channel *curchan = hw->conf.channel;
1934         struct ath9k_channel *init_channel;
1935         int r, pos;
1936
1937         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1938                 "initial channel: %d MHz\n", curchan->center_freq);
1939
1940         mutex_lock(&sc->mutex);
1941
1942         /* setup initial channel */
1943
1944         pos = curchan->hw_value;
1945
1946         init_channel = &sc->sc_ah->ah_channels[pos];
1947         ath9k_update_ichannel(sc, init_channel);
1948
1949         /* Reset SERDES registers */
1950         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1951
1952         /*
1953          * The basic interface to setting the hardware in a good
1954          * state is ``reset''.  On return the hardware is known to
1955          * be powered up and with interrupts disabled.  This must
1956          * be followed by initialization of the appropriate bits
1957          * and then setup of the interrupt mask.
1958          */
1959         spin_lock_bh(&sc->sc_resetlock);
1960         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1961         if (r) {
1962                 DPRINTF(sc, ATH_DBG_FATAL,
1963                         "Unable to reset hardware; reset status %u "
1964                         "(freq %u MHz)\n", r,
1965                         curchan->center_freq);
1966                 spin_unlock_bh(&sc->sc_resetlock);
1967                 goto mutex_unlock;
1968         }
1969         spin_unlock_bh(&sc->sc_resetlock);
1970
1971         /*
1972          * This is needed only to setup initial state
1973          * but it's best done after a reset.
1974          */
1975         ath_update_txpow(sc);
1976
1977         /*
1978          * Setup the hardware after reset:
1979          * The receive engine is set going.
1980          * Frame transmit is handled entirely
1981          * in the frame output path; there's nothing to do
1982          * here except setup the interrupt mask.
1983          */
1984         if (ath_startrecv(sc) != 0) {
1985                 DPRINTF(sc, ATH_DBG_FATAL,
1986                         "Unable to start recv logic\n");
1987                 r = -EIO;
1988                 goto mutex_unlock;
1989         }
1990
1991         /* Setup our intr mask. */
1992         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1993                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1994                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1995
1996         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1997                 sc->sc_imask |= ATH9K_INT_GTT;
1998
1999         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
2000                 sc->sc_imask |= ATH9K_INT_CST;
2001
2002         ath_cache_conf_rate(sc, &hw->conf);
2003
2004         sc->sc_flags &= ~SC_OP_INVALID;
2005
2006         /* Disable BMISS interrupt when we're not associated */
2007         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2008         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2009
2010         ieee80211_wake_queues(sc->hw);
2011
2012 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2013         r = ath_start_rfkill_poll(sc);
2014 #endif
2015
2016 mutex_unlock:
2017         mutex_unlock(&sc->mutex);
2018
2019         return r;
2020 }
2021
2022 static int ath9k_tx(struct ieee80211_hw *hw,
2023                     struct sk_buff *skb)
2024 {
2025         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2026         struct ath_softc *sc = hw->priv;
2027         struct ath_tx_control txctl;
2028         int hdrlen, padsize;
2029
2030         memset(&txctl, 0, sizeof(struct ath_tx_control));
2031
2032         /*
2033          * As a temporary workaround, assign seq# here; this will likely need
2034          * to be cleaned up to work better with Beacon transmission and virtual
2035          * BSSes.
2036          */
2037         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2038                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2039                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2040                         sc->tx.seq_no += 0x10;
2041                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2042                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2043         }
2044
2045         /* Add the padding after the header if this is not already done */
2046         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2047         if (hdrlen & 3) {
2048                 padsize = hdrlen % 4;
2049                 if (skb_headroom(skb) < padsize)
2050                         return -1;
2051                 skb_push(skb, padsize);
2052                 memmove(skb->data, skb->data + padsize, hdrlen);
2053         }
2054
2055         /* Check if a tx queue is available */
2056
2057         txctl.txq = ath_test_get_txq(sc, skb);
2058         if (!txctl.txq)
2059                 goto exit;
2060
2061         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2062
2063         if (ath_tx_start(sc, skb, &txctl) != 0) {
2064                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2065                 goto exit;
2066         }
2067
2068         return 0;
2069 exit:
2070         dev_kfree_skb_any(skb);
2071         return 0;
2072 }
2073
2074 static void ath9k_stop(struct ieee80211_hw *hw)
2075 {
2076         struct ath_softc *sc = hw->priv;
2077
2078         if (sc->sc_flags & SC_OP_INVALID) {
2079                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2080                 return;
2081         }
2082
2083         mutex_lock(&sc->mutex);
2084
2085         ieee80211_stop_queues(sc->hw);
2086
2087         /* make sure h/w will not generate any interrupt
2088          * before setting the invalid flag. */
2089         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2090
2091         if (!(sc->sc_flags & SC_OP_INVALID)) {
2092                 ath_drain_all_txq(sc, false);
2093                 ath_stoprecv(sc);
2094                 ath9k_hw_phy_disable(sc->sc_ah);
2095         } else
2096                 sc->rx.rxlink = NULL;
2097
2098 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2099         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2100                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2101 #endif
2102         /* disable HAL and put h/w to sleep */
2103         ath9k_hw_disable(sc->sc_ah);
2104         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2105
2106         sc->sc_flags |= SC_OP_INVALID;
2107
2108         mutex_unlock(&sc->mutex);
2109
2110         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2111 }
2112
2113 static int ath9k_add_interface(struct ieee80211_hw *hw,
2114                                struct ieee80211_if_init_conf *conf)
2115 {
2116         struct ath_softc *sc = hw->priv;
2117         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2118         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2119
2120         /* Support only vap for now */
2121
2122         if (sc->sc_nvaps)
2123                 return -ENOBUFS;
2124
2125         mutex_lock(&sc->mutex);
2126
2127         switch (conf->type) {
2128         case NL80211_IFTYPE_STATION:
2129                 ic_opmode = NL80211_IFTYPE_STATION;
2130                 break;
2131         case NL80211_IFTYPE_ADHOC:
2132                 ic_opmode = NL80211_IFTYPE_ADHOC;
2133                 break;
2134         case NL80211_IFTYPE_AP:
2135                 ic_opmode = NL80211_IFTYPE_AP;
2136                 break;
2137         default:
2138                 DPRINTF(sc, ATH_DBG_FATAL,
2139                         "Interface type %d not yet supported\n", conf->type);
2140                 return -EOPNOTSUPP;
2141         }
2142
2143         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2144
2145         /* Set the VAP opmode */
2146         avp->av_opmode = ic_opmode;
2147         avp->av_bslot = -1;
2148
2149         if (ic_opmode == NL80211_IFTYPE_AP)
2150                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2151
2152         sc->sc_vaps[0] = conf->vif;
2153         sc->sc_nvaps++;
2154
2155         /* Set the device opmode */
2156         sc->sc_ah->ah_opmode = ic_opmode;
2157
2158         /*
2159          * Enable MIB interrupts when there are hardware phy counters.
2160          * Note we only do this (at the moment) for station mode.
2161          */
2162         if (ath9k_hw_phycounters(sc->sc_ah) &&
2163             ((conf->type == NL80211_IFTYPE_STATION) ||
2164              (conf->type == NL80211_IFTYPE_ADHOC)))
2165                 sc->sc_imask |= ATH9K_INT_MIB;
2166         /*
2167          * Some hardware processes the TIM IE and fires an
2168          * interrupt when the TIM bit is set.  For hardware
2169          * that does, if not overridden by configuration,
2170          * enable the TIM interrupt when operating as station.
2171          */
2172         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2173             (conf->type == NL80211_IFTYPE_STATION) &&
2174             !sc->sc_config.swBeaconProcess)
2175                 sc->sc_imask |= ATH9K_INT_TIM;
2176
2177         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2178
2179         if (conf->type == NL80211_IFTYPE_AP) {
2180                 /* TODO: is this a suitable place to start ANI for AP mode? */
2181                 /* Start ANI */
2182                 mod_timer(&sc->sc_ani.timer,
2183                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2184         }
2185
2186         mutex_unlock(&sc->mutex);
2187
2188         return 0;
2189 }
2190
2191 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2192                                    struct ieee80211_if_init_conf *conf)
2193 {
2194         struct ath_softc *sc = hw->priv;
2195         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2196
2197         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2198
2199         mutex_lock(&sc->mutex);
2200
2201         /* Stop ANI */
2202         del_timer_sync(&sc->sc_ani.timer);
2203
2204         /* Reclaim beacon resources */
2205         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2206             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2207                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2208                 ath_beacon_return(sc, avp);
2209         }
2210
2211         sc->sc_flags &= ~SC_OP_BEACONS;
2212
2213         sc->sc_vaps[0] = NULL;
2214         sc->sc_nvaps--;
2215
2216         mutex_unlock(&sc->mutex);
2217 }
2218
2219 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2220 {
2221         struct ath_softc *sc = hw->priv;
2222         struct ieee80211_conf *conf = &hw->conf;
2223
2224         mutex_lock(&sc->mutex);
2225
2226         if (changed & IEEE80211_CONF_CHANGE_PS) {
2227                 if (conf->flags & IEEE80211_CONF_PS) {
2228                         if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2229                                 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2230                                 ath9k_hw_set_interrupts(sc->sc_ah,
2231                                                 sc->sc_imask);
2232                         }
2233                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2234                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2235                 } else {
2236                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2237                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2238                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2239                         if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2240                                 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2241                                 ath9k_hw_set_interrupts(sc->sc_ah,
2242                                                 sc->sc_imask);
2243                         }
2244                 }
2245         }
2246
2247         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2248                 struct ieee80211_channel *curchan = hw->conf.channel;
2249                 int pos = curchan->hw_value;
2250
2251                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2252                         curchan->center_freq);
2253
2254                 /* XXX: remove me eventualy */
2255                 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2256
2257                 ath_update_chainmask(sc, conf_is_ht(conf));
2258
2259                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2260                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2261                         mutex_unlock(&sc->mutex);
2262                         return -EINVAL;
2263                 }
2264         }
2265
2266         if (changed & IEEE80211_CONF_CHANGE_POWER)
2267                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2268
2269         mutex_unlock(&sc->mutex);
2270
2271         return 0;
2272 }
2273
2274 static int ath9k_config_interface(struct ieee80211_hw *hw,
2275                                   struct ieee80211_vif *vif,
2276                                   struct ieee80211_if_conf *conf)
2277 {
2278         struct ath_softc *sc = hw->priv;
2279         struct ath_hal *ah = sc->sc_ah;
2280         struct ath_vap *avp = (void *)vif->drv_priv;
2281         u32 rfilt = 0;
2282         int error, i;
2283
2284         /* TODO: Need to decide which hw opmode to use for multi-interface
2285          * cases */
2286         if (vif->type == NL80211_IFTYPE_AP &&
2287             ah->ah_opmode != NL80211_IFTYPE_AP) {
2288                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2289                 ath9k_hw_setopmode(ah);
2290                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2291                 /* Request full reset to get hw opmode changed properly */
2292                 sc->sc_flags |= SC_OP_FULL_RESET;
2293         }
2294
2295         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2296             !is_zero_ether_addr(conf->bssid)) {
2297                 switch (vif->type) {
2298                 case NL80211_IFTYPE_STATION:
2299                 case NL80211_IFTYPE_ADHOC:
2300                         /* Set BSSID */
2301                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2302                         sc->sc_curaid = 0;
2303                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2304                                                sc->sc_curaid);
2305
2306                         /* Set aggregation protection mode parameters */
2307                         sc->sc_config.ath_aggr_prot = 0;
2308
2309                         DPRINTF(sc, ATH_DBG_CONFIG,
2310                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2311                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2312
2313                         /* need to reconfigure the beacon */
2314                         sc->sc_flags &= ~SC_OP_BEACONS ;
2315
2316                         break;
2317                 default:
2318                         break;
2319                 }
2320         }
2321
2322         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2323             (vif->type == NL80211_IFTYPE_AP)) {
2324                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2325                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2326                      conf->enable_beacon)) {
2327                         /*
2328                          * Allocate and setup the beacon frame.
2329                          *
2330                          * Stop any previous beacon DMA.  This may be
2331                          * necessary, for example, when an ibss merge
2332                          * causes reconfiguration; we may be called
2333                          * with beacon transmission active.
2334                          */
2335                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2336
2337                         error = ath_beacon_alloc(sc, 0);
2338                         if (error != 0)
2339                                 return error;
2340
2341                         ath_beacon_sync(sc, 0);
2342                 }
2343         }
2344
2345         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2346         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2347                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2348                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2349                                 ath9k_hw_keysetmac(sc->sc_ah,
2350                                                    (u16)i,
2351                                                    sc->sc_curbssid);
2352         }
2353
2354         /* Only legacy IBSS for now */
2355         if (vif->type == NL80211_IFTYPE_ADHOC)
2356                 ath_update_chainmask(sc, 0);
2357
2358         return 0;
2359 }
2360
2361 #define SUPPORTED_FILTERS                       \
2362         (FIF_PROMISC_IN_BSS |                   \
2363         FIF_ALLMULTI |                          \
2364         FIF_CONTROL |                           \
2365         FIF_OTHER_BSS |                         \
2366         FIF_BCN_PRBRESP_PROMISC |               \
2367         FIF_FCSFAIL)
2368
2369 /* FIXME: sc->sc_full_reset ? */
2370 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2371                                    unsigned int changed_flags,
2372                                    unsigned int *total_flags,
2373                                    int mc_count,
2374                                    struct dev_mc_list *mclist)
2375 {
2376         struct ath_softc *sc = hw->priv;
2377         u32 rfilt;
2378
2379         changed_flags &= SUPPORTED_FILTERS;
2380         *total_flags &= SUPPORTED_FILTERS;
2381
2382         sc->rx.rxfilter = *total_flags;
2383         rfilt = ath_calcrxfilter(sc);
2384         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2385
2386         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2387                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2388                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2389         }
2390
2391         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2392 }
2393
2394 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2395                              struct ieee80211_vif *vif,
2396                              enum sta_notify_cmd cmd,
2397                              struct ieee80211_sta *sta)
2398 {
2399         struct ath_softc *sc = hw->priv;
2400
2401         switch (cmd) {
2402         case STA_NOTIFY_ADD:
2403                 ath_node_attach(sc, sta);
2404                 break;
2405         case STA_NOTIFY_REMOVE:
2406                 ath_node_detach(sc, sta);
2407                 break;
2408         default:
2409                 break;
2410         }
2411 }
2412
2413 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2414                          const struct ieee80211_tx_queue_params *params)
2415 {
2416         struct ath_softc *sc = hw->priv;
2417         struct ath9k_tx_queue_info qi;
2418         int ret = 0, qnum;
2419
2420         if (queue >= WME_NUM_AC)
2421                 return 0;
2422
2423         mutex_lock(&sc->mutex);
2424
2425         qi.tqi_aifs = params->aifs;
2426         qi.tqi_cwmin = params->cw_min;
2427         qi.tqi_cwmax = params->cw_max;
2428         qi.tqi_burstTime = params->txop;
2429         qnum = ath_get_hal_qnum(queue, sc);
2430
2431         DPRINTF(sc, ATH_DBG_CONFIG,
2432                 "Configure tx [queue/halq] [%d/%d],  "
2433                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2434                 queue, qnum, params->aifs, params->cw_min,
2435                 params->cw_max, params->txop);
2436
2437         ret = ath_txq_update(sc, qnum, &qi);
2438         if (ret)
2439                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2440
2441         mutex_unlock(&sc->mutex);
2442
2443         return ret;
2444 }
2445
2446 static int ath9k_set_key(struct ieee80211_hw *hw,
2447                          enum set_key_cmd cmd,
2448                          struct ieee80211_vif *vif,
2449                          struct ieee80211_sta *sta,
2450                          struct ieee80211_key_conf *key)
2451 {
2452         struct ath_softc *sc = hw->priv;
2453         int ret = 0;
2454
2455         mutex_lock(&sc->mutex);
2456         ath9k_ps_wakeup(sc);
2457         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2458
2459         switch (cmd) {
2460         case SET_KEY:
2461                 ret = ath_key_config(sc, sta, key);
2462                 if (ret >= 0) {
2463                         key->hw_key_idx = ret;
2464                         /* push IV and Michael MIC generation to stack */
2465                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2466                         if (key->alg == ALG_TKIP)
2467                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2468                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2469                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2470                         ret = 0;
2471                 }
2472                 break;
2473         case DISABLE_KEY:
2474                 ath_key_delete(sc, key);
2475                 break;
2476         default:
2477                 ret = -EINVAL;
2478         }
2479
2480         ath9k_ps_restore(sc);
2481         mutex_unlock(&sc->mutex);
2482
2483         return ret;
2484 }
2485
2486 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2487                                    struct ieee80211_vif *vif,
2488                                    struct ieee80211_bss_conf *bss_conf,
2489                                    u32 changed)
2490 {
2491         struct ath_softc *sc = hw->priv;
2492
2493         mutex_lock(&sc->mutex);
2494
2495         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2496                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2497                         bss_conf->use_short_preamble);
2498                 if (bss_conf->use_short_preamble)
2499                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2500                 else
2501                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2502         }
2503
2504         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2505                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2506                         bss_conf->use_cts_prot);
2507                 if (bss_conf->use_cts_prot &&
2508                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2509                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2510                 else
2511                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2512         }
2513
2514         if (changed & BSS_CHANGED_ASSOC) {
2515                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2516                         bss_conf->assoc);
2517                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2518         }
2519
2520         mutex_unlock(&sc->mutex);
2521 }
2522
2523 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2524 {
2525         u64 tsf;
2526         struct ath_softc *sc = hw->priv;
2527
2528         mutex_lock(&sc->mutex);
2529         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2530         mutex_unlock(&sc->mutex);
2531
2532         return tsf;
2533 }
2534
2535 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2536 {
2537         struct ath_softc *sc = hw->priv;
2538
2539         mutex_lock(&sc->mutex);
2540         ath9k_hw_settsf64(sc->sc_ah, tsf);
2541         mutex_unlock(&sc->mutex);
2542 }
2543
2544 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2545 {
2546         struct ath_softc *sc = hw->priv;
2547
2548         mutex_lock(&sc->mutex);
2549         ath9k_hw_reset_tsf(sc->sc_ah);
2550         mutex_unlock(&sc->mutex);
2551 }
2552
2553 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2554                               enum ieee80211_ampdu_mlme_action action,
2555                               struct ieee80211_sta *sta,
2556                               u16 tid, u16 *ssn)
2557 {
2558         struct ath_softc *sc = hw->priv;
2559         int ret = 0;
2560
2561         switch (action) {
2562         case IEEE80211_AMPDU_RX_START:
2563                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2564                         ret = -ENOTSUPP;
2565                 break;
2566         case IEEE80211_AMPDU_RX_STOP:
2567                 break;
2568         case IEEE80211_AMPDU_TX_START:
2569                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2570                 if (ret < 0)
2571                         DPRINTF(sc, ATH_DBG_FATAL,
2572                                 "Unable to start TX aggregation\n");
2573                 else
2574                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2575                 break;
2576         case IEEE80211_AMPDU_TX_STOP:
2577                 ret = ath_tx_aggr_stop(sc, sta, tid);
2578                 if (ret < 0)
2579                         DPRINTF(sc, ATH_DBG_FATAL,
2580                                 "Unable to stop TX aggregation\n");
2581
2582                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2583                 break;
2584         case IEEE80211_AMPDU_TX_RESUME:
2585                 ath_tx_aggr_resume(sc, sta, tid);
2586                 break;
2587         default:
2588                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2589         }
2590
2591         return ret;
2592 }
2593
2594 struct ieee80211_ops ath9k_ops = {
2595         .tx                 = ath9k_tx,
2596         .start              = ath9k_start,
2597         .stop               = ath9k_stop,
2598         .add_interface      = ath9k_add_interface,
2599         .remove_interface   = ath9k_remove_interface,
2600         .config             = ath9k_config,
2601         .config_interface   = ath9k_config_interface,
2602         .configure_filter   = ath9k_configure_filter,
2603         .sta_notify         = ath9k_sta_notify,
2604         .conf_tx            = ath9k_conf_tx,
2605         .bss_info_changed   = ath9k_bss_info_changed,
2606         .set_key            = ath9k_set_key,
2607         .get_tsf            = ath9k_get_tsf,
2608         .set_tsf            = ath9k_set_tsf,
2609         .reset_tsf          = ath9k_reset_tsf,
2610         .ampdu_action       = ath9k_ampdu_action,
2611 };
2612
2613 static struct {
2614         u32 version;
2615         const char * name;
2616 } ath_mac_bb_names[] = {
2617         { AR_SREV_VERSION_5416_PCI,     "5416" },
2618         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2619         { AR_SREV_VERSION_9100,         "9100" },
2620         { AR_SREV_VERSION_9160,         "9160" },
2621         { AR_SREV_VERSION_9280,         "9280" },
2622         { AR_SREV_VERSION_9285,         "9285" }
2623 };
2624
2625 static struct {
2626         u16 version;
2627         const char * name;
2628 } ath_rf_names[] = {
2629         { 0,                            "5133" },
2630         { AR_RAD5133_SREV_MAJOR,        "5133" },
2631         { AR_RAD5122_SREV_MAJOR,        "5122" },
2632         { AR_RAD2133_SREV_MAJOR,        "2133" },
2633         { AR_RAD2122_SREV_MAJOR,        "2122" }
2634 };
2635
2636 /*
2637  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2638  */
2639 const char *
2640 ath_mac_bb_name(u32 mac_bb_version)
2641 {
2642         int i;
2643
2644         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2645                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2646                         return ath_mac_bb_names[i].name;
2647                 }
2648         }
2649
2650         return "????";
2651 }
2652
2653 /*
2654  * Return the RF name. "????" is returned if the RF is unknown.
2655  */
2656 const char *
2657 ath_rf_name(u16 rf_version)
2658 {
2659         int i;
2660
2661         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2662                 if (ath_rf_names[i].version == rf_version) {
2663                         return ath_rf_names[i].name;
2664                 }
2665         }
2666
2667         return "????";
2668 }
2669
2670 static int __init ath9k_init(void)
2671 {
2672         int error;
2673
2674         /* Register rate control algorithm */
2675         error = ath_rate_control_register();
2676         if (error != 0) {
2677                 printk(KERN_ERR
2678                         "ath9k: Unable to register rate control "
2679                         "algorithm: %d\n",
2680                         error);
2681                 goto err_out;
2682         }
2683
2684         error = ath_pci_init();
2685         if (error < 0) {
2686                 printk(KERN_ERR
2687                         "ath9k: No PCI devices found, driver not installed.\n");
2688                 error = -ENODEV;
2689                 goto err_rate_unregister;
2690         }
2691
2692         error = ath_ahb_init();
2693         if (error < 0) {
2694                 error = -ENODEV;
2695                 goto err_pci_exit;
2696         }
2697
2698         return 0;
2699
2700  err_pci_exit:
2701         ath_pci_exit();
2702
2703  err_rate_unregister:
2704         ath_rate_control_unregister();
2705  err_out:
2706         return error;
2707 }
2708 module_init(ath9k_init);
2709
2710 static void __exit ath9k_exit(void)
2711 {
2712         ath_ahb_exit();
2713         ath_pci_exit();
2714         ath_rate_control_unregister();
2715         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2716 }
2717 module_exit(ath9k_exit);