2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
29 #ifdef CONFIG_PCI_DOMAINS
30 int pci_domains_supported = 1;
33 #define DEFAULT_CARDBUS_IO_SIZE (256)
34 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
35 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
36 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
37 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
40 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
41 * @bus: pointer to PCI bus structure to search
43 * Given a PCI bus, returns the highest PCI bus number present in the set
44 * including the given PCI bus and its list of child PCI buses.
46 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
48 struct list_head *tmp;
51 max = bus->subordinate;
52 list_for_each(tmp, &bus->children) {
53 n = pci_bus_max_busnr(pci_bus_b(tmp));
59 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
61 #ifdef CONFIG_HAS_IOMEM
62 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
65 * Make sure the BAR is actually a memory resource, not an IO resource
67 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
71 return ioremap_nocache(pci_resource_start(pdev, bar),
72 pci_resource_len(pdev, bar));
74 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
79 * pci_max_busnr - returns maximum PCI bus number
81 * Returns the highest PCI bus number present in the system global list of
84 unsigned char __devinit
87 struct pci_bus *bus = NULL;
91 while ((bus = pci_find_next_bus(bus)) != NULL) {
92 n = pci_bus_max_busnr(bus);
101 #define PCI_FIND_CAP_TTL 48
103 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
104 u8 pos, int cap, int *ttl)
109 pci_bus_read_config_byte(bus, devfn, pos, &pos);
113 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
119 pos += PCI_CAP_LIST_NEXT;
124 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
127 int ttl = PCI_FIND_CAP_TTL;
129 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
132 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
134 return __pci_find_next_cap(dev->bus, dev->devfn,
135 pos + PCI_CAP_LIST_NEXT, cap);
137 EXPORT_SYMBOL_GPL(pci_find_next_capability);
139 static int __pci_bus_find_cap_start(struct pci_bus *bus,
140 unsigned int devfn, u8 hdr_type)
144 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
145 if (!(status & PCI_STATUS_CAP_LIST))
149 case PCI_HEADER_TYPE_NORMAL:
150 case PCI_HEADER_TYPE_BRIDGE:
151 return PCI_CAPABILITY_LIST;
152 case PCI_HEADER_TYPE_CARDBUS:
153 return PCI_CB_CAPABILITY_LIST;
162 * pci_find_capability - query for devices' capabilities
163 * @dev: PCI device to query
164 * @cap: capability code
166 * Tell if a device supports a given PCI capability.
167 * Returns the address of the requested capability structure within the
168 * device's PCI configuration space or 0 in case the device does not
169 * support it. Possible values for @cap:
171 * %PCI_CAP_ID_PM Power Management
172 * %PCI_CAP_ID_AGP Accelerated Graphics Port
173 * %PCI_CAP_ID_VPD Vital Product Data
174 * %PCI_CAP_ID_SLOTID Slot Identification
175 * %PCI_CAP_ID_MSI Message Signalled Interrupts
176 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
177 * %PCI_CAP_ID_PCIX PCI-X
178 * %PCI_CAP_ID_EXP PCI Express
180 int pci_find_capability(struct pci_dev *dev, int cap)
184 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
186 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
192 * pci_bus_find_capability - query for devices' capabilities
193 * @bus: the PCI bus to query
194 * @devfn: PCI device to query
195 * @cap: capability code
197 * Like pci_find_capability() but works for pci devices that do not have a
198 * pci_dev structure set up yet.
200 * Returns the address of the requested capability structure within the
201 * device's PCI configuration space or 0 in case the device does not
204 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
209 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
211 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
213 pos = __pci_find_next_cap(bus, devfn, pos, cap);
219 * pci_find_ext_capability - Find an extended capability
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Returns the address of the requested extended capability structure
224 * within the device's PCI configuration space or 0 if the device does
225 * not support it. Possible values for @cap:
227 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
228 * %PCI_EXT_CAP_ID_VC Virtual Channel
229 * %PCI_EXT_CAP_ID_DSN Device Serial Number
230 * %PCI_EXT_CAP_ID_PWR Power Budgeting
232 int pci_find_ext_capability(struct pci_dev *dev, int cap)
236 int pos = PCI_CFG_SPACE_SIZE;
238 /* minimum 8 bytes per capability */
239 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
241 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
244 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
248 * If we have no capabilities, this is indicated by cap ID,
249 * cap version and next pointer all being 0.
255 if (PCI_EXT_CAP_ID(header) == cap)
258 pos = PCI_EXT_CAP_NEXT(header);
259 if (pos < PCI_CFG_SPACE_SIZE)
262 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
268 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
270 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
272 int rc, ttl = PCI_FIND_CAP_TTL;
275 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
276 mask = HT_3BIT_CAP_MASK;
278 mask = HT_5BIT_CAP_MASK;
280 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
281 PCI_CAP_ID_HT, &ttl);
283 rc = pci_read_config_byte(dev, pos + 3, &cap);
284 if (rc != PCIBIOS_SUCCESSFUL)
287 if ((cap & mask) == ht_cap)
290 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
291 pos + PCI_CAP_LIST_NEXT,
292 PCI_CAP_ID_HT, &ttl);
298 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @pos: Position from which to continue searching
301 * @ht_cap: Hypertransport capability code
303 * To be used in conjunction with pci_find_ht_capability() to search for
304 * all capabilities matching @ht_cap. @pos should always be a value returned
305 * from pci_find_ht_capability().
307 * NB. To be 100% safe against broken PCI devices, the caller should take
308 * steps to avoid an infinite loop.
310 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
312 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
314 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
317 * pci_find_ht_capability - query a device's Hypertransport capabilities
318 * @dev: PCI device to query
319 * @ht_cap: Hypertransport capability code
321 * Tell if a device supports a given Hypertransport capability.
322 * Returns an address within the device's PCI configuration space
323 * or 0 in case the device does not support the request capability.
324 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
325 * which has a Hypertransport capability matching @ht_cap.
327 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
331 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
333 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
337 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
340 * pci_find_parent_resource - return resource region of parent bus of given region
341 * @dev: PCI device structure contains resources to be searched
342 * @res: child resource record for which parent is sought
344 * For given resource region of given device, return the resource
345 * region of parent bus the given region is contained in or where
346 * it should be allocated from.
349 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
351 const struct pci_bus *bus = dev->bus;
353 struct resource *best = NULL;
355 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
356 struct resource *r = bus->resource[i];
359 if (res->start && !(res->start >= r->start && res->end <= r->end))
360 continue; /* Not contained */
361 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
362 continue; /* Wrong type */
363 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
364 return r; /* Exact match */
365 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
366 best = r; /* Approximating prefetchable by non-prefetchable */
372 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
373 * @dev: PCI device to have its BARs restored
375 * Restore the BAR values for a given device, so as to make it
376 * accessible by its driver.
379 pci_restore_bars(struct pci_dev *dev)
383 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
384 pci_update_resource(dev, i);
387 static struct pci_platform_pm_ops *pci_platform_pm;
389 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
391 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
392 || !ops->sleep_wake || !ops->can_wakeup)
394 pci_platform_pm = ops;
398 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
400 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
403 static inline int platform_pci_set_power_state(struct pci_dev *dev,
406 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
409 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
411 return pci_platform_pm ?
412 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
415 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
417 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
420 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
422 return pci_platform_pm ?
423 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
427 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
429 * @dev: PCI device to handle.
430 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
433 * -EINVAL if the requested state is invalid.
434 * -EIO if device does not support PCI PM or its PM capabilities register has a
435 * wrong version, or device doesn't support the requested state.
436 * 0 if device already is in the requested state.
437 * 0 if device's power state has been successfully changed.
439 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
442 bool need_restore = false;
444 /* Check if we're already there */
445 if (dev->current_state == state)
451 if (state < PCI_D0 || state > PCI_D3hot)
454 /* Validate current state:
455 * Can enter D0 from any state, but if we can only go deeper
456 * to sleep if we're already in a low power state
458 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
459 && dev->current_state > state) {
460 dev_err(&dev->dev, "invalid power transition "
461 "(from state %d to %d)\n", dev->current_state, state);
465 /* check if this device supports the desired state */
466 if ((state == PCI_D1 && !dev->d1_support)
467 || (state == PCI_D2 && !dev->d2_support))
470 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
472 /* If we're (effectively) in D3, force entire word to 0.
473 * This doesn't affect PME_Status, disables PME_En, and
474 * sets PowerState to 0.
476 switch (dev->current_state) {
480 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
485 case PCI_UNKNOWN: /* Boot-up */
486 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
487 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
489 /* Fall-through: force to D0 */
495 /* enter specified state */
496 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
498 /* Mandatory power management transition delays */
499 /* see PCI PM 1.1 5.6.1 table 18 */
500 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
501 msleep(pci_pm_d3_delay);
502 else if (state == PCI_D2 || dev->current_state == PCI_D2)
503 udelay(PCI_PM_D2_DELAY);
505 dev->current_state = state;
507 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
508 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
509 * from D3hot to D0 _may_ perform an internal reset, thereby
510 * going to "D0 Uninitialized" rather than "D0 Initialized".
511 * For example, at least some versions of the 3c905B and the
512 * 3c556B exhibit this behaviour.
514 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
515 * devices in a D3hot state at boot. Consequently, we need to
516 * restore at least the BARs so that the device will be
517 * accessible to its driver.
520 pci_restore_bars(dev);
523 pcie_aspm_pm_state_change(dev->bus->self);
529 * pci_update_current_state - Read PCI power state of given device from its
530 * PCI PM registers and cache it
531 * @dev: PCI device to handle.
532 * @state: State to cache in case the device doesn't have the PM capability
534 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
539 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
540 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
542 dev->current_state = state;
547 * pci_platform_power_transition - Use platform to change device power state
548 * @dev: PCI device to handle.
549 * @state: State to put the device into.
551 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
555 if (platform_pci_power_manageable(dev)) {
556 error = platform_pci_set_power_state(dev, state);
558 pci_update_current_state(dev, state);
561 /* Fall back to PCI_D0 if native PM is not supported */
563 dev->current_state = PCI_D0;
570 * __pci_start_power_transition - Start power transition of a PCI device
571 * @dev: PCI device to handle.
572 * @state: State to put the device into.
574 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
577 pci_platform_power_transition(dev, PCI_D0);
581 * __pci_complete_power_transition - Complete power transition of a PCI device
582 * @dev: PCI device to handle.
583 * @state: State to put the device into.
585 * This function should not be called directly by device drivers.
587 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
589 return state > PCI_D0 ?
590 pci_platform_power_transition(dev, state) : -EINVAL;
592 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
595 * pci_set_power_state - Set the power state of a PCI device
596 * @dev: PCI device to handle.
597 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
599 * Transition a device to a new power state, using the platform firmware and/or
600 * the device's PCI PM registers.
603 * -EINVAL if the requested state is invalid.
604 * -EIO if device does not support PCI PM or its PM capabilities register has a
605 * wrong version, or device doesn't support the requested state.
606 * 0 if device already is in the requested state.
607 * 0 if device's power state has been successfully changed.
609 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
613 /* bound the state we're entering */
614 if (state > PCI_D3hot)
616 else if (state < PCI_D0)
618 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
620 * If the device or the parent bridge do not support PCI PM,
621 * ignore the request if we're doing anything other than putting
622 * it into D0 (which would only happen on boot).
626 /* Check if we're already there */
627 if (dev->current_state == state)
630 __pci_start_power_transition(dev, state);
632 /* This device is quirked not to be put into D3, so
633 don't put it in D3 */
634 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
637 error = pci_raw_set_power_state(dev, state);
639 if (!__pci_complete_power_transition(dev, state))
646 * pci_choose_state - Choose the power state of a PCI device
647 * @dev: PCI device to be suspended
648 * @state: target sleep state for the whole system. This is the value
649 * that is passed to suspend() function.
651 * Returns PCI power state suitable for given device and given system
655 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
659 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
662 ret = platform_pci_choose_state(dev);
663 if (ret != PCI_POWER_ERROR)
666 switch (state.event) {
669 case PM_EVENT_FREEZE:
670 case PM_EVENT_PRETHAW:
671 /* REVISIT both freeze and pre-thaw "should" use D0 */
672 case PM_EVENT_SUSPEND:
673 case PM_EVENT_HIBERNATE:
676 dev_info(&dev->dev, "unrecognized suspend event %d\n",
683 EXPORT_SYMBOL(pci_choose_state);
685 #define PCI_EXP_SAVE_REGS 7
687 #define pcie_cap_has_devctl(type, flags) 1
688 #define pcie_cap_has_lnkctl(type, flags) \
689 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
690 (type == PCI_EXP_TYPE_ROOT_PORT || \
691 type == PCI_EXP_TYPE_ENDPOINT || \
692 type == PCI_EXP_TYPE_LEG_END))
693 #define pcie_cap_has_sltctl(type, flags) \
694 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
695 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
696 (type == PCI_EXP_TYPE_DOWNSTREAM && \
697 (flags & PCI_EXP_FLAGS_SLOT))))
698 #define pcie_cap_has_rtctl(type, flags) \
699 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
700 (type == PCI_EXP_TYPE_ROOT_PORT || \
701 type == PCI_EXP_TYPE_RC_EC))
702 #define pcie_cap_has_devctl2(type, flags) \
703 ((flags & PCI_EXP_FLAGS_VERS) > 1)
704 #define pcie_cap_has_lnkctl2(type, flags) \
705 ((flags & PCI_EXP_FLAGS_VERS) > 1)
706 #define pcie_cap_has_sltctl2(type, flags) \
707 ((flags & PCI_EXP_FLAGS_VERS) > 1)
709 static int pci_save_pcie_state(struct pci_dev *dev)
712 struct pci_cap_saved_state *save_state;
716 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
720 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
722 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
725 cap = (u16 *)&save_state->data[0];
727 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
729 if (pcie_cap_has_devctl(dev->pcie_type, flags))
730 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
731 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
732 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
733 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
734 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
735 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
736 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
737 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
738 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
739 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
740 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
741 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
742 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
747 static void pci_restore_pcie_state(struct pci_dev *dev)
750 struct pci_cap_saved_state *save_state;
754 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
755 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
756 if (!save_state || pos <= 0)
758 cap = (u16 *)&save_state->data[0];
760 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
762 if (pcie_cap_has_devctl(dev->pcie_type, flags))
763 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
764 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
765 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
766 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
767 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
768 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
769 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
770 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
771 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
772 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
773 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
774 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
775 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
779 static int pci_save_pcix_state(struct pci_dev *dev)
782 struct pci_cap_saved_state *save_state;
784 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
788 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
790 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
794 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
799 static void pci_restore_pcix_state(struct pci_dev *dev)
802 struct pci_cap_saved_state *save_state;
805 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
806 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
807 if (!save_state || pos <= 0)
809 cap = (u16 *)&save_state->data[0];
811 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
816 * pci_save_state - save the PCI configuration space of a device before suspending
817 * @dev: - PCI device that we're dealing with
820 pci_save_state(struct pci_dev *dev)
823 /* XXX: 100% dword access ok here? */
824 for (i = 0; i < 16; i++)
825 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
826 dev->state_saved = true;
827 if ((i = pci_save_pcie_state(dev)) != 0)
829 if ((i = pci_save_pcix_state(dev)) != 0)
835 * pci_restore_state - Restore the saved state of a PCI device
836 * @dev: - PCI device that we're dealing with
839 pci_restore_state(struct pci_dev *dev)
844 /* PCI Express register must be restored first */
845 pci_restore_pcie_state(dev);
848 * The Base Address register should be programmed before the command
851 for (i = 15; i >= 0; i--) {
852 pci_read_config_dword(dev, i * 4, &val);
853 if (val != dev->saved_config_space[i]) {
854 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
855 "space at offset %#x (was %#x, writing %#x)\n",
856 i, val, (int)dev->saved_config_space[i]);
857 pci_write_config_dword(dev,i * 4,
858 dev->saved_config_space[i]);
861 pci_restore_pcix_state(dev);
862 pci_restore_msi_state(dev);
863 pci_restore_iov_state(dev);
868 static int do_pci_enable_device(struct pci_dev *dev, int bars)
872 err = pci_set_power_state(dev, PCI_D0);
873 if (err < 0 && err != -EIO)
875 err = pcibios_enable_device(dev, bars);
878 pci_fixup_device(pci_fixup_enable, dev);
884 * pci_reenable_device - Resume abandoned device
885 * @dev: PCI device to be resumed
887 * Note this function is a backend of pci_default_resume and is not supposed
888 * to be called by normal code, write proper resume handler and use it instead.
890 int pci_reenable_device(struct pci_dev *dev)
892 if (pci_is_enabled(dev))
893 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
897 static int __pci_enable_device_flags(struct pci_dev *dev,
898 resource_size_t flags)
903 if (atomic_add_return(1, &dev->enable_cnt) > 1)
904 return 0; /* already enabled */
906 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
907 if (dev->resource[i].flags & flags)
910 err = do_pci_enable_device(dev, bars);
912 atomic_dec(&dev->enable_cnt);
917 * pci_enable_device_io - Initialize a device for use with IO space
918 * @dev: PCI device to be initialized
920 * Initialize device before it's used by a driver. Ask low-level code
921 * to enable I/O resources. Wake up the device if it was suspended.
922 * Beware, this function can fail.
924 int pci_enable_device_io(struct pci_dev *dev)
926 return __pci_enable_device_flags(dev, IORESOURCE_IO);
930 * pci_enable_device_mem - Initialize a device for use with Memory space
931 * @dev: PCI device to be initialized
933 * Initialize device before it's used by a driver. Ask low-level code
934 * to enable Memory resources. Wake up the device if it was suspended.
935 * Beware, this function can fail.
937 int pci_enable_device_mem(struct pci_dev *dev)
939 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
943 * pci_enable_device - Initialize device before it's used by a driver.
944 * @dev: PCI device to be initialized
946 * Initialize device before it's used by a driver. Ask low-level code
947 * to enable I/O and memory. Wake up the device if it was suspended.
948 * Beware, this function can fail.
950 * Note we don't actually enable the device many times if we call
951 * this function repeatedly (we just increment the count).
953 int pci_enable_device(struct pci_dev *dev)
955 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
959 * Managed PCI resources. This manages device on/off, intx/msi/msix
960 * on/off and BAR regions. pci_dev itself records msi/msix status, so
961 * there's no need to track it separately. pci_devres is initialized
962 * when a device is enabled using managed PCI device enable interface.
965 unsigned int enabled:1;
966 unsigned int pinned:1;
967 unsigned int orig_intx:1;
968 unsigned int restore_intx:1;
972 static void pcim_release(struct device *gendev, void *res)
974 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
975 struct pci_devres *this = res;
978 if (dev->msi_enabled)
979 pci_disable_msi(dev);
980 if (dev->msix_enabled)
981 pci_disable_msix(dev);
983 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
984 if (this->region_mask & (1 << i))
985 pci_release_region(dev, i);
987 if (this->restore_intx)
988 pci_intx(dev, this->orig_intx);
990 if (this->enabled && !this->pinned)
991 pci_disable_device(dev);
994 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
996 struct pci_devres *dr, *new_dr;
998 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1002 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1005 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1008 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1010 if (pci_is_managed(pdev))
1011 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1016 * pcim_enable_device - Managed pci_enable_device()
1017 * @pdev: PCI device to be initialized
1019 * Managed pci_enable_device().
1021 int pcim_enable_device(struct pci_dev *pdev)
1023 struct pci_devres *dr;
1026 dr = get_pci_dr(pdev);
1032 rc = pci_enable_device(pdev);
1034 pdev->is_managed = 1;
1041 * pcim_pin_device - Pin managed PCI device
1042 * @pdev: PCI device to pin
1044 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1045 * driver detach. @pdev must have been enabled with
1046 * pcim_enable_device().
1048 void pcim_pin_device(struct pci_dev *pdev)
1050 struct pci_devres *dr;
1052 dr = find_pci_dr(pdev);
1053 WARN_ON(!dr || !dr->enabled);
1059 * pcibios_disable_device - disable arch specific PCI resources for device dev
1060 * @dev: the PCI device to disable
1062 * Disables architecture specific PCI resources for the device. This
1063 * is the default implementation. Architecture implementations can
1066 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1068 static void do_pci_disable_device(struct pci_dev *dev)
1072 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1073 if (pci_command & PCI_COMMAND_MASTER) {
1074 pci_command &= ~PCI_COMMAND_MASTER;
1075 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1078 pcibios_disable_device(dev);
1082 * pci_disable_enabled_device - Disable device without updating enable_cnt
1083 * @dev: PCI device to disable
1085 * NOTE: This function is a backend of PCI power management routines and is
1086 * not supposed to be called drivers.
1088 void pci_disable_enabled_device(struct pci_dev *dev)
1090 if (pci_is_enabled(dev))
1091 do_pci_disable_device(dev);
1095 * pci_disable_device - Disable PCI device after use
1096 * @dev: PCI device to be disabled
1098 * Signal to the system that the PCI device is not in use by the system
1099 * anymore. This only involves disabling PCI bus-mastering, if active.
1101 * Note we don't actually disable the device until all callers of
1102 * pci_device_enable() have called pci_device_disable().
1105 pci_disable_device(struct pci_dev *dev)
1107 struct pci_devres *dr;
1109 dr = find_pci_dr(dev);
1113 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1116 do_pci_disable_device(dev);
1118 dev->is_busmaster = 0;
1122 * pcibios_set_pcie_reset_state - set reset state for device dev
1123 * @dev: the PCI-E device reset
1124 * @state: Reset state to enter into
1127 * Sets the PCI-E reset state for the device. This is the default
1128 * implementation. Architecture implementations can override this.
1130 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1131 enum pcie_reset_state state)
1137 * pci_set_pcie_reset_state - set reset state for device dev
1138 * @dev: the PCI-E device reset
1139 * @state: Reset state to enter into
1142 * Sets the PCI reset state for the device.
1144 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1146 return pcibios_set_pcie_reset_state(dev, state);
1150 * pci_pme_capable - check the capability of PCI device to generate PME#
1151 * @dev: PCI device to handle.
1152 * @state: PCI state from which device will issue PME#.
1154 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1159 return !!(dev->pme_support & (1 << state));
1163 * pci_pme_active - enable or disable PCI device's PME# function
1164 * @dev: PCI device to handle.
1165 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1167 * The caller must verify that the device is capable of generating PME# before
1168 * calling this function with @enable equal to 'true'.
1170 void pci_pme_active(struct pci_dev *dev, bool enable)
1177 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1178 /* Clear PME_Status by writing 1 to it and enable PME# */
1179 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1181 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1183 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1185 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1186 enable ? "enabled" : "disabled");
1190 * pci_enable_wake - enable PCI device as wakeup event source
1191 * @dev: PCI device affected
1192 * @state: PCI state from which device will issue wakeup events
1193 * @enable: True to enable event generation; false to disable
1195 * This enables the device as a wakeup event source, or disables it.
1196 * When such events involves platform-specific hooks, those hooks are
1197 * called automatically by this routine.
1199 * Devices with legacy power management (no standard PCI PM capabilities)
1200 * always require such platform hooks.
1203 * 0 is returned on success
1204 * -EINVAL is returned if device is not supposed to wake up the system
1205 * Error code depending on the platform is returned if both the platform and
1206 * the native mechanism fail to enable the generation of wake-up events
1208 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1211 bool pme_done = false;
1213 if (enable && !device_may_wakeup(&dev->dev))
1217 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1218 * Anderson we should be doing PME# wake enable followed by ACPI wake
1219 * enable. To disable wake-up we call the platform first, for symmetry.
1222 if (!enable && platform_pci_can_wakeup(dev))
1223 error = platform_pci_sleep_wake(dev, false);
1225 if (!enable || pci_pme_capable(dev, state)) {
1226 pci_pme_active(dev, enable);
1230 if (enable && platform_pci_can_wakeup(dev))
1231 error = platform_pci_sleep_wake(dev, true);
1233 return pme_done ? 0 : error;
1237 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1238 * @dev: PCI device to prepare
1239 * @enable: True to enable wake-up event generation; false to disable
1241 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1242 * and this function allows them to set that up cleanly - pci_enable_wake()
1243 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1244 * ordering constraints.
1246 * This function only returns error code if the device is not capable of
1247 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1248 * enable wake-up power for it.
1250 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1252 return pci_pme_capable(dev, PCI_D3cold) ?
1253 pci_enable_wake(dev, PCI_D3cold, enable) :
1254 pci_enable_wake(dev, PCI_D3hot, enable);
1258 * pci_target_state - find an appropriate low power state for a given PCI dev
1261 * Use underlying platform code to find a supported low power state for @dev.
1262 * If the platform can't manage @dev, return the deepest state from which it
1263 * can generate wake events, based on any available PME info.
1265 pci_power_t pci_target_state(struct pci_dev *dev)
1267 pci_power_t target_state = PCI_D3hot;
1269 if (platform_pci_power_manageable(dev)) {
1271 * Call the platform to choose the target state of the device
1272 * and enable wake-up from this state if supported.
1274 pci_power_t state = platform_pci_choose_state(dev);
1277 case PCI_POWER_ERROR:
1282 if (pci_no_d1d2(dev))
1285 target_state = state;
1287 } else if (!dev->pm_cap) {
1288 target_state = PCI_D0;
1289 } else if (device_may_wakeup(&dev->dev)) {
1291 * Find the deepest state from which the device can generate
1292 * wake-up events, make it the target state and enable device
1295 if (dev->pme_support) {
1297 && !(dev->pme_support & (1 << target_state)))
1302 return target_state;
1306 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1307 * @dev: Device to handle.
1309 * Choose the power state appropriate for the device depending on whether
1310 * it can wake up the system and/or is power manageable by the platform
1311 * (PCI_D3hot is the default) and put the device into that state.
1313 int pci_prepare_to_sleep(struct pci_dev *dev)
1315 pci_power_t target_state = pci_target_state(dev);
1318 if (target_state == PCI_POWER_ERROR)
1321 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1323 error = pci_set_power_state(dev, target_state);
1326 pci_enable_wake(dev, target_state, false);
1332 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1333 * @dev: Device to handle.
1335 * Disable device's sytem wake-up capability and put it into D0.
1337 int pci_back_from_sleep(struct pci_dev *dev)
1339 pci_enable_wake(dev, PCI_D0, false);
1340 return pci_set_power_state(dev, PCI_D0);
1344 * pci_pm_init - Initialize PM functions of given PCI device
1345 * @dev: PCI device to handle.
1347 void pci_pm_init(struct pci_dev *dev)
1354 /* find PCI PM capability in list */
1355 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1358 /* Check device's ability to generate PME# */
1359 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1361 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1362 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1363 pmc & PCI_PM_CAP_VER_MASK);
1369 dev->d1_support = false;
1370 dev->d2_support = false;
1371 if (!pci_no_d1d2(dev)) {
1372 if (pmc & PCI_PM_CAP_D1)
1373 dev->d1_support = true;
1374 if (pmc & PCI_PM_CAP_D2)
1375 dev->d2_support = true;
1377 if (dev->d1_support || dev->d2_support)
1378 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1379 dev->d1_support ? " D1" : "",
1380 dev->d2_support ? " D2" : "");
1383 pmc &= PCI_PM_CAP_PME_MASK;
1385 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1386 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1387 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1388 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1389 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1390 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1391 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1393 * Make device's PM flags reflect the wake-up capability, but
1394 * let the user space enable it to wake up the system as needed.
1396 device_set_wakeup_capable(&dev->dev, true);
1397 device_set_wakeup_enable(&dev->dev, false);
1398 /* Disable the PME# generation functionality */
1399 pci_pme_active(dev, false);
1401 dev->pme_support = 0;
1406 * platform_pci_wakeup_init - init platform wakeup if present
1409 * Some devices don't have PCI PM caps but can still generate wakeup
1410 * events through platform methods (like ACPI events). If @dev supports
1411 * platform wakeup events, set the device flag to indicate as much. This
1412 * may be redundant if the device also supports PCI PM caps, but double
1413 * initialization should be safe in that case.
1415 void platform_pci_wakeup_init(struct pci_dev *dev)
1417 if (!platform_pci_can_wakeup(dev))
1420 device_set_wakeup_capable(&dev->dev, true);
1421 device_set_wakeup_enable(&dev->dev, false);
1422 platform_pci_sleep_wake(dev, false);
1426 * pci_add_save_buffer - allocate buffer for saving given capability registers
1427 * @dev: the PCI device
1428 * @cap: the capability to allocate the buffer for
1429 * @size: requested size of the buffer
1431 static int pci_add_cap_save_buffer(
1432 struct pci_dev *dev, char cap, unsigned int size)
1435 struct pci_cap_saved_state *save_state;
1437 pos = pci_find_capability(dev, cap);
1441 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1445 save_state->cap_nr = cap;
1446 pci_add_saved_cap(dev, save_state);
1452 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1453 * @dev: the PCI device
1455 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1459 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1460 PCI_EXP_SAVE_REGS * sizeof(u16));
1463 "unable to preallocate PCI Express save buffer\n");
1465 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1468 "unable to preallocate PCI-X save buffer\n");
1472 * pci_enable_ari - enable ARI forwarding if hardware support it
1473 * @dev: the PCI device
1475 void pci_enable_ari(struct pci_dev *dev)
1480 struct pci_dev *bridge;
1482 if (!dev->is_pcie || dev->devfn)
1485 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1489 bridge = dev->bus->self;
1490 if (!bridge || !bridge->is_pcie)
1493 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1497 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1498 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1501 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1502 ctrl |= PCI_EXP_DEVCTL2_ARI;
1503 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1505 bridge->ari_enabled = 1;
1509 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1510 * @dev: the PCI device
1511 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1513 * Perform INTx swizzling for a device behind one level of bridge. This is
1514 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1515 * behind bridges on add-in cards.
1517 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1519 return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1;
1523 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1531 while (!pci_is_root_bus(dev->bus)) {
1532 pin = pci_swizzle_interrupt_pin(dev, pin);
1533 dev = dev->bus->self;
1540 * pci_common_swizzle - swizzle INTx all the way to root bridge
1541 * @dev: the PCI device
1542 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1544 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1545 * bridges all the way up to a PCI root bus.
1547 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1551 while (!pci_is_root_bus(dev->bus)) {
1552 pin = pci_swizzle_interrupt_pin(dev, pin);
1553 dev = dev->bus->self;
1556 return PCI_SLOT(dev->devfn);
1560 * pci_release_region - Release a PCI bar
1561 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1562 * @bar: BAR to release
1564 * Releases the PCI I/O and memory resources previously reserved by a
1565 * successful call to pci_request_region. Call this function only
1566 * after all use of the PCI regions has ceased.
1568 void pci_release_region(struct pci_dev *pdev, int bar)
1570 struct pci_devres *dr;
1572 if (pci_resource_len(pdev, bar) == 0)
1574 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1575 release_region(pci_resource_start(pdev, bar),
1576 pci_resource_len(pdev, bar));
1577 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1578 release_mem_region(pci_resource_start(pdev, bar),
1579 pci_resource_len(pdev, bar));
1581 dr = find_pci_dr(pdev);
1583 dr->region_mask &= ~(1 << bar);
1587 * __pci_request_region - Reserved PCI I/O and memory resource
1588 * @pdev: PCI device whose resources are to be reserved
1589 * @bar: BAR to be reserved
1590 * @res_name: Name to be associated with resource.
1591 * @exclusive: whether the region access is exclusive or not
1593 * Mark the PCI region associated with PCI device @pdev BR @bar as
1594 * being reserved by owner @res_name. Do not access any
1595 * address inside the PCI regions unless this call returns
1598 * If @exclusive is set, then the region is marked so that userspace
1599 * is explicitly not allowed to map the resource via /dev/mem or
1600 * sysfs MMIO access.
1602 * Returns 0 on success, or %EBUSY on error. A warning
1603 * message is also printed on failure.
1605 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1608 struct pci_devres *dr;
1610 if (pci_resource_len(pdev, bar) == 0)
1613 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1614 if (!request_region(pci_resource_start(pdev, bar),
1615 pci_resource_len(pdev, bar), res_name))
1618 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1619 if (!__request_mem_region(pci_resource_start(pdev, bar),
1620 pci_resource_len(pdev, bar), res_name,
1625 dr = find_pci_dr(pdev);
1627 dr->region_mask |= 1 << bar;
1632 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
1634 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1635 &pdev->resource[bar]);
1640 * pci_request_region - Reserve PCI I/O and memory resource
1641 * @pdev: PCI device whose resources are to be reserved
1642 * @bar: BAR to be reserved
1643 * @res_name: Name to be associated with resource
1645 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1646 * being reserved by owner @res_name. Do not access any
1647 * address inside the PCI regions unless this call returns
1650 * Returns 0 on success, or %EBUSY on error. A warning
1651 * message is also printed on failure.
1653 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1655 return __pci_request_region(pdev, bar, res_name, 0);
1659 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1660 * @pdev: PCI device whose resources are to be reserved
1661 * @bar: BAR to be reserved
1662 * @res_name: Name to be associated with resource.
1664 * Mark the PCI region associated with PCI device @pdev BR @bar as
1665 * being reserved by owner @res_name. Do not access any
1666 * address inside the PCI regions unless this call returns
1669 * Returns 0 on success, or %EBUSY on error. A warning
1670 * message is also printed on failure.
1672 * The key difference that _exclusive makes it that userspace is
1673 * explicitly not allowed to map the resource via /dev/mem or
1676 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1678 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1681 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1682 * @pdev: PCI device whose resources were previously reserved
1683 * @bars: Bitmask of BARs to be released
1685 * Release selected PCI I/O and memory resources previously reserved.
1686 * Call this function only after all use of the PCI regions has ceased.
1688 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1692 for (i = 0; i < 6; i++)
1693 if (bars & (1 << i))
1694 pci_release_region(pdev, i);
1697 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1698 const char *res_name, int excl)
1702 for (i = 0; i < 6; i++)
1703 if (bars & (1 << i))
1704 if (__pci_request_region(pdev, i, res_name, excl))
1710 if (bars & (1 << i))
1711 pci_release_region(pdev, i);
1718 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1719 * @pdev: PCI device whose resources are to be reserved
1720 * @bars: Bitmask of BARs to be requested
1721 * @res_name: Name to be associated with resource
1723 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1724 const char *res_name)
1726 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1729 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1730 int bars, const char *res_name)
1732 return __pci_request_selected_regions(pdev, bars, res_name,
1733 IORESOURCE_EXCLUSIVE);
1737 * pci_release_regions - Release reserved PCI I/O and memory resources
1738 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1740 * Releases all PCI I/O and memory resources previously reserved by a
1741 * successful call to pci_request_regions. Call this function only
1742 * after all use of the PCI regions has ceased.
1745 void pci_release_regions(struct pci_dev *pdev)
1747 pci_release_selected_regions(pdev, (1 << 6) - 1);
1751 * pci_request_regions - Reserved PCI I/O and memory resources
1752 * @pdev: PCI device whose resources are to be reserved
1753 * @res_name: Name to be associated with resource.
1755 * Mark all PCI regions associated with PCI device @pdev as
1756 * being reserved by owner @res_name. Do not access any
1757 * address inside the PCI regions unless this call returns
1760 * Returns 0 on success, or %EBUSY on error. A warning
1761 * message is also printed on failure.
1763 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1765 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1769 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1770 * @pdev: PCI device whose resources are to be reserved
1771 * @res_name: Name to be associated with resource.
1773 * Mark all PCI regions associated with PCI device @pdev as
1774 * being reserved by owner @res_name. Do not access any
1775 * address inside the PCI regions unless this call returns
1778 * pci_request_regions_exclusive() will mark the region so that
1779 * /dev/mem and the sysfs MMIO access will not be allowed.
1781 * Returns 0 on success, or %EBUSY on error. A warning
1782 * message is also printed on failure.
1784 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1786 return pci_request_selected_regions_exclusive(pdev,
1787 ((1 << 6) - 1), res_name);
1790 static void __pci_set_master(struct pci_dev *dev, bool enable)
1794 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1796 cmd = old_cmd | PCI_COMMAND_MASTER;
1798 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1799 if (cmd != old_cmd) {
1800 dev_dbg(&dev->dev, "%s bus mastering\n",
1801 enable ? "enabling" : "disabling");
1802 pci_write_config_word(dev, PCI_COMMAND, cmd);
1804 dev->is_busmaster = enable;
1808 * pci_set_master - enables bus-mastering for device dev
1809 * @dev: the PCI device to enable
1811 * Enables bus-mastering on the device and calls pcibios_set_master()
1812 * to do the needed arch specific settings.
1814 void pci_set_master(struct pci_dev *dev)
1816 __pci_set_master(dev, true);
1817 pcibios_set_master(dev);
1821 * pci_clear_master - disables bus-mastering for device dev
1822 * @dev: the PCI device to disable
1824 void pci_clear_master(struct pci_dev *dev)
1826 __pci_set_master(dev, false);
1829 #ifdef PCI_DISABLE_MWI
1830 int pci_set_mwi(struct pci_dev *dev)
1835 int pci_try_set_mwi(struct pci_dev *dev)
1840 void pci_clear_mwi(struct pci_dev *dev)
1846 #ifndef PCI_CACHE_LINE_BYTES
1847 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1850 /* This can be overridden by arch code. */
1851 /* Don't forget this is measured in 32-bit words, not bytes */
1852 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1855 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1856 * @dev: the PCI device for which MWI is to be enabled
1858 * Helper function for pci_set_mwi.
1859 * Originally copied from drivers/net/acenic.c.
1860 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1862 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1865 pci_set_cacheline_size(struct pci_dev *dev)
1869 if (!pci_cache_line_size)
1870 return -EINVAL; /* The system doesn't support MWI. */
1872 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1873 equal to or multiple of the right value. */
1874 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1875 if (cacheline_size >= pci_cache_line_size &&
1876 (cacheline_size % pci_cache_line_size) == 0)
1879 /* Write the correct value. */
1880 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1882 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1883 if (cacheline_size == pci_cache_line_size)
1886 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1887 "supported\n", pci_cache_line_size << 2);
1893 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1894 * @dev: the PCI device for which MWI is enabled
1896 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1898 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1901 pci_set_mwi(struct pci_dev *dev)
1906 rc = pci_set_cacheline_size(dev);
1910 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1911 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1912 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1913 cmd |= PCI_COMMAND_INVALIDATE;
1914 pci_write_config_word(dev, PCI_COMMAND, cmd);
1921 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1922 * @dev: the PCI device for which MWI is enabled
1924 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1925 * Callers are not required to check the return value.
1927 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1929 int pci_try_set_mwi(struct pci_dev *dev)
1931 int rc = pci_set_mwi(dev);
1936 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1937 * @dev: the PCI device to disable
1939 * Disables PCI Memory-Write-Invalidate transaction on the device
1942 pci_clear_mwi(struct pci_dev *dev)
1946 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1947 if (cmd & PCI_COMMAND_INVALIDATE) {
1948 cmd &= ~PCI_COMMAND_INVALIDATE;
1949 pci_write_config_word(dev, PCI_COMMAND, cmd);
1952 #endif /* ! PCI_DISABLE_MWI */
1955 * pci_intx - enables/disables PCI INTx for device dev
1956 * @pdev: the PCI device to operate on
1957 * @enable: boolean: whether to enable or disable PCI INTx
1959 * Enables/disables PCI INTx for device dev
1962 pci_intx(struct pci_dev *pdev, int enable)
1964 u16 pci_command, new;
1966 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1969 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1971 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1974 if (new != pci_command) {
1975 struct pci_devres *dr;
1977 pci_write_config_word(pdev, PCI_COMMAND, new);
1979 dr = find_pci_dr(pdev);
1980 if (dr && !dr->restore_intx) {
1981 dr->restore_intx = 1;
1982 dr->orig_intx = !enable;
1988 * pci_msi_off - disables any msi or msix capabilities
1989 * @dev: the PCI device to operate on
1991 * If you want to use msi see pci_enable_msi and friends.
1992 * This is a lower level primitive that allows us to disable
1993 * msi operation at the device level.
1995 void pci_msi_off(struct pci_dev *dev)
2000 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2002 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2003 control &= ~PCI_MSI_FLAGS_ENABLE;
2004 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2006 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2008 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2009 control &= ~PCI_MSIX_FLAGS_ENABLE;
2010 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2014 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2016 * These can be overridden by arch-specific implementations
2019 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2021 if (!pci_dma_supported(dev, mask))
2024 dev->dma_mask = mask;
2030 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2032 if (!pci_dma_supported(dev, mask))
2035 dev->dev.coherent_dma_mask = mask;
2041 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2042 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2044 return dma_set_max_seg_size(&dev->dev, size);
2046 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2049 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2050 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2052 return dma_set_seg_boundary(&dev->dev, mask);
2054 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2057 static int pcie_flr(struct pci_dev *dev, int probe)
2064 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2068 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2069 if (!(cap & PCI_EXP_DEVCAP_FLR))
2075 /* Wait for Transaction Pending bit clean */
2076 for (i = 0; i < 4; i++) {
2078 msleep((1 << (i - 1)) * 100);
2080 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2081 if (!(status & PCI_EXP_DEVSTA_TRPND))
2085 dev_err(&dev->dev, "transaction is not cleared; "
2086 "proceeding with reset anyway\n");
2089 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2090 PCI_EXP_DEVCTL_BCR_FLR);
2096 static int pci_af_flr(struct pci_dev *dev, int probe)
2103 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2107 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2108 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2114 /* Wait for Transaction Pending bit clean */
2115 for (i = 0; i < 4; i++) {
2117 msleep((1 << (i - 1)) * 100);
2119 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2120 if (!(status & PCI_AF_STATUS_TP))
2124 dev_err(&dev->dev, "transaction is not cleared; "
2125 "proceeding with reset anyway\n");
2128 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2134 static int pci_pm_reset(struct pci_dev *dev, int probe)
2141 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2142 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2148 if (dev->current_state != PCI_D0)
2151 csr &= ~PCI_PM_CTRL_STATE_MASK;
2153 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2154 msleep(pci_pm_d3_delay);
2156 csr &= ~PCI_PM_CTRL_STATE_MASK;
2158 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2159 msleep(pci_pm_d3_delay);
2164 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2167 struct pci_dev *pdev;
2169 if (dev->subordinate)
2172 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2179 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2180 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2181 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2184 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2185 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2191 static int pci_dev_reset(struct pci_dev *dev, int probe)
2198 pci_block_user_cfg_access(dev);
2199 /* block PM suspend, driver probe, etc. */
2200 down(&dev->dev.sem);
2203 rc = pcie_flr(dev, probe);
2207 rc = pci_af_flr(dev, probe);
2211 rc = pci_pm_reset(dev, probe);
2215 rc = pci_parent_bus_reset(dev, probe);
2219 pci_unblock_user_cfg_access(dev);
2226 * __pci_reset_function - reset a PCI device function
2227 * @dev: PCI device to reset
2229 * Some devices allow an individual function to be reset without affecting
2230 * other functions in the same device. The PCI device must be responsive
2231 * to PCI config space in order to use this function.
2233 * The device function is presumed to be unused when this function is called.
2234 * Resetting the device will make the contents of PCI configuration space
2235 * random, so any caller of this must be prepared to reinitialise the
2236 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2239 * Returns 0 if the device function was successfully reset or negative if the
2240 * device doesn't support resetting a single function.
2242 int __pci_reset_function(struct pci_dev *dev)
2244 return pci_dev_reset(dev, 0);
2246 EXPORT_SYMBOL_GPL(__pci_reset_function);
2249 * pci_reset_function - quiesce and reset a PCI device function
2250 * @dev: PCI device to reset
2252 * Some devices allow an individual function to be reset without affecting
2253 * other functions in the same device. The PCI device must be responsive
2254 * to PCI config space in order to use this function.
2256 * This function does not just reset the PCI portion of a device, but
2257 * clears all the state associated with the device. This function differs
2258 * from __pci_reset_function in that it saves and restores device state
2261 * Returns 0 if the device function was successfully reset or negative if the
2262 * device doesn't support resetting a single function.
2264 int pci_reset_function(struct pci_dev *dev)
2268 rc = pci_dev_reset(dev, 1);
2272 pci_save_state(dev);
2275 * both INTx and MSI are disabled after the Interrupt Disable bit
2276 * is set and the Bus Master bit is cleared.
2278 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2280 rc = pci_dev_reset(dev, 0);
2282 pci_restore_state(dev);
2286 EXPORT_SYMBOL_GPL(pci_reset_function);
2289 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2290 * @dev: PCI device to query
2292 * Returns mmrbc: maximum designed memory read count in bytes
2293 * or appropriate error value.
2295 int pcix_get_max_mmrbc(struct pci_dev *dev)
2300 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2304 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2308 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2310 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2313 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2314 * @dev: PCI device to query
2316 * Returns mmrbc: maximum memory read count in bytes
2317 * or appropriate error value.
2319 int pcix_get_mmrbc(struct pci_dev *dev)
2324 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2328 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2330 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2334 EXPORT_SYMBOL(pcix_get_mmrbc);
2337 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2338 * @dev: PCI device to query
2339 * @mmrbc: maximum memory read count in bytes
2340 * valid values are 512, 1024, 2048, 4096
2342 * If possible sets maximum memory read byte count, some bridges have erratas
2343 * that prevent this.
2345 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2347 int cap, err = -EINVAL;
2348 u32 stat, cmd, v, o;
2350 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2353 v = ffs(mmrbc) - 10;
2355 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2359 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2363 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2366 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2370 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2372 if (v > o && dev->bus &&
2373 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2376 cmd &= ~PCI_X_CMD_MAX_READ;
2378 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2383 EXPORT_SYMBOL(pcix_set_mmrbc);
2386 * pcie_get_readrq - get PCI Express read request size
2387 * @dev: PCI device to query
2389 * Returns maximum memory read request in bytes
2390 * or appropriate error value.
2392 int pcie_get_readrq(struct pci_dev *dev)
2397 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2401 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2403 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2407 EXPORT_SYMBOL(pcie_get_readrq);
2410 * pcie_set_readrq - set PCI Express maximum memory read request
2411 * @dev: PCI device to query
2412 * @rq: maximum memory read count in bytes
2413 * valid values are 128, 256, 512, 1024, 2048, 4096
2415 * If possible sets maximum read byte count
2417 int pcie_set_readrq(struct pci_dev *dev, int rq)
2419 int cap, err = -EINVAL;
2422 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2425 v = (ffs(rq) - 8) << 12;
2427 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2431 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2435 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2436 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2438 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2444 EXPORT_SYMBOL(pcie_set_readrq);
2447 * pci_select_bars - Make BAR mask from the type of resource
2448 * @dev: the PCI device for which BAR mask is made
2449 * @flags: resource type mask to be selected
2451 * This helper routine makes bar mask from the type of resource.
2453 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2456 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2457 if (pci_resource_flags(dev, i) & flags)
2463 * pci_resource_bar - get position of the BAR associated with a resource
2464 * @dev: the PCI device
2465 * @resno: the resource number
2466 * @type: the BAR type to be filled in
2468 * Returns BAR position in config space, or 0 if the BAR is invalid.
2470 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2474 if (resno < PCI_ROM_RESOURCE) {
2475 *type = pci_bar_unknown;
2476 return PCI_BASE_ADDRESS_0 + 4 * resno;
2477 } else if (resno == PCI_ROM_RESOURCE) {
2478 *type = pci_bar_mem32;
2479 return dev->rom_base_reg;
2480 } else if (resno < PCI_BRIDGE_RESOURCES) {
2481 /* device specific resource */
2482 reg = pci_iov_resource_bar(dev, resno, type);
2487 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2491 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2492 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2493 spinlock_t resource_alignment_lock = SPIN_LOCK_UNLOCKED;
2496 * pci_specified_resource_alignment - get resource alignment specified by user.
2497 * @dev: the PCI device to get
2499 * RETURNS: Resource alignment if it is specified.
2500 * Zero if it is not specified.
2502 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2504 int seg, bus, slot, func, align_order, count;
2505 resource_size_t align = 0;
2508 spin_lock(&resource_alignment_lock);
2509 p = resource_alignment_param;
2512 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2518 if (sscanf(p, "%x:%x:%x.%x%n",
2519 &seg, &bus, &slot, &func, &count) != 4) {
2521 if (sscanf(p, "%x:%x.%x%n",
2522 &bus, &slot, &func, &count) != 3) {
2523 /* Invalid format */
2524 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2530 if (seg == pci_domain_nr(dev->bus) &&
2531 bus == dev->bus->number &&
2532 slot == PCI_SLOT(dev->devfn) &&
2533 func == PCI_FUNC(dev->devfn)) {
2534 if (align_order == -1) {
2537 align = 1 << align_order;
2542 if (*p != ';' && *p != ',') {
2543 /* End of param or invalid format */
2548 spin_unlock(&resource_alignment_lock);
2553 * pci_is_reassigndev - check if specified PCI is target device to reassign
2554 * @dev: the PCI device to check
2556 * RETURNS: non-zero for PCI device is a target device to reassign,
2559 int pci_is_reassigndev(struct pci_dev *dev)
2561 return (pci_specified_resource_alignment(dev) != 0);
2564 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2566 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2567 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2568 spin_lock(&resource_alignment_lock);
2569 strncpy(resource_alignment_param, buf, count);
2570 resource_alignment_param[count] = '\0';
2571 spin_unlock(&resource_alignment_lock);
2575 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2578 spin_lock(&resource_alignment_lock);
2579 count = snprintf(buf, size, "%s", resource_alignment_param);
2580 spin_unlock(&resource_alignment_lock);
2584 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2586 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2589 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2590 const char *buf, size_t count)
2592 return pci_set_resource_alignment_param(buf, count);
2595 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2596 pci_resource_alignment_store);
2598 static int __init pci_resource_alignment_sysfs_init(void)
2600 return bus_create_file(&pci_bus_type,
2601 &bus_attr_resource_alignment);
2604 late_initcall(pci_resource_alignment_sysfs_init);
2606 static void __devinit pci_no_domains(void)
2608 #ifdef CONFIG_PCI_DOMAINS
2609 pci_domains_supported = 0;
2614 * pci_ext_cfg_enabled - can we access extended PCI config space?
2615 * @dev: The PCI device of the root bridge.
2617 * Returns 1 if we can access PCI extended config space (offsets
2618 * greater than 0xff). This is the default implementation. Architecture
2619 * implementations can override this.
2621 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2626 static int __devinit pci_init(void)
2628 struct pci_dev *dev = NULL;
2630 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2631 pci_fixup_device(pci_fixup_final, dev);
2637 static int __init pci_setup(char *str)
2640 char *k = strchr(str, ',');
2643 if (*str && (str = pcibios_setup(str)) && *str) {
2644 if (!strcmp(str, "nomsi")) {
2646 } else if (!strcmp(str, "noaer")) {
2648 } else if (!strcmp(str, "nodomains")) {
2650 } else if (!strncmp(str, "cbiosize=", 9)) {
2651 pci_cardbus_io_size = memparse(str + 9, &str);
2652 } else if (!strncmp(str, "cbmemsize=", 10)) {
2653 pci_cardbus_mem_size = memparse(str + 10, &str);
2654 } else if (!strncmp(str, "resource_alignment=", 19)) {
2655 pci_set_resource_alignment_param(str + 19,
2657 } else if (!strncmp(str, "ecrc=", 5)) {
2658 pcie_ecrc_get_policy(str + 5);
2660 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2668 early_param("pci", pci_setup);
2670 device_initcall(pci_init);
2672 EXPORT_SYMBOL(pci_reenable_device);
2673 EXPORT_SYMBOL(pci_enable_device_io);
2674 EXPORT_SYMBOL(pci_enable_device_mem);
2675 EXPORT_SYMBOL(pci_enable_device);
2676 EXPORT_SYMBOL(pcim_enable_device);
2677 EXPORT_SYMBOL(pcim_pin_device);
2678 EXPORT_SYMBOL(pci_disable_device);
2679 EXPORT_SYMBOL(pci_find_capability);
2680 EXPORT_SYMBOL(pci_bus_find_capability);
2681 EXPORT_SYMBOL(pci_release_regions);
2682 EXPORT_SYMBOL(pci_request_regions);
2683 EXPORT_SYMBOL(pci_request_regions_exclusive);
2684 EXPORT_SYMBOL(pci_release_region);
2685 EXPORT_SYMBOL(pci_request_region);
2686 EXPORT_SYMBOL(pci_request_region_exclusive);
2687 EXPORT_SYMBOL(pci_release_selected_regions);
2688 EXPORT_SYMBOL(pci_request_selected_regions);
2689 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2690 EXPORT_SYMBOL(pci_set_master);
2691 EXPORT_SYMBOL(pci_clear_master);
2692 EXPORT_SYMBOL(pci_set_mwi);
2693 EXPORT_SYMBOL(pci_try_set_mwi);
2694 EXPORT_SYMBOL(pci_clear_mwi);
2695 EXPORT_SYMBOL_GPL(pci_intx);
2696 EXPORT_SYMBOL(pci_set_dma_mask);
2697 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2698 EXPORT_SYMBOL(pci_assign_resource);
2699 EXPORT_SYMBOL(pci_find_parent_resource);
2700 EXPORT_SYMBOL(pci_select_bars);
2702 EXPORT_SYMBOL(pci_set_power_state);
2703 EXPORT_SYMBOL(pci_save_state);
2704 EXPORT_SYMBOL(pci_restore_state);
2705 EXPORT_SYMBOL(pci_pme_capable);
2706 EXPORT_SYMBOL(pci_pme_active);
2707 EXPORT_SYMBOL(pci_enable_wake);
2708 EXPORT_SYMBOL(pci_wake_from_d3);
2709 EXPORT_SYMBOL(pci_target_state);
2710 EXPORT_SYMBOL(pci_prepare_to_sleep);
2711 EXPORT_SYMBOL(pci_back_from_sleep);
2712 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);