2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/pci.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
93 struct dentry *debugfs_root;
94 struct dentry *debugfs_phy;
95 struct dentry *debugfs_dma;
98 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
99 int ath9k_init_debug(struct ath_softc *sc);
100 void ath9k_exit_debug(struct ath_softc *sc);
104 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
105 const char *fmt, ...)
109 static inline int ath9k_init_debug(struct ath_softc *sc)
114 static inline void ath9k_exit_debug(struct ath_softc *sc)
118 #endif /* CONFIG_ATH9K_DEBUG */
123 u16 txpowlimit_override;
128 /*************************/
129 /* Descriptor Management */
130 /*************************/
132 #define ATH_TXBUF_RESET(_bf) do { \
133 (_bf)->bf_status = 0; \
134 (_bf)->bf_lastbf = NULL; \
135 (_bf)->bf_lastfrm = NULL; \
136 (_bf)->bf_next = NULL; \
137 memset(&((_bf)->bf_state), 0, \
138 sizeof(struct ath_buf_state)); \
148 BUF_SHORT_PREAMBLE = BIT(6),
151 BUF_AGGR_BURST = BIT(9),
152 BUF_CALC_AIRTIME = BIT(10),
155 struct ath_buf_state {
156 int bfs_nframes; /* # frames in aggregate */
157 u16 bfs_al; /* length of aggregate */
158 u16 bfs_frmlen; /* length of frame */
159 int bfs_seqno; /* sequence number */
160 int bfs_tidno; /* tid of this frame */
161 int bfs_retries; /* current retries */
162 u32 bf_type; /* BUF_* (enum buffer_type) */
164 enum ath9k_key_type bfs_keytype;
167 #define bf_nframes bf_state.bfs_nframes
168 #define bf_al bf_state.bfs_al
169 #define bf_frmlen bf_state.bfs_frmlen
170 #define bf_retries bf_state.bfs_retries
171 #define bf_seqno bf_state.bfs_seqno
172 #define bf_tidno bf_state.bfs_tidno
173 #define bf_rcs bf_state.bfs_rcs
174 #define bf_keyix bf_state.bfs_keyix
175 #define bf_keytype bf_state.bfs_keytype
176 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
177 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
178 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
179 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
180 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
181 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
182 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
183 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
184 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
185 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
188 * Abstraction of a contiguous buffer to transmit/receive. There is only
189 * a single hw descriptor encapsulated here.
192 struct list_head list;
193 struct list_head *last;
194 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
196 struct ath_buf *bf_lastfrm; /* last buf of this frame */
197 struct ath_buf *bf_next; /* next subframe in the aggregate */
198 void *bf_mpdu; /* enclosing frame structure */
199 struct ath_desc *bf_desc; /* virtual addr of desc */
200 dma_addr_t bf_daddr; /* physical addr of desc */
201 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
203 u16 bf_flags; /* tx descriptor flags */
204 struct ath_buf_state bf_state; /* buffer state */
205 dma_addr_t bf_dmacontext;
208 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
210 /* hw processing complete, desc processed by hal */
211 #define ATH_BUFSTATUS_DONE 0x00000001
212 /* hw processing complete, desc hold for hw */
213 #define ATH_BUFSTATUS_STALE 0x00000002
214 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
215 #define ATH_BUFSTATUS_FREE 0x00000004
217 /* DMA state for tx/rx descriptors */
221 struct ath_desc *dd_desc; /* descriptors */
222 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
223 u32 dd_desc_len; /* size of dd_desc */
224 struct ath_buf *dd_bufptr; /* associated buffers */
225 dma_addr_t dd_dmacontext;
228 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
229 struct list_head *head, const char *name,
230 int nbuf, int ndesc);
231 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
232 struct list_head *head);
238 #define ATH_MAX_ANTENNA 3
239 #define ATH_RXBUF 512
240 #define WME_NUM_TID 16
242 int ath_startrecv(struct ath_softc *sc);
243 bool ath_stoprecv(struct ath_softc *sc);
244 void ath_flushrecv(struct ath_softc *sc);
245 u32 ath_calcrxfilter(struct ath_softc *sc);
246 int ath_rx_init(struct ath_softc *sc, int nbufs);
247 void ath_rx_cleanup(struct ath_softc *sc);
248 int ath_rx_tasklet(struct ath_softc *sc, int flush);
250 #define ATH_TXBUF 512
251 #define ATH_TXMAXTRY 13
252 #define ATH_11N_TXMAXTRY 10
253 #define ATH_MGT_TXMAXTRY 4
254 #define WME_BA_BMP_SIZE 64
255 #define WME_MAX_BA WME_BA_BMP_SIZE
256 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
257 #define TID_TO_WME_AC(_tid) \
258 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
259 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
260 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
271 u32 axq_qnum; /* hardware q number */
272 u32 *axq_link; /* link ptr in last TX desc */
273 struct list_head axq_q; /* transmit queue */
275 unsigned long axq_lockflags; /* intr state when must cli */
276 u32 axq_depth; /* queue depth */
277 u8 axq_aggr_depth; /* aggregates queued */
278 u32 axq_totalqueued; /* total ever queued */
280 bool stopped; /* Is mac80211 queue stopped ? */
281 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
283 /* first desc of the last descriptor that contains CTS */
284 struct ath_desc *axq_lastdsWithCTS;
286 /* final desc of the gating desc that determines whether
287 lastdsWithCTS has been DMA'ed or not */
288 struct ath_desc *axq_gatingds;
290 struct list_head axq_acq;
293 #define AGGR_CLEANUP BIT(1)
294 #define AGGR_ADDBA_COMPLETE BIT(2)
295 #define AGGR_ADDBA_PROGRESS BIT(3)
297 /* per TID aggregate tx state for a destination */
299 struct list_head list; /* round-robin tid entry */
300 struct list_head buf_q; /* pending buffers */
302 struct ath_atx_ac *ac;
303 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
308 int baw_head; /* first un-acked tx buffer */
309 int baw_tail; /* next unused tx buffer slot */
313 int addba_exchangeattempts;
316 /* per access-category aggregate tx state for a destination */
318 int sched; /* dest-ac is scheduled */
319 int qnum; /* H/W queue number associated
321 struct list_head list; /* round-robin txq entry */
322 struct list_head tid_q; /* queue of TIDs with buffers */
325 /* per dest tx state */
327 struct ath_atx_tid tid[WME_NUM_TID];
328 struct ath_atx_ac ac[WME_NUM_AC];
331 /* per-frame tx control block */
332 struct ath_tx_control {
337 /* per frame tx status block */
338 struct ath_xmit_status {
339 int retries; /* number of retries to successufully
340 transmit this frame */
341 int flags; /* status of transmit */
342 #define ATH_TX_ERROR 0x01
343 #define ATH_TX_XRETRY 0x02
344 #define ATH_TX_BAR 0x04
347 /* All RSSI values are noise floor adjusted */
350 int rssictl[ATH_MAX_ANTENNA];
351 int rssiextn[ATH_MAX_ANTENNA];
356 /* if any of ctl,extn chain rssis are valid */
357 #define ATH_TX_CHAIN_RSSI_VALID 0x01
358 /* if extn chain rssis are valid */
359 #define ATH_TX_RSSI_EXTN_VALID 0x02
360 u32 airtime; /* time on air per final tx rate */
363 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
364 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
365 int ath_tx_setup(struct ath_softc *sc, int haltype);
366 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
367 void ath_tx_draintxq(struct ath_softc *sc,
368 struct ath_txq *txq, bool retry_tx);
369 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
370 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
371 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
372 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
373 int ath_tx_init(struct ath_softc *sc, int nbufs);
374 int ath_tx_cleanup(struct ath_softc *sc);
375 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
376 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
377 int ath_txq_update(struct ath_softc *sc, int qnum,
378 struct ath9k_tx_queue_info *q);
379 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
380 struct ath_tx_control *txctl);
381 void ath_tx_tasklet(struct ath_softc *sc);
382 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
383 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
384 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
386 /**********************/
387 /* Node / Aggregation */
388 /**********************/
390 #define ADDBA_EXCHANGE_ATTEMPTS 10
391 #define ATH_AGGR_DELIM_SZ 4
392 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
393 /* number of delimiters for encryption padding */
394 #define ATH_AGGR_ENCRYPTDELIM 10
395 /* minimum h/w qdepth to be sustained to maximize aggregation */
396 #define ATH_AGGR_MIN_QDEPTH 2
397 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
398 #define IEEE80211_SEQ_SEQ_SHIFT 4
399 #define IEEE80211_SEQ_MAX 4096
400 #define IEEE80211_MIN_AMPDU_BUF 0x8
401 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
403 /* return whether a bit at index _n in bitmap _bm is set
404 * _sz is the size of the bitmap */
405 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
406 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
408 /* return block-ack bitmap index given sequence and starting sequence */
409 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
411 /* returns delimiter padding required given the packet length */
412 #define ATH_AGGR_GET_NDELIM(_len) \
413 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
414 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
416 #define BAW_WITHIN(_start, _bawsz, _seqno) \
417 ((((_seqno) - (_start)) & 4095) < (_bawsz))
419 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
420 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
421 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
422 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
424 enum ATH_AGGR_STATUS {
432 struct aggr_rifs_param {
433 int param_max_frames;
437 struct ath_rc_series *param_rcs;
440 /* Per-node aggregation state */
441 struct ath_node_aggr {
446 struct ath_softc *an_sc;
447 struct ath_node_aggr an_aggr;
452 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
453 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
454 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
455 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
457 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
458 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
465 * Define the scheme that we select MAC address for multiple
466 * BSS on the same radio. The very first VAP will just use the MAC
467 * address from the EEPROM. For the next 3 VAPs, we set the
468 * U/L bit (bit 1) in MAC address, and use the next two bits as the
472 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
473 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
477 enum nl80211_iftype av_opmode;
478 struct ath_buf *av_bcbuf;
479 struct ath_tx_control av_btxctl;
482 /*******************/
483 /* Beacon Handling */
484 /*******************/
487 * Regardless of the number of beacons we stagger, (i.e. regardless of the
488 * number of BSSIDs) if a given beacon does not go out even after waiting this
489 * number of beacon intervals, the game's up.
491 #define BSTUCK_THRESH (9 * ATH_BCBUF)
493 #define ATH_DEFAULT_BINTVAL 100 /* TU */
494 #define ATH_DEFAULT_BMISS_LIMIT 10
495 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
497 struct ath_beacon_config {
507 } u; /* last received beacon/probe response timestamp of this BSS. */
510 void ath9k_beacon_tasklet(unsigned long data);
511 void ath_beacon_config(struct ath_softc *sc, int if_id);
512 int ath_beaconq_setup(struct ath_hal *ah);
513 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
514 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
515 void ath_beacon_sync(struct ath_softc *sc, int if_id);
521 /* ANI values for STA only.
522 FIXME: Add appropriate values for AP later */
524 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
525 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
526 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
527 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
531 int16_t sc_noise_floor;
532 unsigned int sc_longcal_timer;
533 unsigned int sc_shortcal_timer;
534 unsigned int sc_resetcal_timer;
535 unsigned int sc_checkani_timer;
536 struct timer_list timer;
539 /********************/
541 /********************/
543 #define ATH_LED_PIN 1
553 struct ath_softc *sc;
554 struct led_classdev led_cdev;
555 enum ath_led_type led_type;
561 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
564 struct rfkill *rfkill;
565 struct delayed_work rfkill_poll;
566 char rfkill_name[32];
569 /********************/
570 /* Main driver core */
571 /********************/
574 * Default cache line size, in bytes.
575 * Used when PCI device not fully initialized by bootrom/BIOS
577 #define DEFAULT_CACHELINE 32
578 #define ATH_DEFAULT_NOISE_FLOOR -95
579 #define ATH_REGCLASSIDS_MAX 10
580 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
581 #define ATH_MAX_SW_RETRIES 10
582 #define ATH_CHAN_MAX 255
583 #define IEEE80211_WEP_NKID 4 /* number of key ids */
584 #define IEEE80211_RATE_VAL 0x7f
586 * The key cache is used for h/w cipher state and also for
587 * tracking station state such as the current tx antenna.
588 * We also setup a mapping table between key cache slot indices
589 * and station state to short-circuit node lookups on rx.
590 * Different parts have different size key caches. We handle
591 * up to ATH_KEYMAX entries (could dynamically allocate state).
593 #define ATH_KEYMAX 128 /* max key cache size we handle */
595 #define ATH_IF_ID_ANY 0xff
596 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
597 #define ATH_RSSI_DUMMY_MARKER 0x127
598 #define ATH_RATE_DUMMY_MARKER 0
606 #define SC_OP_INVALID BIT(0)
607 #define SC_OP_BEACONS BIT(1)
608 #define SC_OP_RXAGGR BIT(2)
609 #define SC_OP_TXAGGR BIT(3)
610 #define SC_OP_CHAINMASK_UPDATE BIT(4)
611 #define SC_OP_FULL_RESET BIT(5)
612 #define SC_OP_NO_RESET BIT(6)
613 #define SC_OP_PREAMBLE_SHORT BIT(7)
614 #define SC_OP_PROTECT_ENABLE BIT(8)
615 #define SC_OP_RXFLUSH BIT(9)
616 #define SC_OP_LED_ASSOCIATED BIT(10)
617 #define SC_OP_RFKILL_REGISTERED BIT(11)
618 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
619 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
622 struct ieee80211_hw *hw;
623 struct pci_dev *pdev;
624 struct tasklet_struct intr_tq;
625 struct tasklet_struct bcon_tasklet;
626 struct ath_config sc_config;
627 struct ath_hal *sc_ah;
630 u8 sc_curbssid[ETH_ALEN];
631 u8 sc_myaddr[ETH_ALEN];
632 u8 sc_bssidmask[ETH_ALEN];
634 #ifdef CONFIG_ATH9K_DEBUG
635 struct ath9k_debug sc_debug;
638 u32 sc_flags; /* SC_OP_* */
639 unsigned int rx_filter;
643 int sc_slotupdate; /* slot to next advance fsm */
645 int sc_bslot[ATH_BCBUF];
648 enum ath9k_int sc_imask;
649 enum wireless_mode sc_curmode;
650 enum PROT_MODE sc_protmode;
654 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
660 struct ath9k_node_stats sc_halstats;
661 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
662 enum ath9k_ht_macmode tx_chan_width;
664 #ifdef CONFIG_SLOW_ANT_DIV
665 struct ath_antdiv sc_antdiv;
668 OK, /* no change needed */
669 UPDATE, /* update pending */
670 COMMIT /* beacon sent, commit change */
671 } sc_updateslot; /* slot time update fsm */
675 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
676 u8 sc_splitmic; /* split TKIP MIC keys */
679 struct list_head sc_rxbuf;
680 struct ath_descdma sc_rxdma;
685 struct list_head sc_txbuf;
686 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
687 struct ath_descdma sc_txdma;
689 int sc_haltype2q[ATH9K_WME_AC_VO+1];
690 u16 seq_no; /* TX sequence number */
693 struct ath9k_tx_queue_info sc_beacon_qi;
694 struct ath_descdma sc_bdma;
695 struct ath_txq *sc_cabq;
696 struct list_head sc_bbuf;
703 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
704 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
708 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
709 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
712 spinlock_t sc_rxflushlock;
713 spinlock_t sc_rxbuflock;
714 spinlock_t sc_txbuflock;
715 spinlock_t sc_resetlock;
718 struct ath_led radio_led;
719 struct ath_led assoc_led;
720 struct ath_led tx_led;
721 struct ath_led rx_led;
724 struct ath_rfkill rf_kill;
727 struct ath_ani sc_ani;
730 int ath_reset(struct ath_softc *sc, bool retry_tx);
731 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
732 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
733 int ath_cabq_update(struct ath_softc *);