[Blackfin] arch: we no longer use BFIN_{SINGLE,DUAL}_CORE in our source

[linux-2.6] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index ba21e33..87c9a7e 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,16 +24,13 @@ config RWSEM_XCHGADD_ALGORITHM
 config BLACKFIN
        bool
        default y
+       select HAVE_IDE
        select HAVE_OPROFILE
 
 config ZONE_DMA
        bool
        default y
 
-config SEMAPHORE_SLEEPERS
-       bool
-       default y
-
 config GENERIC_FIND_NEXT_BIT
        bool
        default y
@@ -50,10 +47,6 @@ config GENERIC_IRQ_PROBE
        bool
        default y
 
-config GENERIC_TIME
-       bool
-       default n
-
 config GENERIC_GPIO
        bool
        default y
@@ -227,16 +220,6 @@ config BF54x
        depends on (BF542 || BF544 || BF547 || BF548 || BF549)
        default y
 
-config BFIN_DUAL_CORE
-       bool
-       depends on (BF561)
-       default y
-
-config BFIN_SINGLE_CORE
-       bool
-       depends on !BFIN_DUAL_CORE
-       default y
-
 config MEM_GENERIC_BOARD
        bool
        depends on GENERIC_BOARD
@@ -310,6 +293,18 @@ config BFIN_KERNEL_CLOCK
          are also not changed, and the Bootloader does 100% of the hardware
          configuration.
 
+config MEM_ADD_WIDTH
+       int "Memory Address Width"
+       depends on BFIN_KERNEL_CLOCK
+       depends on (!BF54x)
+       default  9 if BFIN533_EZKIT
+       default  9 if BFIN561_EZKIT
+       default  9 if H8606_HVSISTEMAS
+       default 10 if BFIN527_EZKIT
+       default 10 if BFIN537_STAMP
+       default 11 if BFIN533_STAMP
+       default 10 if PNAV10
+
 config PLL_BYPASS
        bool "Bypass PLL"
        depends on BFIN_KERNEL_CLOCK
@@ -418,6 +413,30 @@ comment "Kernel Timer/Scheduler"
 
 source kernel/Kconfig.hz
 
+config GENERIC_TIME
+       bool "Generic time"
+       default y
+
+config GENERIC_CLOCKEVENTS
+       bool "Generic clock events"
+       depends on GENERIC_TIME
+       default y
+
+config CYCLES_CLOCKSOURCE
+       bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
+       depends on EXPERIMENTAL
+       depends on GENERIC_CLOCKEVENTS
+       depends on !BFIN_SCRATCH_REG_CYCLES
+       default n
+       help
+         If you say Y here, you will enable support for using the 'cycles'
+         registers as a clock source.  Doing so means you will be unable to
+         safely write to the 'cycles' register during runtime.  You will
+         still be able to read it (such as for performance monitoring), but
+         writing the registers will most likely crash the kernel.
+
+source kernel/time/Kconfig
+
 comment "Memory Setup"
 
 config MEM_SIZE
@@ -431,18 +450,6 @@ config MEM_SIZE
        default  64 if PNAV10
        default  32 if H8606_HVSISTEMAS
 
-config MEM_ADD_WIDTH
-       int "SDRAM Memory Address Width"
-       depends on (!BF54x)
-       default  9 if BFIN533_EZKIT
-       default  9 if BFIN561_EZKIT
-       default  9 if H8606_HVSISTEMAS
-       default 10 if BFIN527_EZKIT
-       default 10 if BFIN537_STAMP
-       default 11 if BFIN533_STAMP
-       default 10 if PNAV10
-
-
 choice
        prompt "DDR SDRAM Chip Type"
        depends on BFIN548_EZKIT
@@ -544,7 +551,7 @@ config EXCPT_IRQ_SYSC_L1
        default y
        help
          If enabled, the entire ASM lowlevel exception and interrupt entry code
-         (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 
+         (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
          (less latency)
 
 config DO_IRQ_L1
@@ -904,29 +911,38 @@ config ARCH_SUSPEND_POSSIBLE
        depends on !SMP
 
 choice
-       prompt "Select PM Wakeup Event Source"
-       default PM_WAKEUP_GPIO_BY_SIC_IWR
+       prompt "Default Power Saving Mode"
        depends on PM
-       help
-         If you have a GPIO already configured as input with the corresponding PORTx_MASK
-         bit set - "Specify Wakeup Event by SIC_IWR value"
+       default PM_BFIN_SLEEP_DEEPER
+config  PM_BFIN_SLEEP_DEEPER
+       bool "Sleep Deeper"
+       help
+         Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
+         power dissipation by disabling the clock to the processor core (CCLK).
+         Furthermore, Standby sets the internal power supply voltage (VDDINT)
+         to 0.85 V to provide the greatest power savings, while preserving the
+         processor state.
+         The PLL and system clock (SCLK) continue to operate at a very low
+         frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
+         the SDRAM is put into Self Refresh Mode. Typically an external event
+         such as GPIO interrupt or RTC activity wakes up the processor.
+         Various Peripherals such as UART, SPORT, PPI may not function as
+         normal during Sleep Deeper, due to the reduced SCLK frequency.
+         When in the sleep mode, system DMA access to L1 memory is not supported.
+
+config  PM_BFIN_SLEEP
+       bool "Sleep"
+       help
+         Sleep Mode (High Power Savings) - The sleep mode reduces power
+         dissipation by disabling the clock to the processor core (CCLK).
+         The PLL and system clock (SCLK), however, continue to operate in
+         this mode. Typically an external event or RTC activity will wake
+         up the processor. When in the sleep mode,
+         system DMA access to L1 memory is not supported.
+endchoice
 
-config PM_WAKEUP_GPIO_BY_SIC_IWR
-       bool "Specify Wakeup Event by SIC_IWR value"
 config PM_WAKEUP_BY_GPIO
        bool "Cause Wakeup Event by GPIO"
-config PM_WAKEUP_GPIO_API
-       bool "Configure Wakeup Event by PM GPIO API"
-
-endchoice
-
-config PM_WAKEUP_SIC_IWR
-       hex "Wakeup Events (SIC_IWR)"
-       depends on PM_WAKEUP_GPIO_BY_SIC_IWR
-       default 0x8 if (BF537 || BF536 || BF534)
-       default 0x80 if (BF533 || BF532 || BF531)
-       default 0x80 if (BF54x)
-       default 0x80 if (BF52x)
 
 config PM_WAKEUP_GPIO_NUMBER
        int "Wakeup GPIO number"