net: Fix routing tables with id > 255 for legacy software
[linux-2.6] / include / asm-blackfin / mach-bf561 / defBF561.h
index a6de4c6..1ab50e9 100644 (file)
 #define PLL_LOCKCNT            0xFFC00010      /* PLL Lock Count register (16-bit) */
 #define CHIPID                 0xFFC00014       /* Chip ID Register */
 
+/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
+#define SWRST                   SICA_SWRST
+#define SYSCR                   SICA_SYSCR
+#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
+#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
+#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
+#define RESET_SOFTWARE          (SWRST_OCCURRED)
+
 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
 #define SICA_SWRST              0xFFC00100     /* Software Reset register */
 #define SICA_SYSCR              0xFFC00104     /* System Reset Configuration register */
 #define WDOGB_STAT                             0xFFC01208      /* Watchdog Status register */
 
 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR               0xFFC00400      /* Transmit Holding register */
-#define UART_RBR               0xFFC00400      /* Receive Buffer register */
-#define UART_DLL               0xFFC00400      /* Divisor Latch (Low-Byte) */
-#define UART_IER               0xFFC00404      /* Interrupt Enable Register */
-#define UART_DLH               0xFFC00404      /* Divisor Latch (High-Byte) */
-#define UART_IIR               0xFFC00408      /* Interrupt Identification Register */
-#define UART_LCR               0xFFC0040C      /* Line Control Register */
-#define UART_MCR                               0xFFC00410      /* Modem Control Register */
-#define UART_LSR               0xFFC00414      /* Line Status Register */
-#define UART_MSR               0xFFC00418      /* Modem Status Register */
-#define UART_SCR               0xFFC0041C      /* SCR Scratch Register */
-#define UART_GCTL                      0xFFC00424      /* Global Control Register */
+
+/*
+ * Because include/linux/serial_reg.h have defined UART_*,
+ * So we define blackfin uart regs to BFIN_UART0_*.
+ */
+#define BFIN_UART_THR                  0xFFC00400  /* Transmit Holding register */
+#define BFIN_UART_RBR                  0xFFC00400  /* Receive Buffer register */
+#define BFIN_UART_DLL                  0xFFC00400  /* Divisor Latch (Low-Byte) */
+#define BFIN_UART_IER                  0xFFC00404  /* Interrupt Enable Register */
+#define BFIN_UART_DLH                  0xFFC00404  /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR                  0xFFC00408  /* Interrupt Identification Register */
+#define BFIN_UART_LCR                  0xFFC0040C  /* Line Control Register */
+#define BFIN_UART_MCR                  0xFFC00410  /* Modem Control Register */
+#define BFIN_UART_LSR                  0xFFC00414  /* Line Status Register */
+#define BFIN_UART_MSR                  0xFFC00418  /* Modem Status Register */
+#define BFIN_UART_SCR                  0xFFC0041C  /* SCR Scratch Register */
+#define BFIN_UART_GCTL                 0xFFC00424  /* Global Control Register */
 
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE                   0xFFC00500
 #define SPI_CTL                        0xFFC00500      /* SPI Control Register */
 #define SPI_FLG                        0xFFC00504      /* SPI Flag register */
 #define SPI_STAT                       0xFFC00508      /* SPI Status register */
 #define CHIPID_FAMILY          0x0FFFF000
 #define CHIPID_MANUFACTURE     0x00000FFE
 
+/* VR_CTL Masks                                                                                                                                        */
+#define        FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define        HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
+#define        FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define        FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define        FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+
+#define        GAIN                    0x000C  /* Voltage Level Gain   */
+#define        GAIN_5                  0x0000  /* GAIN = 5*/
+#define        GAIN_10                 0x0004  /* GAIN = 1*/
+#define        GAIN_20                 0x0008  /* GAIN = 2*/
+#define        GAIN_50                 0x000C  /* GAIN = 5*/
+
+#define        VLEV                    0x00F0  /* Internal Voltage Level */
+#define        VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define        VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define        VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define        VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define        VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define        VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define        VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define        VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define        VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define        VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+#define        WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define        SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
 /* PLL_DIV Masks */
 #define SCLK_DIV(x)  (x)       /* SCLK = VCO / x */
 
+#define CSEL                   0x30            /* Core Select */
+#define SSEL                   0xf             /* System Select */
 #define CCLK_DIV1              0x00000000      /* CCLK = VCO / 1 */
 #define CCLK_DIV2              0x00000010      /* CCLK = VCO / 2 */
 #define CCLK_DIV4              0x00000020      /* CCLK = VCO / 4 */
 #define        PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007      /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B      0x00000800      /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A      0x00001000      /* SWRST Core A Double Fault */
-#define SWRST_WDT_B                   0x00002000       /* SWRST Watchdog B */
-#define SWRST_WDT_A                   0x00004000       /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x00008000      /* SWRST Status */
+#define SYSTEM_RESET           0x0007  /* Initiates a system software reset */
+#define DOUBLE_FAULT_A         0x0008  /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B         0x0010  /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A      0x0800  /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B      0x1000  /* SWRST Core B Double Fault */
+#define SWRST_WDT_B                   0x2000   /* SWRST Watchdog B */
+#define SWRST_WDT_A                   0x4000   /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x8000  /* SWRST Status */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
 
 #define IWR_ENABLE(x)         (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))       /* Wakeup Disable Peripheral #x */
 
-/* *********  WATCHDOG TIMER MASKS  ********************8 */
-
-/* Watchdog Timer WDOG_CTL Register */
-#define ICTL(x) ((x<<1) & 0x0006)
-#define ENABLE_RESET     0x00000000    /* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI       0x00000002    /* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI       0x00000004    /* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT      0x00000006    /* Disable Watchdog Timer interrupts */
-
-#define TMR_EN         0x0000
-#define TMR_DIS                0x0AD0
-#define TRO            0x8000
-
-#define ICTL_P0                0x01
-#define ICTL_P1                0x02
-#define TRO_P          0x0F
-
 /* ***************************** UART CONTROLLER MASKS ********************** */
 
 /* UART_LCR Register */
 #define TIMIL9         0x0002
 #define TIMIL10                0x0004
 #define TIMIL11                0x0008
-#define TOVL_ERR0      0x00000010
-#define TOVL_ERR1      0x00000020
-#define TOVL_ERR2      0x00000040
-#define TOVL_ERR3      0x00000080
-#define TOVL_ERR4      0x00100000
-#define TOVL_ERR5      0x00200000
-#define TOVL_ERR6      0x00400000
-#define TOVL_ERR7      0x00800000
-#define TOVL_ERR8      0x0010
-#define TOVL_ERR9      0x0020
-#define TOVL_ERR10     0x0040
-#define TOVL_ERR11     0x0080
+#define TOVF_ERR0      0x00000010
+#define TOVF_ERR1      0x00000020
+#define TOVF_ERR2      0x00000040
+#define TOVF_ERR3      0x00000080
+#define TOVF_ERR4      0x00100000
+#define TOVF_ERR5      0x00200000
+#define TOVF_ERR6      0x00400000
+#define TOVF_ERR7      0x00800000
+#define TOVF_ERR8      0x0010
+#define TOVF_ERR9      0x0020
+#define TOVF_ERR10     0x0040
+#define TOVF_ERR11     0x0080
 #define TRUN0          0x00001000
 #define TRUN1          0x00002000
 #define TRUN2          0x00004000
 #define TIMIL9_P       0x01
 #define TIMIL10_P      0x02
 #define TIMIL11_P      0x03
-#define TOVL_ERR0_P    0x04
-#define TOVL_ERR1_P    0x05
-#define TOVL_ERR2_P    0x06
-#define TOVL_ERR3_P    0x07
-#define TOVL_ERR4_P    0x14
-#define TOVL_ERR5_P    0x15
-#define TOVL_ERR6_P    0x16
-#define TOVL_ERR7_P    0x17
-#define TOVL_ERR8_P    0x04
-#define TOVL_ERR9_P    0x05
-#define TOVL_ERR10_P   0x06
-#define TOVL_ERR11_P   0x07
+#define TOVF_ERR0_P    0x04
+#define TOVF_ERR1_P    0x05
+#define TOVF_ERR2_P    0x06
+#define TOVF_ERR3_P    0x07
+#define TOVF_ERR4_P    0x14
+#define TOVF_ERR5_P    0x15
+#define TOVF_ERR6_P    0x16
+#define TOVF_ERR7_P    0x17
+#define TOVF_ERR8_P    0x04
+#define TOVF_ERR9_P    0x05
+#define TOVF_ERR10_P   0x06
+#define TOVF_ERR11_P   0x07
 #define TRUN0_P                0x0C
 #define TRUN1_P                0x0D
 #define TRUN2_P                0x0E
 #define TRUN10_P       0x0E
 #define TRUN11_P       0x0F
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+#define TOVL_ERR8 TOVF_ERR8
+#define TOVL_ERR9 TOVF_ERR9
+#define TOVL_ERR10 TOVF_ERR10
+#define TOVL_ERR11 TOVF_ERR11
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+#define TOVL_ERR3_P TOVF_ERR3_P
+#define TOVL_ERR4_P TOVF_ERR4_P
+#define TOVL_ERR5_P TOVF_ERR5_P
+#define TOVL_ERR6_P TOVF_ERR6_P
+#define TOVL_ERR7_P TOVF_ERR7_P
+#define TOVL_ERR8_P TOVF_ERR8_P
+#define TOVL_ERR9_P TOVF_ERR9_P
+#define TOVL_ERR10_P TOVF_ERR10_P
+#define TOVL_ERR11_P TOVF_ERR11_P
+
 /* TIMERx_CONFIG Registers */
 #define PWM_OUT                0x0001
 #define WDTH_CAP       0x0002
 #define SDEASE             0x00000010  /* SDRAM EAB sticky error status - W1C */
 #define BGSTAT                 0x00000020      /* Bus granted */
 
-/*VR_CTL Masks*/
-#define WAKE                    0x100
-#define VLEV_6                  0x60
-#define VLEV_7                  0x70
-#define VLEV_8                  0x80
-#define VLEV_9                  0x90
-#define VLEV_10                 0xA0
-#define VLEV_11                 0xB0
-#define VLEV_12                 0xC0
-#define VLEV_13                 0xD0
-#define VLEV_14                 0xE0
-#define VLEV_15                 0xF0
-#define FREQ_3                  0x03
-
 #endif                         /* _DEF_BF561_H */