OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
authorPaul Walmsley <paul@pwsan.com>
Sat, 20 Jun 2009 01:08:24 +0000 (19:08 -0600)
committerpaul <paul@twilight.(none)>
Sat, 20 Jun 2009 01:09:30 +0000 (19:09 -0600)
commit6adb8f388ef2f23d4a81e1e42d15f22d62749a06
tree217206b7b4751b6644e3cbe91cfff8e4df861e48
parentcd07ecc828486e5887113c7dc4d9f9022145811b
OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider.  This does not appear
to be necessary.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/sram34xx.S