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(parent: c947a58) | patch
xtensa: enforce slab alignment to maximum register width
authorOskar Schirmer <os@emlix.com>
Wed, 4 Mar 2009 15:21:30 +0000 (16:21 +0100)
committerChris Zankel <chris@zankel.net>
Fri, 3 Apr 2009 06:41:16 +0000 (23:41 -0700)
commita81cbd2da48eacc860acf4f40ea05db790f4c7c3
treee6d8b940bfa97afebb713a01ad96e31b6ca0de48tree | snapshot
parentc947a585ab13f310c9223284dfd502790abd05f9commit | diff
xtensa: enforce slab alignment to maximum register width

XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now.  But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
arch/xtensa/include/asm/processor.h diff | blob | blame | history
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