From 267c0eef02f5e2a48217235d170a0530de6a94d3 Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Tue, 14 Oct 2008 23:58:11 +0100 Subject: [PATCH] Name crtc index regs according to rules.xml --- src/nv_bios.c | 28 +++--- src/nv_crtc.c | 255 ++++++++++++++++++++++++------------------------ src/nv_driver.c | 12 +-- src/nv_hw.c | 92 ++++++++--------- src/nv_output.c | 22 ++--- src/nv_setup.c | 28 +++--- src/nvreg.h | 124 ++++++++++++----------- 7 files changed, 279 insertions(+), 282 deletions(-) diff --git a/src/nv_bios.c b/src/nv_bios.c index 847fef4..246d7c3 100644 --- a/src/nv_bios.c +++ b/src/nv_bios.c @@ -35,8 +35,8 @@ /* FIXME: put these somewhere */ #define SEQ_INDEX VGA_SEQ_INDEX -#define NV_VGA_CRTCX_OWNER_HEADA 0x0 -#define NV_VGA_CRTCX_OWNER_HEADB 0x3 +#define NV_CIO_CRE_44_HEADA 0x0 +#define NV_CIO_CRE_44_HEADB 0x3 #define FEATURE_MOBILE 0x10 //#define BIOSLOG(sip, fmt, arg...) xf86DrvMsg(sip->scrnIndex, X_INFO, fmt, ##arg) @@ -385,12 +385,12 @@ static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint return; /* The current head is maintained in a file scope variable crtchead. - * We trap changes to CRTCX_OWNER and update the head variable - * and hence the register set written. - * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0 - * in advance of the write, and to head1 after the write + * We trap changes to CR44 and update the head variable and hence the + * register set written. + * As CR44 only exists on CRTC0, we update crtchead to head0 in advance + * of the write, and to head1 after the write */ - if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB) + if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data != NV_CIO_CRE_44_HEADB) crtchead = 0; LOG_OLD_VALUE(nv_idx_port_rd(pScrn, port, index)); @@ -405,7 +405,7 @@ static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint NVWriteVgaCrtc(pNv, crtchead, index, data); } - if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB) + if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) crtchead = 1; } @@ -1887,7 +1887,7 @@ static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, /* no iexec->execute check by design */ - uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4); + uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; uint32_t reg, data; @@ -1939,7 +1939,7 @@ static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, /* no iexec->execute check by design */ - uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4); + uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); int clock; if (bios->major_version > 2) @@ -1975,7 +1975,7 @@ static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t off if (bios->major_version > 2) return false; - nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4, cr3c); + nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX, cr3c); return true; } @@ -2732,8 +2732,8 @@ static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, struct dc init_exec_t iexec = {true, false}; xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr); - nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, - head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA); + nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_44, + head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); NVWriteVgaCrtc5758(NVPTR(pScrn), head, 0, dcbent->index); parse_init_table(pScrn, bios, scriptptr, &iexec); @@ -3465,7 +3465,7 @@ bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pl if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) || ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { - if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_REVISION) < 0xa3) + if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) pll_lim->refclk = 200000; else pll_lim->refclk = 25000; diff --git a/src/nv_crtc.c b/src/nv_crtc.c index c02725b..3b5c088 100644 --- a/src/nv_crtc.c +++ b/src/nv_crtc.c @@ -185,17 +185,17 @@ static void nv_crtc_cursor_set(xf86CrtcPtr crtc) else cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset; - CRTC[NV_VGA_CRTCX_CURCTL0] = cursor_start >> 17; + CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17; if (pNv->Architecture != NV_ARCH_04) - CRTC[NV_VGA_CRTCX_CURCTL0] |= 0x80; - CRTC[NV_VGA_CRTCX_CURCTL1] = (cursor_start >> 11) << 2; + CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= 0x80; + CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2; if (crtc->mode.Flags & V_DBLSCAN) - CRTC[NV_VGA_CRTCX_CURCTL1] |= 2; - CRTC[NV_VGA_CRTCX_CURCTL2] = cursor_start >> 24; + CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 2; + CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24; - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, CRTC[NV_VGA_CRTCX_CURCTL0]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, CRTC[NV_VGA_CRTCX_CURCTL1]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, CRTC[NV_VGA_CRTCX_CURCTL2]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]); if (pNv->Architecture == NV_ARCH_40) nv_fix_nv40_hw_cursor(pNv, nv_crtc->head); } @@ -294,10 +294,10 @@ static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int do } else nv30UpdateArbitrationSettings(&arbitration0, &arbitration1); - regp->CRTC[NV_VGA_CRTCX_FIFO0] = arbitration0; - regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = arbitration1 & 0xff; + regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0; + regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff; if (pNv->Architecture >= NV_ARCH_30) - regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = arbitration1 >> 8; + regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8; nv_crtc_cursor_set(crtc); } @@ -321,7 +321,7 @@ nv_crtc_dpms(xf86CrtcPtr crtc, int mode) if (pNv->twoHeads) NVSetOwner(pNv, nv_crtc->head); - crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0; + crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0; switch(mode) { case DPMSModeStandby: /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ @@ -353,12 +353,12 @@ nv_crtc_dpms(xf86CrtcPtr crtc, int mode) /* Each head has it's own sequencer, so we can turn it off when we want */ seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20); NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1); - crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80); + crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80); usleep(10000); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17); NVVgaSeqReset(pNv, nv_crtc->head, false); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A); } static Bool @@ -476,16 +476,16 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus /* * CRTC Controller */ - regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal); - regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay); - regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart); - regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0) + regp->CRTC[NV_CIO_CR_HDT_INDEX] = Set8Bits(horizTotal); + regp->CRTC[NV_CIO_CR_HDE_INDEX] = Set8Bits(horizDisplay); + regp->CRTC[NV_CIO_CR_HBS_INDEX] = Set8Bits(horizBlankStart); + regp->CRTC[NV_CIO_CR_HBE_INDEX] = SetBitField(horizBlankEnd,4:0,4:0) | SetBit(7); - regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart); - regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7) + regp->CRTC[NV_CIO_CR_HRS_INDEX] = Set8Bits(horizStart); + regp->CRTC[NV_CIO_CR_HRE_INDEX] = SetBitField(horizBlankEnd,5:5,7:7) | SetBitField(horizEnd,4:0,4:0); - regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0); - regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0) + regp->CRTC[NV_CIO_CR_VDT_INDEX] = SetBitField(vertTotal,7:0,7:0); + regp->CRTC[NV_CIO_CR_OVL_INDEX] = SetBitField(vertTotal,8:8,0:0) | SetBitField(vertDisplay,8:8,1:1) | SetBitField(vertStart,8:8,2:2) | SetBitField(vertBlankStart,8:8,3:3) @@ -493,58 +493,57 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus | SetBitField(vertTotal,9:9,5:5) | SetBitField(vertDisplay,9:9,6:6) | SetBitField(vertStart,9:9,7:7); - regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00; - regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5) + regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; + regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = SetBitField(vertBlankStart,9:9,5:5) | SetBit(6) | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00); - regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00; - regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00; - regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00; - regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00; + regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; + regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; + regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; + regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; regp->CRTC[0xe] = 0x00; regp->CRTC[0xf] = 0x00; - regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart); + regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart); /* What is the meaning of bit5, it is empty in the vga spec. */ - regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5); - regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay); + regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5); + regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay); /* framebuffer can be larger than crtc scanout area. */ - regp->CRTC[NV_VGA_CRTCX_PITCHL] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8; - regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00; - regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart); - regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd); - /* 0x80 enables the sequencer, we don't want that */ - regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80; - regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff; + regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8; + regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; + regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart); + regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd); + regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; + regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; /* * Some extended CRTC registers (they are not saved with the rest of the vga regs). */ /* framebuffer can be larger than crtc scanout area. */ - regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3; - regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00; - regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4) + regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3; + regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00; + regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4) | SetBitField(vertBlankStart,10:10,3:3) | SetBitField(vertStart,10:10,2:2) | SetBitField(vertDisplay,10:10,1:1) | SetBitField(vertTotal,10:10,0:0); - regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0) + regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0) | SetBitField(horizDisplay,8:8,1:1) | SetBitField(horizBlankStart,8:8,2:2) | SetBitField(horizStart,8:8,3:3); - regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0) + regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0) | SetBitField(vertDisplay,11:11,2:2) | SetBitField(vertStart,11:11,4:4) | SetBitField(vertBlankStart,11:11,6:6); if(mode->Flags & V_INTERLACE) { horizTotal = (horizTotal >> 1) & ~1; - regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal); - regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4); + regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal); + regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4); } else - regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */ + regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ /* * Graphics Display Controller @@ -617,17 +616,17 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode) /* bit2 = 0 -> fine pitched crtc granularity */ /* The rest disables double buffering on CRTC access */ - regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa; + regp->CRTC[NV_CIO_CRE_21] = 0xfa; /* the blob sometimes sets |= 0x10 (which is the same as setting |= * 1 << 30 on 0x60.830), for no apparent reason */ - regp->CRTC[NV_VGA_CRTCX_59] = 0x0; + regp->CRTC[NV_CIO_CRE_59] = 0x0; if (tmds_output && pNv->Architecture < NV_ARCH_40) - regp->CRTC[NV_VGA_CRTCX_59] |= 0x1; + regp->CRTC[NV_CIO_CRE_59] |= 0x1; /* What is the meaning of this register? */ /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ - regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5); + regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); regp->head = 0; /* Except for rare conditions I2C is enabled on the primary crtc */ @@ -654,26 +653,26 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode) regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES; /* Unblock some timings */ - regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0; - regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0; + regp->CRTC[NV_CIO_CRE_53] = 0; + regp->CRTC[NV_CIO_CRE_54] = 0; /* What is the purpose of this register? */ /* 0x14 may be disabled? */ - regp->CRTC[NV_VGA_CRTCX_26] = 0x20; + regp->CRTC[NV_CIO_CR_ARX_INDEX] = 0x20; /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ if (lvds_output) - regp->CRTC[NV_VGA_CRTCX_3B] = 0x11; + regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; else if (tmds_output) - regp->CRTC[NV_VGA_CRTCX_3B] = 0x88; + regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; else - regp->CRTC[NV_VGA_CRTCX_3B] = 0x22; + regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; /* These values seem to vary */ /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ - regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4]; + regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; - regp->CRTC[NV_VGA_CRTCX_45] = 0x80; + regp->CRTC[NV_CIO_CRE_CSB] = 0x80; /* What does this do?: * bit0: crtc0 @@ -681,18 +680,18 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode) * bit7: (only in X) */ if (nv_crtc->head == 0) - regp->CRTC[NV_VGA_CRTCX_4B] = 0x81; + regp->CRTC[NV_CIO_CRE_4B] = 0x81; else - regp->CRTC[NV_VGA_CRTCX_4B] = 0x80; + regp->CRTC[NV_CIO_CRE_4B] = 0x80; if (lvds_output) - regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40; + regp->CRTC[NV_CIO_CRE_4B] |= 0x40; /* The blob seems to take the current value from crtc 0, add 4 to that * and reuse the old value for crtc 1 */ - regp->CRTC[NV_VGA_CRTCX_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_VGA_CRTCX_52]; + regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52]; if (!nv_crtc->head) - regp->CRTC[NV_VGA_CRTCX_52] += 4; + regp->CRTC[NV_CIO_CRE_52] += 4; regp->unk830 = mode->CrtcVDisplay - 3; regp->unk834 = mode->CrtcVDisplay - 1; @@ -711,14 +710,14 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode) /* Some misc regs */ if (pNv->Architecture == NV_ARCH_40) { - regp->CRTC[NV_VGA_CRTCX_85] = 0xFF; - regp->CRTC[NV_VGA_CRTCX_86] = 0x1; + regp->CRTC[NV_CIO_CRE_85] = 0xFF; + regp->CRTC[NV_CIO_CRE_86] = 0x1; } - regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pScrn->depth + 1) / 8; + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8; /* Enable slaved mode */ if (lvds_output || tmds_output) - regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7); + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); /* Generic PRAMDAC regs */ @@ -960,9 +959,9 @@ nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, { unsigned char tmp; - tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING); + tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR); tmp |= (1 << 7); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp); } #endif } @@ -985,7 +984,7 @@ static void nv_crtc_save(xf86CrtcPtr crtc) /* init some state to saved value */ pNv->ModeReg.reg580 = pNv->SavedReg.reg580; pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16); - pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]; + pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX]; } static void nv_crtc_restore(xf86CrtcPtr crtc) @@ -1374,7 +1373,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) if (pNv->Architecture >= NV_ARCH_10) { if (pNv->twoHeads) - /* setting FSEL *must* come before CRTCX_LCD, as writing CRTCX_LCD sets some + /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */ NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head); @@ -1388,7 +1387,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1); nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21, regp->CRTC[NV_CIO_CRE_21]); NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig); NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830); NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834); @@ -1409,45 +1408,45 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config); NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX, regp->CRTC[NV_CIO_CRE_RPC0_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, regp->CRTC[NV_CIO_CRE_RPC1_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX, regp->CRTC[NV_CIO_CRE_LSR_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX, regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, regp->CRTC[NV_CIO_CRE_LCD__INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX, regp->CRTC[NV_CIO_CRE_HEB__INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX, regp->CRTC[NV_CIO_CRE_ENH_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX, regp->CRTC[NV_CIO_CRE_FF_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX, regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]); if (pNv->Architecture >= NV_ARCH_30) - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47, regp->CRTC[NV_CIO_CRE_47]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]); if (pNv->Architecture == NV_ARCH_40) nv_fix_nv40_hw_cursor(pNv, nv_crtc->head); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX, regp->CRTC[NV_CIO_CR_ARX_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]); if (pNv->Architecture >= NV_ARCH_10) { - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX, regp->CRTC[NV_CIO_CRE_EBR_INDEX]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB, regp->CRTC[NV_CIO_CRE_CSB]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B, regp->CRTC[NV_CIO_CRE_4B]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52, regp->CRTC[NV_CIO_CRE_52]); } /* NV11 and NV20 stop at 0x52. */ if (pNv->NVArch >= 0x17 && pNv->twoHeads) { - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53, regp->CRTC[NV_CIO_CRE_53]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54, regp->CRTC[NV_CIO_CRE_54]); for (i = 0; i < 0x10; i++) NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59, regp->CRTC[NV_CIO_CRE_59]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85, regp->CRTC[NV_CIO_CRE_85]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86, regp->CRTC[NV_CIO_CRE_86]); } NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start); @@ -1492,23 +1491,23 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) regp = &state->crtc_reg[nv_crtc->head]; - regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD); - regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0); - regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1); - regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR); - regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL); - regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB); - regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1); - - regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0); - regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM); - regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER); + regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX); + regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX); + regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX); + regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX); + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX); + regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX); + regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX); + + regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX); + regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX); + regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21); if (pNv->Architecture >= NV_ARCH_30) - regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30); - regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0); - regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1); - regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2); - regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE); + regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47); + regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX); + regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX); + regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX); + regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX); if (pNv->Architecture >= NV_ARCH_10) { regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830); @@ -1519,7 +1518,7 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) } if (pNv->twoHeads) { regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL); - regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER); + regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_44); } regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG); } @@ -1527,26 +1526,26 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO); regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG); - regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26); - regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B); - regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4); + regp->CRTC[NV_CIO_CR_ARX_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX); + regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX); + regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX); if (pNv->Architecture >= NV_ARCH_10) { - regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA); - regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45); - regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B); - regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52); + regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX); + regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB); + regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B); + regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52); } /* NV11 and NV20 don't have this, they stop at 0x52. */ if (pNv->NVArch >= 0x17 && pNv->twoHeads) { for (i = 0; i < 0x10; i++) regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i); - regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59); - regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING); - regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING); + regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59); + regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53); + regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54); - regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85); - regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86); + regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85); + regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86); } regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START); diff --git a/src/nv_driver.c b/src/nv_driver.c index 336a771..09b4d21 100644 --- a/src/nv_driver.c +++ b/src/nv_driver.c @@ -1697,7 +1697,7 @@ NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode) NVLockUnlock(pScrn, 0); if(pNv->twoHeads) { - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, nvReg->crtcOwner); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, nvReg->crtcOwner); NVLockUnlock(pScrn, 0); } @@ -1711,9 +1711,9 @@ NVModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode) { unsigned char tmp; - tmp = nvReadCurVGA(pNv, NV_VGA_CRTCX_SWAPPING); + tmp = nvReadCurVGA(pNv, NV_CIO_CRE_RCR); tmp |= (1 << 7); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_SWAPPING, tmp); + nvWriteCurVGA(pNv, NV_CIO_CRE_RCR, tmp); } #endif @@ -1762,7 +1762,7 @@ NVRestore(ScrnInfoPtr pScrn) NVLockUnlock(pScrn, 0); if(pNv->twoHeads) { - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->crtc_active[1] * 0x3); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, pNv->crtc_active[1] * 0x3); NVLockUnlock(pScrn, 0); } @@ -1776,7 +1776,7 @@ NVRestore(ScrnInfoPtr pScrn) NVSetOwner(pNv, 0); /* move to head A to set owner */ NVLockVgaCrtc(pNv, 0, false); xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring CRTC_OWNER to %d.\n", pNv->vtOWNER); - NVWriteVgaCrtc(pNv, 0, NV_VGA_CRTCX_OWNER, pNv->vtOWNER); + NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_44, pNv->vtOWNER); NVLockVgaCrtc(pNv, 0, true); } } @@ -2231,7 +2231,7 @@ NVSave(ScrnInfoPtr pScrn) vgaRegPtr vgaReg = &pVga->SavedReg; NVLockUnlock(pScrn, 0); if (pNv->twoHeads) { - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->crtc_active[1] * 0x3); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, pNv->crtc_active[1] * 0x3); NVLockUnlock(pScrn, 0); } diff --git a/src/nv_hw.c b/src/nv_hw.c index ca58851..21733c5 100644 --- a/src/nv_hw.c +++ b/src/nv_hw.c @@ -130,14 +130,14 @@ uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index) void NVWriteVgaCrtc5758(NVPtr pNv, int head, uint8_t index, uint8_t value) { - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_57, index); - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_58, value); + NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index); + NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_58, value); } uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index) { - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_57, index); - return NVReadVgaCrtc(pNv, head, NV_VGA_CRTCX_58); + NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index); + return NVReadVgaCrtc(pNv, head, NV_CIO_CRE_58); } uint8_t NVReadPVIO(NVPtr pNv, int head, uint16_t port) @@ -252,22 +252,22 @@ void NVVgaProtect(NVPtr pNv, int head, bool protect) void NVSetOwner(NVPtr pNv, int head) { - /* CRTCX_OWNER is always changed on CRTC0 */ - NVWriteVgaCrtc(pNv, 0, NV_VGA_CRTCX_OWNER, head * 0x3); + /* CR44 is always changed on CRTC0 */ + NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_44, head * 0x3); } void NVLockVgaCrtc(NVPtr pNv, int head, bool lock) { uint8_t cr11; - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57); + NVWriteVgaCrtc(pNv, head, NV_CIO_SR_LOCK_INDEX, lock ? 0x99 : 0x57); - cr11 = NVReadVgaCrtc(pNv, head, NV_VGA_CRTCX_VSYNCE); + cr11 = NVReadVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX); if (lock) cr11 |= 0x80; else cr11 &= ~0x80; - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_VSYNCE, cr11); + NVWriteVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX, cr11); } void NVBlankScreen(NVPtr pNv, int head, bool blank) @@ -300,12 +300,12 @@ void nv_fix_nv40_hw_cursor(NVPtr pNv, int head) void nv_show_cursor(NVPtr pNv, int head, bool show) { - int curctl1 = NVReadVgaCrtc(pNv, head, NV_VGA_CRTCX_CURCTL1); + int curctl1 = NVReadVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX); if (show) - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_CURCTL1, curctl1 | 1); + NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, curctl1 | 1); else - NVWriteVgaCrtc(pNv, head, NV_VGA_CRTCX_CURCTL1, curctl1 & ~1); + NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, curctl1 & ~1); if (pNv->Architecture == NV_ARCH_40) nv_fix_nv40_hw_cursor(pNv, head); @@ -996,34 +996,34 @@ void NVLoadStateExt ( nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FP_HTIMING, state->timingH); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FP_VTIMING, state->timingV); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_BUFFER, 0xfa); + nvWriteCurVGA(pNv, NV_CIO_CRE_53, state->timingH); + nvWriteCurVGA(pNv, NV_CIO_CRE_54, state->timingV); + nvWriteCurVGA(pNv, NV_CIO_CRE_21, 0xfa); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_EXTRA, state->extra); + nvWriteCurVGA(pNv, NV_CIO_CRE_EBR_INDEX, state->extra); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_REPAINT0, state->repaint0); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_REPAINT1, state->repaint1); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_LSR, state->screen); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_PIXEL, state->pixel); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_HEB, state->horiz); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FIFO1, state->fifo); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FIFO0, state->arbitration0); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FIFO_LWM, state->arbitration1); + nvWriteCurVGA(pNv, NV_CIO_CRE_RPC0_INDEX, state->repaint0); + nvWriteCurVGA(pNv, NV_CIO_CRE_RPC1_INDEX, state->repaint1); + nvWriteCurVGA(pNv, NV_CIO_CRE_LSR_INDEX, state->screen); + nvWriteCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX, state->pixel); + nvWriteCurVGA(pNv, NV_CIO_CRE_HEB__INDEX, state->horiz); + nvWriteCurVGA(pNv, NV_CIO_CRE_ENH_INDEX, state->fifo); + nvWriteCurVGA(pNv, NV_CIO_CRE_FF_INDEX, state->arbitration0); + nvWriteCurVGA(pNv, NV_CIO_CRE_FFLWM__INDEX, state->arbitration1); if(pNv->Architecture >= NV_ARCH_30) { - nvWriteCurVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30, state->arbitration1 >> 8); + nvWriteCurVGA(pNv, NV_CIO_CRE_47, state->arbitration1 >> 8); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_CURCTL0, state->cursor0); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_CURCTL1, state->cursor1); + nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR0_INDEX, state->cursor0); + nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR1_INDEX, state->cursor1); if(pNv->Architecture == NV_ARCH_40) { /* HW bug */ volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS); nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_CURCTL2, state->cursor2); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_INTERLACE, state->interlace); + nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR2_INDEX, state->cursor2); + nvWriteCurVGA(pNv, NV_CIO_CRE_ILACE__INDEX, state->interlace); if(!pNv->FlatPanel) { NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel); @@ -1050,21 +1050,21 @@ void NVUnloadStateExt RIVA_HW_STATE *state ) { - state->repaint0 = nvReadCurVGA(pNv, NV_VGA_CRTCX_REPAINT0); - state->repaint1 = nvReadCurVGA(pNv, NV_VGA_CRTCX_REPAINT1); - state->screen = nvReadCurVGA(pNv, NV_VGA_CRTCX_LSR); - state->pixel = nvReadCurVGA(pNv, NV_VGA_CRTCX_PIXEL); - state->horiz = nvReadCurVGA(pNv, NV_VGA_CRTCX_HEB); - state->fifo = nvReadCurVGA(pNv, NV_VGA_CRTCX_FIFO1); - state->arbitration0 = nvReadCurVGA(pNv, NV_VGA_CRTCX_FIFO0); - state->arbitration1 = nvReadCurVGA(pNv, NV_VGA_CRTCX_FIFO_LWM); + state->repaint0 = nvReadCurVGA(pNv, NV_CIO_CRE_RPC0_INDEX); + state->repaint1 = nvReadCurVGA(pNv, NV_CIO_CRE_RPC1_INDEX); + state->screen = nvReadCurVGA(pNv, NV_CIO_CRE_LSR_INDEX); + state->pixel = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX); + state->horiz = nvReadCurVGA(pNv, NV_CIO_CRE_HEB__INDEX); + state->fifo = nvReadCurVGA(pNv, NV_CIO_CRE_ENH_INDEX); + state->arbitration0 = nvReadCurVGA(pNv, NV_CIO_CRE_FF_INDEX); + state->arbitration1 = nvReadCurVGA(pNv, NV_CIO_CRE_FFLWM__INDEX); if(pNv->Architecture >= NV_ARCH_30) { - state->arbitration1 |= (nvReadCurVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30) & 1) << 8; + state->arbitration1 |= (nvReadCurVGA(pNv, NV_CIO_CRE_47) & 1) << 8; } - state->cursor0 = nvReadCurVGA(pNv, NV_VGA_CRTCX_CURCTL0); - state->cursor1 = nvReadCurVGA(pNv, NV_VGA_CRTCX_CURCTL1); - state->cursor2 = nvReadCurVGA(pNv, NV_VGA_CRTCX_CURCTL2); - state->interlace = nvReadCurVGA(pNv, NV_VGA_CRTCX_INTERLACE); + state->cursor0 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR0_INDEX); + state->cursor1 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR1_INDEX); + state->cursor2 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR2_INDEX); + state->interlace = nvReadCurVGA(pNv, NV_CIO_CRE_ILACE__INDEX); state->vpll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL); if(pNv->twoHeads) @@ -1081,9 +1081,9 @@ void NVUnloadStateExt if(pNv->twoHeads) { state->head = NVReadCRTC(pNv, 0, NV_CRTC_FSEL); state->head2 = NVReadCRTC(pNv, 1, NV_CRTC_FSEL); - state->crtcOwner = nvReadCurVGA(pNv, NV_VGA_CRTCX_OWNER); + state->crtcOwner = nvReadCurVGA(pNv, NV_CIO_CRE_44); } - state->extra = nvReadCurVGA(pNv, NV_VGA_CRTCX_EXTRA); + state->extra = nvReadCurVGA(pNv, NV_CIO_CRE_EBR_INDEX); state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG); @@ -1095,8 +1095,8 @@ void NVUnloadStateExt } if(pNv->FlatPanel) { - state->timingH = nvReadCurVGA(pNv, NV_VGA_CRTCX_FP_HTIMING); - state->timingV = nvReadCurVGA(pNv, NV_VGA_CRTCX_FP_VTIMING); + state->timingH = nvReadCurVGA(pNv, NV_CIO_CRE_53); + state->timingV = nvReadCurVGA(pNv, NV_CIO_CRE_54); } } diff --git a/src/nv_output.c b/src/nv_output.c index eadbe30..0c98c03 100644 --- a/src/nv_output.c +++ b/src/nv_output.c @@ -572,18 +572,18 @@ nv_output_prepare(xf86OutputPtr output) nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head); /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */ - if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) { + if (!(regp->CRTC[NV_CIO_CRE_LCD__INDEX] & 0x44)) { if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) { - regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30; - regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x30; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x3; if (nv_crtc->head == 0) - regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x8; else - regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x8; if (nv_encoder->dcb->location != LOC_ON_CHIP) - regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= (nv_encoder->dcb->or << 4) & 0x30; } else - regp->CRTC[NV_VGA_CRTCX_LCD] = 0; + regp->CRTC[NV_CIO_CRE_LCD__INDEX] = 0; } } @@ -750,12 +750,12 @@ tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86Crt if (mode == DPMSModeOn) { nv_crtc = to_nouveau_crtc(crtc); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, - pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]); + NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, + pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX]); } else for (i = 0; i <= pNv->twoHeads; i++) - NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD, - NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30)); + NVWriteVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX, + NVReadVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX) & ~((nv_encoder->dcb->or << 4) & 0x30)); } } diff --git a/src/nv_setup.c b/src/nv_setup.c index 1c3add9..661ca5d 100644 --- a/src/nv_setup.c +++ b/src/nv_setup.c @@ -472,7 +472,7 @@ NVCommonSetup(ScrnInfoPtr pScrn) pNv->Television = FALSE; if (pNv->twoHeads) { - pNv->vtOWNER = NVReadVgaCrtc(pNv, 0, NV_VGA_CRTCX_OWNER); + pNv->vtOWNER = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_44); if (pNv->NVArch == 0x11) { /* reading OWNER is broken on nv11 */ if (nvReadMC(pNv, NV_PBUS_DEBUG_1) & (1 << 28)) /* heads tied, restore both */ pNv->vtOWNER = 0x04; @@ -482,16 +482,16 @@ NVCommonSetup(ScrnInfoPtr pScrn) NVSetOwner(pNv, 1); NVLockVgaCrtc(pNv, 1, false); - slaved_on_B = NVReadVgaCrtc(pNv, 1, NV_VGA_CRTCX_PIXEL) & 0x80; + slaved_on_B = NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_PIXEL_INDEX) & 0x80; if (slaved_on_B) - tvB = !(NVReadVgaCrtc(pNv, 1, NV_VGA_CRTCX_LCD) & 0x01); + tvB = !(NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_LCD__INDEX) & 0x01); NVSetOwner(pNv, 0); NVLockVgaCrtc(pNv, 0, false); - slaved_on_A = NVReadVgaCrtc(pNv, 0, NV_VGA_CRTCX_PIXEL) & 0x80; + slaved_on_A = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_PIXEL_INDEX) & 0x80; if (slaved_on_A) - tvA = !(NVReadVgaCrtc(pNv, 0, NV_VGA_CRTCX_LCD) & 0x01); + tvA = !(NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_LCD__INDEX) & 0x01); if (slaved_on_A && !tvA) pNv->vtOWNER = 0x0; @@ -536,8 +536,8 @@ NVCommonSetup(ScrnInfoPtr pScrn) if((pNv->Chipset & 0x0fff) <= CHIPSET_NV04) FlatPanel = 0; } else { - if(nvReadCurVGA(pNv, NV_VGA_CRTCX_PIXEL) & 0x80) { - if(!(nvReadCurVGA(pNv, NV_VGA_CRTCX_LCD) & 0x01)) + if(nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80) { + if(!(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01)) Television = TRUE; FlatPanel = 1; } else { @@ -585,22 +585,22 @@ NVCommonSetup(ScrnInfoPtr pScrn) cr44 = pNv->vtOWNER; - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, 3); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, 3); NVSelectHeadRegisters(pScrn, 1); NVLockUnlock(pScrn, 0); - slaved_on_B = nvReadCurVGA(pNv, NV_VGA_CRTCX_PIXEL) & 0x80; + slaved_on_B = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80; if(slaved_on_B) { - tvB = !(nvReadCurVGA(pNv, NV_VGA_CRTCX_LCD) & 0x01); + tvB = !(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01); } - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, 0); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, 0); NVSelectHeadRegisters(pScrn, 0); NVLockUnlock(pScrn, 0); - slaved_on_A = nvReadCurVGA(pNv, NV_VGA_CRTCX_PIXEL) & 0x80; + slaved_on_A = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX) & 0x80; if(slaved_on_A) { - tvA = !(nvReadCurVGA(pNv, NV_VGA_CRTCX_LCD) & 0x01); + tvA = !(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01); } oldhead = NVReadCRTC(pNv, 0, NV_CRTC_FSEL); @@ -719,7 +719,7 @@ NVCommonSetup(ScrnInfoPtr pScrn) NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, oldhead); - nvWriteCurVGA(pNv, NV_VGA_CRTCX_OWNER, cr44); + nvWriteCurVGA(pNv, NV_CIO_CRE_44, cr44); NVSelectHeadRegisters(pScrn, pNv->crtc_active[1]); } diff --git a/src/nvreg.h b/src/nvreg.h index f1c90c6..bcc64b6 100644 --- a/src/nvreg.h +++ b/src/nvreg.h @@ -98,69 +98,6 @@ #define CRTC_INDEX_COLOR 0x3d4 #define CRTC_DATA_COLOR 0x3d5 -/* Nvidia CRTC indexed registers */ -/* VGA standard registers: - from Haiku */ -#define NV_VGA_CRTCX_HTOTAL 0x00 -#define NV_VGA_CRTCX_HDISPE 0x01 -#define NV_VGA_CRTCX_HBLANKS 0x02 -#define NV_VGA_CRTCX_HBLANKE 0x03 -#define NV_VGA_CRTCX_HSYNCS 0x04 -#define NV_VGA_CRTCX_HSYNCE 0x05 -#define NV_VGA_CRTCX_VTOTAL 0x06 -#define NV_VGA_CRTCX_OVERFLOW 0x07 -#define NV_VGA_CRTCX_PRROWSCN 0x08 -#define NV_VGA_CRTCX_MAXSCLIN 0x09 -#define NV_VGA_CRTCX_VGACURSTART 0x0a -#define NV_VGA_CRTCX_VGACUREND 0x0b -#define NV_VGA_CRTCX_FBSTADDH 0x0c -#define NV_VGA_CRTCX_FBSTADDL 0x0d -#define NV_VGA_CRTCX_VSYNCS 0x10 -#define NV_VGA_CRTCX_VSYNCE 0x11 -#define NV_VGA_CRTCX_VDISPE 0x12 -#define NV_VGA_CRTCX_PITCHL 0x13 -#define NV_VGA_CRTCX_UNDERLINE 0x14 -#define NV_VGA_CRTCX_VBLANKS 0x15 -#define NV_VGA_CRTCX_VBLANKE 0x16 -#define NV_VGA_CRTCX_MODECTL 0x17 -#define NV_VGA_CRTCX_LINECOMP 0x18 -/* Extended VGA CRTC registers */ -#define NV_VGA_CRTCX_REPAINT0 0x19 -#define NV_VGA_CRTCX_REPAINT1 0x1a -#define NV_VGA_CRTCX_FIFO0 0x1b -#define NV_VGA_CRTCX_FIFO1 0x1c -#define NV_VGA_CRTCX_LOCK 0x1f -#define NV_VGA_CRTCX_FIFO_LWM 0x20 -#define NV_VGA_CRTCX_BUFFER 0x21 -#define NV_VGA_CRTCX_LSR 0x25 -#define NV_VGA_CRTCX_26 0x26 -#define NV_VGA_CRTCX_REVISION 0x27 -#define NV_VGA_CRTCX_PIXEL 0x28 -#define NV_VGA_CRTCX_HEB 0x2d -#define NV_VGA_CRTCX_2E 0x2e -#define NV_VGA_CRTCX_CURCTL2 0x2f -#define NV_VGA_CRTCX_CURCTL0 0x30 -#define NV_VGA_CRTCX_CURCTL1 0x31 -#define NV_VGA_CRTCX_LCD 0x33 -#define NV_VGA_CRTCX_INTERLACE 0x39 -#define NV_VGA_CRTCX_3B 0x3b -#define NV_VGA_CRTCX_SCRATCH4 0x3c -#define NV_VGA_CRTCX_EXTRA 0x41 -#define NV_VGA_CRTCX_OWNER 0x44 -#define NV_VGA_CRTCX_45 0x45 -#define NV_VGA_CRTCX_SWAPPING 0x46 -#define NV_VGA_CRTCX_FIFO_LWM_NV30 0x47 -#define NV_VGA_CRTCX_4B 0x4b -#define NV_VGA_CRTCX_FP_HTIMING 0x53 -#define NV_VGA_CRTCX_FP_VTIMING 0x54 -#define NV_VGA_CRTCX_52 0x52 -#define NV_VGA_CRTCX_55 0x55 -#define NV_VGA_CRTCX_56 0x56 -#define NV_VGA_CRTCX_57 0x57 -#define NV_VGA_CRTCX_58 0x58 -#define NV_VGA_CRTCX_59 0x59 -#define NV_VGA_CRTCX_85 0x85 -#define NV_VGA_CRTCX_86 0x86 - #define NV_PMC_BOOT_0 0x00000000 #define NV_PMC_ENABLE 0x00000200 @@ -225,6 +162,67 @@ # define NV_CRTC_FSEL_TVOUT2 (2<<8) # define NV_CRTC_FSEL_OVERLAY (1<<12) +#define NV_PRMCIO_CRX__COLOR 0x006013d4 +#define NV_PRMCIO_CR__COLOR 0x006013d5 + /* Standard VGA CRTC registers */ + #define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */ + #define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */ + #define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */ + #define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */ + #define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */ + #define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */ + #define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */ + #define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */ + #define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */ + #define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */ + #define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */ + #define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */ + #define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */ + #define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */ + #define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */ + #define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */ + #define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */ + #define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */ + #define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */ + #define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */ + #define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */ + #define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */ + #define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */ + /* Extended VGA CRTC registers */ + #define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */ + #define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */ + #define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */ + #define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */ + #define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */ + #define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */ + #define NV_CIO_CRE_21 0x21 /* referred to by some .scp as `shadow lock' */ + #define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */ + #define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index? */ + #define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */ + #define NV_CIO_CRE_PIXEL_INDEX 0x28 + #define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */ + #define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */ + #define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */ + #define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */ + #define NV_CIO_CRE_LCD__INDEX 0x33 + #define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */ + #define NV_CIO_CRE_SCRATCH3__INDEX 0x3b + #define NV_CIO_CRE_SCRATCH4__INDEX 0x3c + #define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */ + #define NV_CIO_CRE_44 0x44 /* head control */ + #define NV_CIO_CRE_CSB 0x45 + #define NV_CIO_CRE_RCR 0x46 + #define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */ + #define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */ + #define NV_CIO_CRE_52 0x52 + #define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */ + #define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */ + #define NV_CIO_CRE_57 0x57 /* index reg for cr58 */ + #define NV_CIO_CRE_58 0x58 /* data reg for cr57 */ + #define NV_CIO_CRE_59 0x59 + #define NV_CIO_CRE_85 0x85 + #define NV_CIO_CRE_86 0x86 + #define NV_RAMDAC_CURSOR_POS 0x00680300 #define NV_RAMDAC_CURSOR_CTRL 0x00680320 #define NV_RAMDAC_CURSOR_DATA_LO 0x00680324 -- 2.32.0.93.g670b81a890