From 7240f861a98c5f8d9779a4f3a743b748af775337 Mon Sep 17 00:00:00 2001 From: Stephane Marchesin Date: Sun, 3 Feb 2008 05:15:41 +0100 Subject: [PATCH] Understood and fixed some NV30 FP_CONTROL bits. --- src/nouveau_class.h | 14 +++++++++++--- src/nv30_shaders.c | 13 +++++-------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/nouveau_class.h b/src/nouveau_class.h index 438bec7..990ac1f 100644 --- a/src/nouveau_class.h +++ b/src/nouveau_class.h @@ -15,10 +15,10 @@ Stephane Marchesin, Serge Martin, Sylvain Munaut, + Simon Raffeiner, Ben Skeggs, Erik Waling, koala_br, - sturmflut. All Rights Reserved. @@ -4025,6 +4025,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV34TCL_FOG_EQUATION_LINEAR 0x000008d4 #define NV34TCL_FOG_EQUATION_QUADRATIC 0x000008d8 #define NV34TCL_FP_ACTIVE_PROGRAM 0x000008e4 +#define NV34TCL_FP_ACTIVE_PROGRAM_DMA0 (1 << 0) +#define NV34TCL_FP_ACTIVE_PROGRAM_DMA1 (1 << 1) +#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_SHIFT 2 +#define NV34TCL_FP_ACTIVE_PROGRAM_OFFSET_MASK 0xfffffffc #define NV34TCL_RC_COLOR0 0x000008ec #define NV34TCL_RC_COLOR0_B_SHIFT 0 #define NV34TCL_RC_COLOR0_B_MASK 0x000000ff @@ -4179,8 +4183,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV34TCL_FRONT_MATERIAL_SHININESS(x) (0x00001400+((x)*4)) #define NV34TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006 #define NV34TCL_FP_REG_CONTROL 0x00001450 -#define NV34TCL_FP_REG_CONTROL_USED_REGS_SHIFT 16 -#define NV34TCL_FP_REG_CONTROL_USED_REGS_MASK 0xffff0000 +#define NV34TCL_FP_REG_CONTROL_UNK1_SHIFT 16 +#define NV34TCL_FP_REG_CONTROL_UNK1_MASK 0xffff0000 +#define NV34TCL_FP_REG_CONTROL_UNK0_SHIFT 0 +#define NV34TCL_FP_REG_CONTROL_UNK0_MASK 0x0000ffff #define NV34TCL_VP_CLIP_PLANES_ENABLE 0x00001478 #define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 (1 << 1) #define NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 (1 << 5) @@ -4485,6 +4491,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV34TCL_VERTEX_ATTR_4F_W__SIZE 0x00000010 #define NV34TCL_FP_CONTROL 0x00001d60 #define NV34TCL_FP_CONTROL_USES_KIL (1 << 7) +#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_SHIFT 0 +#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_MASK 0x0000000f #define NV34TCL_MULTISAMPLE_CONTROL 0x00001d7c #define NV34TCL_CLEAR_DEPTH_VALUE 0x00001d8c #define NV34TCL_CLEAR_COLOR_VALUE 0x00001d90 diff --git a/src/nv30_shaders.c b/src/nv30_shaders.c index 88533bf..29323a1 100644 --- a/src/nv30_shaders.c +++ b/src/nv30_shaders.c @@ -44,18 +44,15 @@ NV30_LoadFragProg(ScrnInfoPtr pScrn, nv_shader_t *shader) BEGIN_RING(Nv3D, NV34TCL_FP_ACTIVE_PROGRAM, 1); OUT_RELOC (fp_mem, shader->hw_id, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, - 1 /*NV30TCL_FP_ADDRESS_DMA0*/, 2 /*NV30TCL_FP_ADDRESS_DMA1*/); + NV34TCL_FP_ACTIVE_PROGRAM_DMA0, NV34TCL_FP_ACTIVE_PROGRAM_DMA1); - BEGIN_RING(Nv3D, 0x1d60, 1); - OUT_RING (0); /* USES_KIL (1<<7) == 0 */ BEGIN_RING(Nv3D, 0x1450, 1); - OUT_RING (shader->card_priv.NV30FP.num_regs << 16| 4); - BEGIN_RING(Nv3D, 0x1d7c, 1); + OUT_RING ((1 << 16)| 4); + BEGIN_RING(Nv3D, NV34TCL_MULTISAMPLE_CONTROL, 1); OUT_RING (0xffff0000); - - /* FIXME this needs to be understood and handled properly */ + BEGIN_RING(Nv3D,NV34TCL_FP_CONTROL,1); - OUT_RING (0x1); + OUT_RING ((shader->card_priv.NV30FP.num_regs-1)/2); } -- 2.32.0.93.g670b81a890