From a1b7f8d9b20bff59956ea1dc2130e5590a60aa4c Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Wed, 15 Oct 2008 00:12:11 +0100 Subject: [PATCH] Rename relevant functions, sizes and offsets to PRM.IO from P.IO, in keeping with the nvidia scheme --- src/nv_bios.c | 12 ++++++------ src/nv_crtc.c | 8 ++++---- src/nv_hw.c | 46 +++++++++++++++++++++++----------------------- src/nv_proto.h | 4 ++-- src/nv_setup.c | 12 ++++++------ src/nvreg.h | 22 +++++++++++----------- 6 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/nv_bios.c b/src/nv_bios.c index 246d7c3..d8ea70f 100644 --- a/src/nv_bios.c +++ b/src/nv_bios.c @@ -281,8 +281,8 @@ static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg) static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port) { /* if adding more ports here, the read/write functions below will need - * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used - * for the port in question + * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is + * used for the port in question */ if (port == CRTC_INDEX_COLOR) return true; @@ -298,8 +298,8 @@ static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port) static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port) { /* if adding more ports here, the read/write functions below will need - * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used - * for the port in question + * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is + * used for the port in question */ if (port == VGA_ENABLE) return true; @@ -417,7 +417,7 @@ static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port) if (!nv_valid_port(pScrn, port)) return 0; - data = NVReadPVIO(pNv, crtchead, port); + data = NVReadPRMVIO(pNv, crtchead, port); BIOSLOG(pScrn, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", port, crtchead, data); @@ -438,7 +438,7 @@ static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data) if (pNv->VBIOS.execute) { still_alive(); - NVWritePVIO(pNv, crtchead, port, data); + NVWritePRMVIO(pNv, crtchead, port, data); } } diff --git a/src/nv_crtc.c b/src/nv_crtc.c index 3b5c088..831b54f 100644 --- a/src/nv_crtc.c +++ b/src/nv_crtc.c @@ -1340,7 +1340,7 @@ static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state) int i; NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head]; - NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg); + NVWritePRMVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg); for (i = 0; i < 5; i++) NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]); @@ -1464,7 +1464,7 @@ static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state) int i; NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head]; - regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R); + regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R); for (i = 0; i < 25; i++) regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i); @@ -1684,7 +1684,7 @@ static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state) { struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc); NVPtr pNv = NVPTR(crtc->scrn); - uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET; + uint32_t mmiobase = nv_crtc->head ? NV_PRMDIO1_OFFSET : NV_PRMDIO0_OFFSET; int i; VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff); @@ -1701,7 +1701,7 @@ static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state) { struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc); NVPtr pNv = NVPTR(crtc->scrn); - uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET; + uint32_t mmiobase = nv_crtc->head ? NV_PRMDIO1_OFFSET : NV_PRMDIO0_OFFSET; int i; VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff); diff --git a/src/nv_hw.c b/src/nv_hw.c index 21733c5..3f0f8a4 100644 --- a/src/nv_hw.c +++ b/src/nv_hw.c @@ -98,7 +98,7 @@ void nv_write_tmds(NVPtr pNv, int or, int dl, uint8_t address, uint8_t data) void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; DDXMMIOH("NVWriteVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, value); NV_WR08(pNv->REGS, CRTC_INDEX_COLOR + mmiobase, index); @@ -107,7 +107,7 @@ void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value) uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; NV_WR08(pNv->REGS, CRTC_INDEX_COLOR + mmiobase, index); DDXMMIOH("NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, CRTC_DATA_COLOR + mmiobase)); @@ -140,53 +140,53 @@ uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index) return NVReadVgaCrtc(pNv, head, NV_CIO_CRE_58); } -uint8_t NVReadPVIO(NVPtr pNv, int head, uint16_t port) +uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint16_t port) { /* Only NV4x have two pvio ranges */ - uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PVIO1_OFFSET : NV_PVIO0_OFFSET; + uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PRMVIO1_OFFSET : NV_PRMVIO0_OFFSET; - DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", head, port + mmiobase, NV_RD08(pNv->REGS, port + mmiobase)); + DDXMMIOH("NVReadPRMVIO: head %d reg %08x val %02x\n", head, port + mmiobase, NV_RD08(pNv->REGS, port + mmiobase)); return NV_RD08(pNv->REGS, port + mmiobase); } -void NVWritePVIO(NVPtr pNv, int head, uint16_t port, uint8_t value) +void NVWritePRMVIO(NVPtr pNv, int head, uint16_t port, uint8_t value) { /* Only NV4x have two pvio ranges */ - uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PVIO1_OFFSET : NV_PVIO0_OFFSET; + uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PRMVIO1_OFFSET : NV_PRMVIO0_OFFSET; - DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", head, port + mmiobase, value); + DDXMMIOH("NVWritePRMVIO: head %d reg %08x val %02x\n", head, port + mmiobase, value); NV_WR08(pNv->REGS, port + mmiobase, value); } void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value) { - NVWritePVIO(pNv, head, VGA_SEQ_INDEX, index); - NVWritePVIO(pNv, head, VGA_SEQ_DATA, value); + NVWritePRMVIO(pNv, head, VGA_SEQ_INDEX, index); + NVWritePRMVIO(pNv, head, VGA_SEQ_DATA, value); } uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index) { - NVWritePVIO(pNv, head, VGA_SEQ_INDEX, index); - return NVReadPVIO(pNv, head, VGA_SEQ_DATA); + NVWritePRMVIO(pNv, head, VGA_SEQ_INDEX, index); + return NVReadPRMVIO(pNv, head, VGA_SEQ_DATA); } void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value) { - NVWritePVIO(pNv, head, VGA_GRAPH_INDEX, index); - NVWritePVIO(pNv, head, VGA_GRAPH_DATA, value); + NVWritePRMVIO(pNv, head, VGA_GRAPH_INDEX, index); + NVWritePRMVIO(pNv, head, VGA_GRAPH_DATA, value); } uint8_t NVReadVgaGr(NVPtr pNv, int head, uint8_t index) { - NVWritePVIO(pNv, head, VGA_GRAPH_INDEX, index); - return NVReadPVIO(pNv, head, VGA_GRAPH_DATA); + NVWritePRMVIO(pNv, head, VGA_GRAPH_INDEX, index); + return NVReadPRMVIO(pNv, head, VGA_GRAPH_DATA); } #define CRTC_IN_STAT_1 0x3da void NVSetEnablePalette(NVPtr pNv, int head, bool enable) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; VGA_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase); VGA_WR08(pNv->REGS, VGA_ATTR_INDEX + mmiobase, enable ? 0 : 0x20); @@ -194,7 +194,7 @@ void NVSetEnablePalette(NVPtr pNv, int head, bool enable) static bool NVGetEnablePalette(NVPtr pNv, int head) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; VGA_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase); return !(VGA_RD08(pNv->REGS, VGA_ATTR_INDEX + mmiobase) & 0x20); @@ -202,7 +202,7 @@ static bool NVGetEnablePalette(NVPtr pNv, int head) void NVWriteVgaAttr(NVPtr pNv, int head, uint8_t index, uint8_t value) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; if (NVGetEnablePalette(pNv, head)) index &= ~0x20; @@ -217,7 +217,7 @@ void NVWriteVgaAttr(NVPtr pNv, int head, uint8_t index, uint8_t value) uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index) { - uint32_t mmiobase = head ? NV_PCIO1_OFFSET : NV_PCIO0_OFFSET; + uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET; if (NVGetEnablePalette(pNv, head)) index &= ~0x20; @@ -1157,14 +1157,14 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save) NVBlankScreen(pNv, 0, true); /* save control regs */ - misc = NVReadPVIO(pNv, 0, VGA_MISC_OUT_R); + misc = NVReadPRMVIO(pNv, 0, VGA_MISC_OUT_R); seq2 = NVReadVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE); seq4 = NVReadVgaSeq(pNv, 0, VGA_SEQ_MEMORY_MODE); gr4 = NVReadVgaGr(pNv, 0, VGA_GFX_PLANE_READ); gr5 = NVReadVgaGr(pNv, 0, VGA_GFX_MODE); gr6 = NVReadVgaGr(pNv, 0, VGA_GFX_MISC); - NVWritePVIO(pNv, 0, VGA_MISC_OUT_W, 0x67); + NVWritePRMVIO(pNv, 0, VGA_MISC_OUT_W, 0x67); NVWriteVgaSeq(pNv, 0, VGA_SEQ_MEMORY_MODE, 0x6); NVWriteVgaGr(pNv, 0, VGA_GFX_MODE, 0x0); NVWriteVgaGr(pNv, 0, VGA_GFX_MISC, 0x5); @@ -1206,7 +1206,7 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save) MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[3][i]); /* restore control regs */ - NVWritePVIO(pNv, 0, VGA_MISC_OUT_W, misc); + NVWritePRMVIO(pNv, 0, VGA_MISC_OUT_W, misc); NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, gr4); NVWriteVgaGr(pNv, 0, VGA_GFX_MODE, gr5); NVWriteVgaGr(pNv, 0, VGA_GFX_MISC, gr6); diff --git a/src/nv_proto.h b/src/nv_proto.h index 5c389dd..0085f51 100644 --- a/src/nv_proto.h +++ b/src/nv_proto.h @@ -99,8 +99,8 @@ void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value); uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index); void NVWriteVgaCrtc5758(NVPtr pNv, int head, uint8_t index, uint8_t value); uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index); -uint8_t NVReadPVIO(NVPtr pNv, int head, uint16_t port); -void NVWritePVIO(NVPtr pNv, int head, uint16_t port, uint8_t value); +uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint16_t port); +void NVWritePRMVIO(NVPtr pNv, int head, uint16_t port, uint8_t value); void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value); uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index); void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value); diff --git a/src/nv_setup.c b/src/nv_setup.c index 661ca5d..70930bf 100644 --- a/src/nv_setup.c +++ b/src/nv_setup.c @@ -372,12 +372,12 @@ NVCommonSetup(ScrnInfoPtr pScrn) pNv->PGRAPH = pNv->REGS + (NV_PGRAPH_OFFSET/4); /* 8 bit registers */ - pNv->PCIO0 = (uint8_t *)pNv->REGS + NV_PCIO0_OFFSET; - pNv->PDIO0 = (uint8_t *)pNv->REGS + NV_PDIO0_OFFSET; - pNv->PVIO0 = (uint8_t *)pNv->REGS + NV_PVIO0_OFFSET; - pNv->PCIO1 = pNv->PCIO0 + NV_PCIO_SIZE; - pNv->PDIO1 = pNv->PDIO0 + NV_PDIO_SIZE; - pNv->PVIO1 = pNv->PVIO0 + NV_PVIO_SIZE; + pNv->PCIO0 = (uint8_t *)pNv->REGS + NV_PRMCIO0_OFFSET; + pNv->PDIO0 = (uint8_t *)pNv->REGS + NV_PRMDIO0_OFFSET; + pNv->PVIO0 = (uint8_t *)pNv->REGS + NV_PRMVIO0_OFFSET; + pNv->PCIO1 = pNv->PCIO0 + NV_PRMCIO_SIZE; + pNv->PDIO1 = pNv->PDIO0 + NV_PRMDIO_SIZE; + pNv->PVIO1 = pNv->PVIO0 + NV_PRMVIO_SIZE; pNv->alphaCursor = (pNv->NVArch >= 0x11); diff --git a/src/nvreg.h b/src/nvreg.h index bcc64b6..43c6a1e 100644 --- a/src/nvreg.h +++ b/src/nvreg.h @@ -50,12 +50,12 @@ #define NV_PPM_OFFSET 0x0000A000 #define NV_PPM_SIZE 0x00001000 -#define NV_PVGA_OFFSET 0x000A0000 -#define NV_PVGA_SIZE 0x00020000 +#define NV_PRMVGA_OFFSET 0x000A0000 +#define NV_PRMVGA_SIZE 0x00020000 -#define NV_PVIO0_OFFSET 0x000C0000 -#define NV_PVIO_SIZE 0x00002000 -#define NV_PVIO1_OFFSET 0x000C2000 +#define NV_PRMVIO0_OFFSET 0x000C0000 +#define NV_PRMVIO_SIZE 0x00002000 +#define NV_PRMVIO1_OFFSET 0x000C2000 #define NV_PFB_OFFSET 0x00100000 #define NV_PFB_SIZE 0x00001000 @@ -75,9 +75,9 @@ #define NV_PCRTC0_OFFSET 0x00600000 #define NV_PCRTC0_SIZE 0x00002000 /* empirical */ -#define NV_PCIO0_OFFSET 0x00601000 -#define NV_PCIO_SIZE 0x00002000 -#define NV_PCIO1_OFFSET 0x00603000 +#define NV_PRMCIO0_OFFSET 0x00601000 +#define NV_PRMCIO_SIZE 0x00002000 +#define NV_PRMCIO1_OFFSET 0x00603000 #define NV50_DISPLAY_OFFSET 0x00610000 #define NV50_DISPLAY_SIZE 0x0000FFFF @@ -85,9 +85,9 @@ #define NV_PRAMDAC0_OFFSET 0x00680000 #define NV_PRAMDAC0_SIZE 0x00002000 -#define NV_PDIO0_OFFSET 0x00681000 -#define NV_PDIO_SIZE 0x00002000 -#define NV_PDIO1_OFFSET 0x00683000 +#define NV_PRMDIO0_OFFSET 0x00681000 +#define NV_PRMDIO_SIZE 0x00002000 +#define NV_PRMDIO1_OFFSET 0x00683000 #define NV_PRAMIN_OFFSET 0x00700000 #define NV_PRAMIN_SIZE 0x00100000 -- 2.32.0.93.g670b81a890