From a3a0710604017f3ceb9c552552d71c3f5dcfab0f Mon Sep 17 00:00:00 2001 From: Maarten Maathuis Date: Mon, 7 Apr 2008 19:09:35 +0200 Subject: [PATCH] NV50: Give a few registers an UNK label. --- src/nv50_crtc.c | 10 +++++----- src/nv50_display.c | 2 +- src/nv50reg.h | 20 ++++++++++++++++++-- src/nv_output.c | 8 ++++---- 4 files changed, 28 insertions(+), 12 deletions(-) diff --git a/src/nv50_crtc.c b/src/nv50_crtc.c index 6b4e378..9e813f2 100644 --- a/src/nv50_crtc.c +++ b/src/nv50_crtc.c @@ -218,7 +218,7 @@ nv50_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjuste NV50CrtcCommand(crtc, NV50_CRTC0_CLOCK, adjusted_mode->Clock | 0x800000); NV50CrtcCommand(crtc, NV50_CRTC0_INTERLACE, (adjusted_mode->Flags & V_INTERLACE) ? 2 : 0); NV50CrtcCommand(crtc, NV50_CRTC0_DISPLAY_START, 0); - NV50CrtcCommand(crtc, 0x82c, 0); + NV50CrtcCommand(crtc, NV50_CRTC0_UNK82C, 0); NV50CrtcCommand(crtc, NV50_CRTC0_DISPLAY_TOTAL, adjusted_mode->CrtcVTotal << 16 | adjusted_mode->CrtcHTotal); NV50CrtcCommand(crtc, NV50_CRTC0_SYNC_DURATION, (vsync_dur - 1) << 16 | (hsync_dur - 1)); NV50CrtcCommand(crtc, NV50_CRTC0_SYNC_START_TO_BLANK_END, (vsync_start_to_end - 1) << 16 | (hsync_start_to_end - 1)); @@ -274,11 +274,11 @@ NV50CrtcBlankScreen(xf86CrtcPtr crtc, Bool blank) } else { NV50CrtcCommand(crtc, NV50_CRTC0_FB_OFFSET, pNv->FB->offset >> 8); NV50CrtcCommand(crtc, 0x864, 0); - NVWrite(pNv, 0x00610380, 0); + NVWrite(pNv, NV50_DISPLAY_UNK_380, 0); /* RAM is clamped to 256 MiB. */ - NVWrite(pNv, NV50_CRTC0_RAM_AMOUNT, pNv->RamAmountKBytes * 1024 - 1); - NVWrite(pNv, 0x00610388, 0x150000); - NVWrite(pNv, 0x0061038C, 0); + NVWrite(pNv, NV50_DISPLAY_RAM_AMOUNT, pNv->RamAmountKBytes * 1024 - 1); + NVWrite(pNv, NV50_DISPLAY_UNK_388, 0x150000); + NVWrite(pNv, NV50_DISPLAY_UNK_38C, 0); if (nv_crtc->head == 1) NV50CrtcCommand(crtc, NV50_CRTC0_CURSOR_OFFSET, pNv->Cursor2->offset >> 8); else diff --git a/src/nv50_display.c b/src/nv50_display.c index 66cb6e6..4066ba8 100644 --- a/src/nv50_display.c +++ b/src/nv50_display.c @@ -94,7 +94,7 @@ NV50DispInit(ScrnInfoPtr pScrn) NV50DisplayCommand(pScrn, NV50_CRTC0_BLANK_CTRL, NV50_CRTC0_BLANK_CTRL_BLANK); NV50DisplayCommand(pScrn, 0x800, 0); NV50DisplayCommand(pScrn, NV50_CRTC0_DISPLAY_START, 0); - NV50DisplayCommand(pScrn, 0x82c, 0); + NV50DisplayCommand(pScrn, NV50_CRTC0_UNK82C, 0); return TRUE; } diff --git a/src/nv50reg.h b/src/nv50reg.h index 81a45fa..cd228a7 100644 --- a/src/nv50reg.h +++ b/src/nv50reg.h @@ -93,9 +93,11 @@ #define NV50_DISPLAY_CTRL_STATE_PENDING (1 << 31) #define NV50_DISPLAY_CTRL_VAL 0x00610304 +#define NV50_DISPLAY_UNK_380 0x00610380 /* Clamped to 256 MiB */ -#define NV50_CRTC0_RAM_AMOUNT 0x00610384 -#define NV50_CRTC1_RAM_AMOUNT 0x00610784 +#define NV50_DISPLAY_RAM_AMOUNT 0x00610384 +#define NV50_DISPLAY_UNK_388 0x00610388 +#define NV50_DISPLAY_UNK_38C 0x0061038C /* The registers in this range are normally accessed through display commands, with an offset of 0x540 for crtc1. */ /* They also seem duplicated into the next register as well. */ @@ -181,6 +183,12 @@ /* I don't know what bit27 does, it doesn't seem extremely important. */ #define NV50_SOR0_CLK_CTRL2 0x0061C008 #define NV50_SOR_CLK_CTRL2_CONNECTED (3 << 9) +/* Seems to be a default state, nothing that can RE'd in great detail. */ +#define NV50_SOR0_UNK00C 0x0061C00C +#define NV50_SOR0_UNK010 0x0061C010 +#define NV50_SOR0_UNK014 0x0061C014 +#define NV50_SOR0_UNK018 0x0061C018 + #define NV50_SOR0_DPMS_STATE 0x0061C030 #define NV50_SOR_DPMS_STATE_SOR_ACTIVE (3 << 16) /* this does not show if DAC is active */ #define NV50_SOR_DPMS_STATE_SOR_DPMS_OFF (8 << 16) /* as in blanked */ @@ -188,6 +196,12 @@ #define NV50_SOR1_DPMS_CTRL 0x0061C804 #define NV50_SOR1_CLK_CTRL2 0x0061C808 +/* Seems to be a default state, nothing that can RE'd in any great detail. */ +#define NV50_SOR1_UNK00C 0x0061C80C +#define NV50_SOR1_UNK010 0x0061C810 +#define NV50_SOR1_UNK014 0x0061C814 +#define NV50_SOR1_UNK018 0x0061C818 + #define NV50_SOR1_DPMS_STATE 0x0061C830 #define NV50_CRTC0_CURSOR_POS 0x00647084 @@ -231,6 +245,8 @@ #define NV50_CRTC0_MODE_UNK1 0x820 #define NV50_CRTC0_MODE_UNK2 0x824 +#define NV50_CRTC0_UNK82C 0x82C + /* You can't have a palette in 8 bit mode (=OFF) */ #define NV50_CRTC0_CLUT_MODE 0x840 #define NV50_CRTC0_CLUT_MODE_BLANK 0x00000000 diff --git a/src/nv_output.c b/src/nv_output.c index 70cf236..158326a 100644 --- a/src/nv_output.c +++ b/src/nv_output.c @@ -968,10 +968,10 @@ static void nv_add_output(ScrnInfoPtr pScrn, int dcb_entry, const xf86OutputFunc if (pNv->Architecture == NV_ARCH_50) { if (nv_output->type == OUTPUT_TMDS) { - NVWrite(pNv, 0x0061c00c + NV50OrOffset(output) * 0x800, 0x03010700); - NVWrite(pNv, 0x0061c010 + NV50OrOffset(output) * 0x800, 0x0000152f); - NVWrite(pNv, 0x0061c014 + NV50OrOffset(output) * 0x800, 0x00000000); - NVWrite(pNv, 0x0061c018 + NV50OrOffset(output) * 0x800, 0x00245af8); + NVWrite(pNv, NV50_SOR0_UNK00C + NV50OrOffset(output) * 0x800, 0x03010700); + NVWrite(pNv, NV50_SOR0_UNK010 + NV50OrOffset(output) * 0x800, 0x0000152f); + NVWrite(pNv, NV50_SOR0_UNK014 + NV50OrOffset(output) * 0x800, 0x00000000); + NVWrite(pNv, NV50_SOR0_UNK018 + NV50OrOffset(output) * 0x800, 0x00245af8); } /* This needs to be handled in the same way as pre-NV5x on the long run. */ -- 2.32.0.93.g670b81a890