From afc6668d2b4a1971c211c421b6a415fe74dbd2ea Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Sat, 18 Oct 2008 02:23:18 +0100 Subject: [PATCH] cr26 is just another view of 0x3c0 remove superfluous crtc unlock too --- src/nv_crtc.c | 9 --------- src/nvreg.h | 2 +- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/nv_crtc.c b/src/nv_crtc.c index c7010d8..e0abf4a 100644 --- a/src/nv_crtc.c +++ b/src/nv_crtc.c @@ -656,10 +656,6 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode) regp->CRTC[NV_CIO_CRE_53] = 0; regp->CRTC[NV_CIO_CRE_54] = 0; - /* What is the purpose of this register? */ - /* 0x14 may be disabled? */ - regp->CRTC[NV_CIO_CR_ARX_INDEX] = 0x20; - /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ if (lvds_output) regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; @@ -1343,9 +1339,6 @@ static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state) for (i = 0; i < 5; i++) NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]); - /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_VRE_INDEX, regp->CRTC[NV_CIO_CR_VRE_INDEX] & ~0x80); - for (i = 0; i < 25; i++) NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]); @@ -1425,7 +1418,6 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) nv_fix_nv40_hw_cursor(pNv, nv_crtc->head); NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]); - NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX, regp->CRTC[NV_CIO_CR_ARX_INDEX]); NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]); NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]); if (pNv->Architecture >= NV_ARCH_10) { @@ -1524,7 +1516,6 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO); regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG); - regp->CRTC[NV_CIO_CR_ARX_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_ARX_INDEX); regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX); regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX); if (pNv->Architecture >= NV_ARCH_10) { diff --git a/src/nvreg.h b/src/nvreg.h index bbc0cc2..dda804a 100644 --- a/src/nvreg.h +++ b/src/nvreg.h @@ -236,7 +236,7 @@ #define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */ #define NV_CIO_CRE_21 0x21 /* referred to by some .scp as `shadow lock' */ #define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */ - #define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index? */ + #define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */ #define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */ #define NV_CIO_CRE_PIXEL_INDEX 0x28 #define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */ -- 2.32.0.93.g670b81a890