git.oblomov.eu Git - clinfo/blob - src/ext.h

   1 /* Include OpenCL header, and define OpenCL extensions, since what is and is not
   2  * available in the official headers is very system-dependent */
   3
   4 #ifndef EXT_H
   5 #define EXT_H
   6
   7 /* Khronos now provides unified headers for all OpenCL versions, and
   8  * it should be included after defining a target OpenCL version
   9  * (otherwise, the maximum version will simply be used, but a message
  10  * will be printed).
  11  *
  12  * TODO: until 3.0 gets finalized, we only target 2.2 because the 3.0
  13  * defines etc are still changing, so users may have an older version
  14  * of the 3.0 headers lying around, which may prevent clinfo from being
  15  * compilable.
  16  */
  17 #define CL_TARGET_OPENCL_VERSION 220
  18
  19 /* We will use the deprecated clGetExtensionFunctionAddress,
  20  * so let the headers know that we don't care about it being deprecated.
  21  * The standard CL_USE_DEPRECATED_OPENCL_1_1_APIS define apparently
  22  * doesn't work for macOS, so we'll just tell the compiler to not
  23  * warn about deprecated functions.
  24  * A more correct solution would be to suppress the warning only around the
  25  * clGetExtensionFunctionAddress call, but honestly I just cleaned up that
  26  * piece of code. And I'm actually wondering if it even makes sense to
  27  * build that part of the code on macOS: does anybody actually use
  28  * ocl-icd as OpenCL dispatcher on macOS?
  29  */
  30
  31 #ifdef __APPLE__
  32 #pragma GCC diagnostic ignored "-Wdeprecated-declarations"
  33 #include <OpenCL/opencl.h>
  34 #else
  35 #define CL_USE_DEPRECATED_OPENCL_1_1_APIS
  36 #include <CL/cl.h>
  37 #endif
  38
  39 /* Very old headers will be missing these defines */
  40 #ifndef CL_VERSION_1_1
  41 #define CL_DEVICE_PREFERRED_VECTOR_WIDTH_HALF           0x1034
  42 #define CL_DEVICE_HOST_UNIFIED_MEMORY                   0x1035
  43 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_CHAR              0x1036
  44 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_SHORT             0x1037
  45 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_INT               0x1038
  46 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_LONG              0x1039
  47 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_FLOAT             0x103A
  48 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE            0x103B
  49 #define CL_DEVICE_NATIVE_VECTOR_WIDTH_HALF              0x103C
  50 #define CL_DEVICE_OPENCL_C_VERSION                      0x103D
  51
  52 #define CL_FP_SOFT_FLOAT                                (1 << 6)
  53
  54 #define CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE    0x11B3
  55 #endif
  56
  57 #ifndef CL_VERSION_1_2
  58 #define CL_DEVICE_TYPE_CUSTOM                           (1 << 4)
  59
  60 #define CL_DEVICE_LINKER_AVAILABLE                      0x103E
  61 #define CL_DEVICE_BUILT_IN_KERNELS                      0x103F
  62 #define CL_DEVICE_IMAGE_MAX_BUFFER_SIZE                 0x1040
  63 #define CL_DEVICE_IMAGE_MAX_ARRAY_SIZE                  0x1041
  64 #define CL_DEVICE_PARTITION_MAX_SUB_DEVICES             0x1043
  65 #define CL_DEVICE_PARTITION_PROPERTIES                  0x1044
  66 #define CL_DEVICE_PARTITION_AFFINITY_DOMAIN             0x1045
  67 #define CL_DEVICE_PARTITION_TYPE                        0x1046
  68 #define CL_DEVICE_PREFERRED_INTEROP_USER_SYNC           0x1048
  69 #define CL_DEVICE_PRINTF_BUFFER_SIZE                    0x1049
  70 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT                 0x104A
  71 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT          0x104B
  72
  73 #define CL_FP_CORRECTLY_ROUNDED_DIVIDE_SQRT             (1 << 7)
  74
  75 /* cl_device_partition_property */
  76 #define CL_DEVICE_PARTITION_EQUALLY                     0x1086
  77 #define CL_DEVICE_PARTITION_BY_COUNTS                   0x1087
  78 #define CL_DEVICE_PARTITION_BY_COUNTS_LIST_END          0x0
  79 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN          0x1088
  80
  81 /* cl_device_affinity_domain */
  82 #define CL_DEVICE_AFFINITY_DOMAIN_NUMA                  (1 << 0)
  83 #define CL_DEVICE_AFFINITY_DOMAIN_L4_CACHE              (1 << 1)
  84 #define CL_DEVICE_AFFINITY_DOMAIN_L3_CACHE              (1 << 2)
  85 #define CL_DEVICE_AFFINITY_DOMAIN_L2_CACHE              (1 << 3)
  86 #define CL_DEVICE_AFFINITY_DOMAIN_L1_CACHE              (1 << 4)
  87 #define CL_DEVICE_AFFINITY_DOMAIN_NEXT_PARTITIONABLE    (1 << 5)
  88
  89 #endif
  90
  91 /* These two defines were introduced in the 1.2 headers
  92  * on 2012-11-30, so earlier versions don't have them
  93  * (e.g. Debian wheezy)
  94  */
  95
  96 #ifndef CL_DEVICE_IMAGE_PITCH_ALIGNMENT
  97 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT                 0x104A
  98 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT          0x104B
  99 #endif
 100
 101 /* 2.0 headers are not very common for the time being, so
 102  * let's copy the defines for the new CL_DEVICE_* properties
 103  * here.
 104  */
 105 #ifndef CL_VERSION_2_0
 106 #define CL_DEVICE_MAX_READ_WRITE_IMAGE_ARGS             0x104C
 107 #define CL_DEVICE_MAX_GLOBAL_VARIABLE_SIZE              0x104D
 108 #define CL_DEVICE_QUEUE_ON_HOST_PROPERTIES              0x102A
 109 #define CL_DEVICE_QUEUE_ON_DEVICE_PROPERTIES            0x104E
 110 #define CL_DEVICE_QUEUE_ON_DEVICE_PREFERRED_SIZE        0x104F
 111 #define CL_DEVICE_QUEUE_ON_DEVICE_MAX_SIZE              0x1050
 112 #define CL_DEVICE_MAX_ON_DEVICE_QUEUES                  0x1051
 113 #define CL_DEVICE_MAX_ON_DEVICE_EVENTS                  0x1052
 114 #define CL_DEVICE_SVM_CAPABILITIES                      0x1053
 115 #define CL_DEVICE_GLOBAL_VARIABLE_PREFERRED_TOTAL_SIZE  0x1054
 116 #define CL_DEVICE_MAX_PIPE_ARGS                         0x1055
 117 #define CL_DEVICE_PIPE_MAX_ACTIVE_RESERVATIONS          0x1056
 118 #define CL_DEVICE_PIPE_MAX_PACKET_SIZE                  0x1057
 119 #define CL_DEVICE_PREFERRED_PLATFORM_ATOMIC_ALIGNMENT   0x1058
 120 #define CL_DEVICE_PREFERRED_GLOBAL_ATOMIC_ALIGNMENT     0x1059
 121 #define CL_DEVICE_PREFERRED_LOCAL_ATOMIC_ALIGNMENT      0x105A
 122
 123 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER           (1 << 0)
 124 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER             (1 << 1)
 125 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM             (1 << 2)
 126 #define CL_DEVICE_SVM_ATOMICS                       (1 << 3)
 127
 128 typedef cl_bitfield         cl_device_svm_capabilities;
 129 #endif
 130
 131 #ifndef CL_VERSION_2_1
 132 #define CL_PLATFORM_HOST_TIMER_RESOLUTION               0x0905
 133 #define CL_DEVICE_IL_VERSION                            0x105B
 134 #define CL_DEVICE_MAX_NUM_SUB_GROUPS                    0x105C
 135 #define CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS 0x105D
 136 #endif
 137
 138 #ifndef CL_VERSION_3_0
 139 #define CL_PLATFORM_NUMERIC_VERSION                     0x0906
 140 #define CL_PLATFORM_EXTENSIONS_WITH_VERSION             0x0907
 141 #define CL_DEVICE_NUMERIC_VERSION                       0x105E
 142 #define CL_DEVICE_EXTENSIONS_WITH_VERSION               0x1060
 143 #define CL_DEVICE_ILS_WITH_VERSION                      0x1061
 144 #define CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION         0x1062
 145 #define CL_DEVICE_ATOMIC_MEMORY_CAPABILITIES            0x1063
 146 #define CL_DEVICE_ATOMIC_FENCE_CAPABILITIES             0x1064
 147 #define CL_DEVICE_NON_UNIFORM_WORK_GROUP_SUPPORT        0x1065
 148 #define CL_DEVICE_OPENCL_C_ALL_VERSIONS                 0x1066
 149 #define CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_MULTIPLE    0x1067
 150 #define CL_DEVICE_WORK_GROUP_COLLECTIVE_FUNCTIONS_SUPPORT 0x1068
 151 #define CL_DEVICE_GENERIC_ADDRESS_SPACE_SUPPORT         0x1069
 152 #define CL_DEVICE_OPENCL_C_FEATURES                     0x106F
 153 #define CL_DEVICE_DEVICE_ENQUEUE_CAPABILITIES           0x1070
 154 #define CL_DEVICE_PIPE_SUPPORT                          0x1071
 155 #define CL_DEVICE_LATEST_CONFORMANCE_VERSION_PASSED     0x1072
 156
 157
 158 typedef cl_bitfield     cl_device_atomic_capabilities;
 159 typedef cl_bitfield     cl_device_device_enqueue_capabilities;
 160 typedef cl_uint         cl_version;
 161
 162 #define CL_NAME_VERSION_MAX_NAME_SIZE 64
 163
 164 typedef struct _cl_name_version {
 165     cl_version              version;
 166     char                    name[CL_NAME_VERSION_MAX_NAME_SIZE];
 167 } cl_name_version;
 168
 169 /* cl_device_atomic_capabilities */
 170 #define CL_DEVICE_ATOMIC_ORDER_RELAXED          (1 << 0)
 171 #define CL_DEVICE_ATOMIC_ORDER_ACQ_REL          (1 << 1)
 172 #define CL_DEVICE_ATOMIC_ORDER_SEQ_CST          (1 << 2)
 173 #define CL_DEVICE_ATOMIC_SCOPE_WORK_ITEM        (1 << 3)
 174 #define CL_DEVICE_ATOMIC_SCOPE_WORK_GROUP       (1 << 4)
 175 #define CL_DEVICE_ATOMIC_SCOPE_DEVICE           (1 << 5)
 176 #define CL_DEVICE_ATOMIC_SCOPE_ALL_DEVICES      (1 << 6)
 177
 178 /* cl_device_device_enqueue_capabilities */
 179 #define CL_DEVICE_QUEUE_SUPPORTED               (1 << 0)
 180 #define CL_DEVICE_QUEUE_REPLACEABLE_DEFAULT     (1 << 1)
 181
 182 #endif
 183
 184 /*
 185  * Extensions
 186  */
 187
 188 /* cl_khr_extended_versioning */
 189 // the _KHR fields are the same as the unsuffixed from OpenCL 3
 190 #define CL_PLATFORM_NUMERIC_VERSION_KHR                 CL_PLATFORM_NUMERIC_VERSION
 191 #define CL_PLATFORM_EXTENSIONS_WITH_VERSION_KHR         CL_PLATFORM_EXTENSIONS_WITH_VERSION
 192 #define CL_DEVICE_NUMERIC_VERSION_KHR                   CL_DEVICE_NUMERIC_VERSION
 193 #define CL_DEVICE_OPENCL_C_NUMERIC_VERSION_KHR          0x105F
 194 #define CL_DEVICE_EXTENSIONS_WITH_VERSION_KHR           CL_DEVICE_EXTENSIONS_WITH_VERSION
 195 #define CL_DEVICE_ILS_WITH_VERSION_KHR                  CL_DEVICE_ILS_WITH_VERSION
 196 #define CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION_KHR     CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION
 197
 198 /* cl_khr_image2d_from_buffer */
 199 // the _KHR fields are the same as the unsuffixed from OpenCL 2
 200 #define CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR             CL_DEVICE_IMAGE_PITCH_ALIGNMENT
 201 #define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR      CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT
 202
 203
 204 /* cl_khr_icd */
 205 #define CL_PLATFORM_ICD_SUFFIX_KHR                      0x0920
 206 #define CL_PLATFORM_NOT_FOUND_KHR                       -1001
 207
 208 /* cl_amd_object_metadata */
 209 #define CL_PLATFORM_MAX_KEYS_AMD                        0x403C
 210
 211 /* cl_khr_device_uuid extension */
 212
 213 #define CL_UUID_SIZE_KHR 16
 214 #define CL_LUID_SIZE_KHR 8
 215
 216 #define CL_DEVICE_UUID_KHR          0x106A
 217 #define CL_DRIVER_UUID_KHR          0x106B
 218 #define CL_DEVICE_LUID_VALID_KHR    0x106C
 219 #define CL_DEVICE_LUID_KHR          0x106D
 220 #define CL_DEVICE_NODE_MASK_KHR     0x106E
 221
 222 /* cl_khr_fp64 */
 223 #define CL_DEVICE_DOUBLE_FP_CONFIG                      0x1032
 224
 225 /* cl_khr_fp16 */
 226 #define CL_DEVICE_HALF_FP_CONFIG                        0x1033
 227
 228 /* cl_khr_il_program */
 229 #define CL_DEVICE_IL_VERSION_KHR                        0x105B
 230
 231 /* cl_khr_command_buffer */
 232 #define CL_DEVICE_COMMAND_BUFFER_CAPABILITIES_KHR       0x12A9
 233 #define CL_DEVICE_COMMAND_BUFFER_REQUIRED_QUEUE_PROPERTIES_KHR  0x12AA
 234 typedef cl_bitfield         cl_device_command_buffer_capabilities_khr;
 235
 236 /* cl_khr_command_buffer_mutable_dispatch */
 237 #define CL_DEVICE_MUTABLE_DISPATCH_CAPABILITIES_KHR     0x12B0
 238 typedef cl_bitfield         cl_mutable_dispatch_fields_khr;
 239
 240 /* cl_khr_terminate_context */
 241 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR_1x           0x200F
 242 #define CL_DEVICE_TERMINATE_CAPABILITY_KHR              0x2031
 243
 244 /* TODO: I cannot find official definitions for these,
 245  * so I'm currently extrapolating them from the specification
 246  */
 247 typedef cl_bitfield cl_device_terminate_capability_khr;
 248 #define CL_DEVICE_TERMINATE_CAPABILITY_CONTEXT_KHR      (1<<0)
 249
 250 /* cl_khr_subgroup_named_barrier */
 251 #define CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR           0x2035
 252
 253 /* cl_khr_semaphore */
 254 #define CL_PLATFORM_SEMAPHORE_TYPES_KHR                 0x2036
 255 #define CL_DEVICE_SEMAPHORE_TYPES_KHR                   0x204C
 256 typedef cl_uint cl_semaphore_type_khr;
 257
 258 /* cl_khr_external_semaphore */
 259 #define CL_PLATFORM_SEMAPHORE_IMPORT_HANDLE_TYPES_KHR   0x2037
 260 #define CL_PLATFORM_SEMAPHORE_EXPORT_HANDLE_TYPES_KHR   0x2038
 261 #define CL_DEVICE_SEMAPHORE_IMPORT_HANDLE_TYPES_KHR     0x204D
 262 #define CL_DEVICE_SEMAPHORE_EXPORT_HANDLE_TYPES_KHR     0x204E
 263 typedef cl_uint cl_external_semaphore_handle_type_khr;
 264
 265 /* cl_khr_external_memory */
 266 #define CL_PLATFORM_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR     0x2044
 267 #define CL_DEVICE_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR       0x204F
 268 typedef cl_uint cl_external_memory_handle_type_khr;
 269
 270
 271 /* cl_khr_pci_bus_info */
 272 typedef struct _cl_device_pci_bus_info_khr {
 273         cl_uint pci_domain;
 274         cl_uint pci_bus;
 275         cl_uint pci_device;
 276         cl_uint pci_function;
 277 } cl_device_pci_bus_info_khr;
 278
 279 #define CL_DEVICE_PCI_BUS_INFO_KHR                      0x410F
 280
 281 /* cl_nv_device_attribute_query */
 282 #define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV           0x4000
 283 #define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV           0x4001
 284 #define CL_DEVICE_REGISTERS_PER_BLOCK_NV                0x4002
 285 #define CL_DEVICE_WARP_SIZE_NV                          0x4003
 286 #define CL_DEVICE_GPU_OVERLAP_NV                        0x4004
 287 #define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV                0x4005
 288 #define CL_DEVICE_INTEGRATED_MEMORY_NV                  0x4006
 289 #define CL_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT_NV       0x4007
 290 #define CL_DEVICE_PCI_BUS_ID_NV                         0x4008
 291 #define CL_DEVICE_PCI_SLOT_ID_NV                        0x4009
 292 #define CL_DEVICE_PCI_DOMAIN_ID_NV                      0x400A
 293
 294 /* cl_ext_atomic_counters_{32,64} */
 295 #define CL_DEVICE_MAX_ATOMIC_COUNTERS_EXT               0x4032
 296
 297 /* cl_amd_device_attribute_query */
 298 #define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD            0x4036
 299 #define CL_DEVICE_TOPOLOGY_AMD                          0x4037
 300 #define CL_DEVICE_BOARD_NAME_AMD                        0x4038
 301 #define CL_DEVICE_GLOBAL_FREE_MEMORY_AMD                0x4039
 302 #define CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD             0x4040
 303 #define CL_DEVICE_SIMD_WIDTH_AMD                        0x4041
 304 #define CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD            0x4042
 305 #define CL_DEVICE_WAVEFRONT_WIDTH_AMD                   0x4043
 306 #define CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD               0x4044
 307 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD          0x4045
 308 #define CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD     0x4046
 309 #define CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD   0x4047
 310 #define CL_DEVICE_LOCAL_MEM_BANKS_AMD                   0x4048
 311 #define CL_DEVICE_THREAD_TRACE_SUPPORTED_AMD            0x4049
 312 #define CL_DEVICE_GFXIP_MAJOR_AMD                       0x404A
 313 #define CL_DEVICE_GFXIP_MINOR_AMD                       0x404B
 314 #define CL_DEVICE_AVAILABLE_ASYNC_QUEUES_AMD            0x404C
 315 /* These two are undocumented */
 316 #define CL_DEVICE_MAX_REAL_TIME_COMPUTE_QUEUES_AMD      0x404D
 317 #define CL_DEVICE_MAX_REAL_TIME_COMPUTE_UNITS_AMD       0x404E
 318 /* These were added in v4 of the extension, but have values lower than
 319  * than the older ones, and spanning around the cl_ext_atomic_counters_*
 320  * define
 321  */
 322 #define CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_AMD         0x4030
 323 #define CL_DEVICE_MAX_WORK_GROUP_SIZE_AMD               0x4031
 324 #define CL_DEVICE_PREFERRED_CONSTANT_BUFFER_SIZE_AMD    0x4033
 325 #define CL_DEVICE_PCIE_ID_AMD                           0x4034
 326
 327 #ifndef CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD
 328 #define CL_DEVICE_TOPOLOGY_TYPE_PCIE_AMD                1
 329
 330 typedef union
 331 {
 332         struct { cl_uint type; cl_uint data[5]; } raw;
 333         struct { cl_uint type; cl_char unused[17]; cl_char bus; cl_char device; cl_char function; } pcie;
 334 } cl_device_topology_amd;
 335 #endif
 336
 337 /* cl_amd_offline_devices */
 338 #define CL_CONTEXT_OFFLINE_DEVICES_AMD                  0x403F
 339
 340 /* cl_amd_copy_buffer_p2p */
 341 #define CL_DEVICE_NUM_P2P_DEVICES_AMD                   0x4088
 342 #define CL_DEVICE_P2P_DEVICES_AMD                       0x4089
 343
 344 /* cl_ext_cxx_for_opencl */
 345 #define CL_DEVICE_CXX_FOR_OPENCL_NUMERIC_VERSION_EXT    0x4230
 346
 347 /* cl_ext_device_fission */
 348 #define cl_ext_device_fission                           1
 349
 350 typedef cl_ulong  cl_device_partition_property_ext;
 351
 352 #define CL_DEVICE_PARTITION_EQUALLY_EXT                 0x4050
 353 #define CL_DEVICE_PARTITION_BY_COUNTS_EXT               0x4051
 354 #define CL_DEVICE_PARTITION_BY_NAMES_EXT                0x4052
 355 #define CL_DEVICE_PARTITION_BY_NAMES_INTEL              0x4052 /* cl_intel_device_partition_by_names */
 356 #define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT      0x4053
 357
 358 #define CL_DEVICE_PARENT_DEVICE_EXT                     0x4054
 359 #define CL_DEVICE_PARTITION_TYPES_EXT                   0x4055
 360 #define CL_DEVICE_AFFINITY_DOMAINS_EXT                  0x4056
 361 #define CL_DEVICE_REFERENCE_COUNT_EXT                   0x4057
 362 #define CL_DEVICE_PARTITION_STYLE_EXT                   0x4058
 363
 364 #define CL_AFFINITY_DOMAIN_L1_CACHE_EXT                 0x1
 365 #define CL_AFFINITY_DOMAIN_L2_CACHE_EXT                 0x2
 366 #define CL_AFFINITY_DOMAIN_L3_CACHE_EXT                 0x3
 367 #define CL_AFFINITY_DOMAIN_L4_CACHE_EXT                 0x4
 368 #define CL_AFFINITY_DOMAIN_NUMA_EXT                     0x10
 369 #define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT         0x100
 370
 371 /* cl_intel_advanced_motion_estimation */
 372 #define CL_DEVICE_ME_VERSION_INTEL                      0x407E
 373
 374 /* cl_intel_device_side_avc_motion_estimation */
 375 #define CL_DEVICE_AVC_ME_VERSION_INTEL                          0x410B
 376 #define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL     0x410C
 377 #define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL              0x410D
 378
 379 /* cl_intel_planar_yuv */
 380 #define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL            0x417E
 381 #define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL           0x417F
 382
 383 /* cl_intel_unified_shared_memory */
 384 #define CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL                   0x4190
 385 #define CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL                 0x4191
 386 #define CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL   0x4192
 387 #define CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL    0x4193
 388 #define CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL          0x4194
 389
 390 /* cl_qcom_ext_host_ptr */
 391 #define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM         0x40A0
 392 #define CL_DEVICE_PAGE_SIZE_QCOM                        0x40A1
 393
 394 /* cl_arm_shared_virtual_memory */
 395 #define CL_DEVICE_SVM_CAPABILITIES_ARM                  0x40B6
 396 #define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER_ARM           CL_DEVICE_SVM_COARSE_GRAIN_BUFFER
 397 #define CL_DEVICE_SVM_FINE_GRAIN_BUFFER_ARM             CL_DEVICE_SVM_FINE_GRAIN_BUFFER
 398 #define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM_ARM             CL_DEVICE_SVM_FINE_GRAIN_SYSTEM
 399 #define CL_DEVICE_SVM_ATOMICS_ARM                       CL_DEVICE_SVM_ATOMICS
 400
 401 /* cl_arm_core_id */
 402 #define CL_DEVICE_COMPUTE_UNITS_BITFIELD_ARM            0x40BF
 403
 404 /* cl_arm_controlled_kernel_termination */
 405 #define CL_DEVICE_CONTROLLED_TERMINATION_CAPABILITIES_ARM       0x41EE
 406
 407 typedef cl_bitfield cl_device_controlled_termination_capabilities_arm;
 408 #define CL_DEVICE_CONTROLLED_TERMINATION_SUCCESS_ARM    (1 << 0)
 409 #define CL_DEVICE_CONTROLLED_TERMINATION_FAILURE_ARM    (1 << 1)
 410 #define CL_DEVICE_CONTROLLED_TERMINATION_QUERY_ARM      (1 << 2)
 411
 412 /* cl_khr_spir */
 413 #define CL_DEVICE_SPIR_VERSIONS                         0x40E0
 414
 415 /* cl_altera_device_temperature */
 416 #define CL_DEVICE_CORE_TEMPERATURE_ALTERA               0x40F3
 417
 418 /* cl_intel_simultaneous_sharing */
 419 #define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL           0x4104
 420 #define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL       0x4105
 421
 422 /* cl_intel_required_subgroup_size */
 423 #define CL_DEVICE_SUB_GROUP_SIZES_INTEL                 0x4108
 424
 425 /* cl_intel_command_queue_families */
 426 #define CL_DEVICE_QUEUE_FAMILY_PROPERTIES_INTEL         0x418B
 427
 428 typedef cl_bitfield         cl_command_queue_capabilities_intel;
 429
 430 #define CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL                 64
 431 typedef struct _cl_queue_family_properties_intel {
 432     cl_command_queue_properties properties;
 433     cl_command_queue_capabilities_intel capabilities;
 434     cl_uint count;
 435     char name[CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL];
 436 } cl_queue_family_properties_intel;
 437
 438 /* cl_arm_job_slot_selection */
 439 #define CL_DEVICE_JOB_SLOTS_ARM                         0x41E0
 440
 441 /* cl_arm_scheduling_controls */
 442
 443 typedef cl_bitfield cl_device_scheduling_controls_capabilities_arm;
 444
 445 #define CL_DEVICE_SCHEDULING_CONTROLS_CAPABILITIES_ARM  0x41E4
 446
 447 #define CL_DEVICE_SCHEDULING_KERNEL_BATCHING_ARM                (1 << 0)
 448 #define CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_ARM           (1 << 1)
 449 #define CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_MODIFIER_ARM  (1 << 2)
 450 #define CL_DEVICE_SCHEDULING_DEFERRED_FLUSH_ARM                 (1 << 3)
 451 #define CL_DEVICE_SCHEDULING_REGISTER_ALLOCATION_ARM            (1 << 4)
 452 #define CL_DEVICE_SCHEDULING_WARP_THROTTLING_ARM                (1 << 5)
 453 #define CL_DEVICE_SCHEDULING_COMPUTE_UNIT_BATCH_QUEUE_SIZE_ARM  (1 << 6)
 454
 455 #define CL_DEVICE_MAX_WARP_COUNT_ARM                    0x41EA
 456 #define CL_DEVICE_SUPPORTED_REGISTER_ALLOCATIONS_ARM    0x41EB
 457
 458 /* cl_intel_device_attribute_query */
 459
 460 typedef cl_bitfield cl_device_feature_capabilities_intel;
 461
 462 #define CL_DEVICE_FEATURE_FLAG_DP4A_INTEL       (1 << 0)
 463 #define CL_DEVICE_FEATURE_FLAG_DPAS_INTEL       (1 << 1)
 464
 465 #define CL_DEVICE_IP_VERSION_INTEL                      0x4250
 466 #define CL_DEVICE_ID_INTEL                              0x4251
 467 #define CL_DEVICE_NUM_SLICES_INTEL                      0x4252
 468 #define CL_DEVICE_NUM_SUB_SLICES_PER_SLICE_INTEL        0x4253
 469 #define CL_DEVICE_NUM_EUS_PER_SUB_SLICE_INTEL           0x4254
 470 #define CL_DEVICE_NUM_THREADS_PER_EU_INTEL              0x4255
 471 #define CL_DEVICE_FEATURE_CAPABILITIES_INTEL            0x4256
 472
 473 /* clGeICDLoaderInfoOCLICD */
 474 typedef enum {
 475         CL_ICDL_OCL_VERSION=1,
 476         CL_ICDL_VERSION=2,
 477         CL_ICDL_NAME=3,
 478         CL_ICDL_VENDOR=4,
 479 } cl_icdl_info;
 480
 481 #endif