2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> More errata workarounds for PCI-X.
33 * --> Complete a full errata audit for all chipsets to identify others.
35 * --> Develop a low-power-consumption strategy, and implement it.
37 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
39 * --> [Experiment, Marvell value added] Is it possible to use target
40 * mode to cross-connect two Linux boxes with Marvell cards? If so,
41 * creating LibATA target mode support would be very interesting.
43 * Target mode, for those without docs, is the ability to directly
44 * connect two SATA ports.
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/blkdev.h>
52 #include <linux/delay.h>
53 #include <linux/interrupt.h>
54 #include <linux/dmapool.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/device.h>
57 #include <linux/platform_device.h>
58 #include <linux/ata_platform.h>
59 #include <linux/mbus.h>
60 #include <linux/bitops.h>
61 #include <scsi/scsi_host.h>
62 #include <scsi/scsi_cmnd.h>
63 #include <scsi/scsi_device.h>
64 #include <linux/libata.h>
66 #define DRV_NAME "sata_mv"
67 #define DRV_VERSION "1.27"
75 module_param(msi, int, S_IRUGO);
76 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
79 static int irq_coalescing_io_count;
80 module_param(irq_coalescing_io_count, int, S_IRUGO);
81 MODULE_PARM_DESC(irq_coalescing_io_count,
82 "IRQ coalescing I/O count threshold (0..255)");
84 static int irq_coalescing_usecs;
85 module_param(irq_coalescing_usecs, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_usecs,
87 "IRQ coalescing time threshold in usecs");
90 /* BAR's are enumerated in terms of pci_resource_start() terms */
91 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
92 MV_IO_BAR = 2, /* offset 0x18: IO space */
93 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
95 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
96 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
98 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
99 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
100 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
101 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
106 * Per-chip ("all ports") interrupt coalescing feature.
107 * This is only for GEN_II / GEN_IIE hardware.
109 * Coalescing defers the interrupt until either the IO_THRESHOLD
110 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
112 MV_COAL_REG_BASE = 0x18000,
113 MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
114 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
116 MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
117 MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
120 * Registers for the (unused here) transaction coalescing feature:
122 MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
123 MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
125 MV_SATAHC0_REG_BASE = 0x20000,
126 MV_FLASH_CTL_OFS = 0x1046c,
127 MV_GPIO_PORT_CTL_OFS = 0x104f0,
128 MV_RESET_CFG_OFS = 0x180d8,
130 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
131 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
132 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
133 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
136 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
138 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
139 * CRPB needs alignment on a 256B boundary. Size == 256B
140 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
142 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
143 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
145 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
147 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
148 MV_PORT_HC_SHIFT = 2,
149 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
150 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
151 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
154 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
156 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
157 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
159 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
161 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
162 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
164 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
166 CRQB_FLAG_READ = (1 << 0),
168 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
169 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
170 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
171 CRQB_CMD_ADDR_SHIFT = 8,
172 CRQB_CMD_CS = (0x2 << 11),
173 CRQB_CMD_LAST = (1 << 15),
175 CRPB_FLAG_STATUS_SHIFT = 8,
176 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
177 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
179 EPRD_FLAG_END_OF_TBL = (1 << 31),
181 /* PCI interface registers */
183 PCI_COMMAND_OFS = 0xc00,
184 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
186 PCI_MAIN_CMD_STS_OFS = 0xd30,
187 STOP_PCI_MASTER = (1 << 2),
188 PCI_MASTER_EMPTY = (1 << 3),
189 GLOB_SFT_RST = (1 << 4),
191 MV_PCI_MODE_OFS = 0xd00,
192 MV_PCI_MODE_MASK = 0x30,
194 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
195 MV_PCI_DISC_TIMER = 0xd04,
196 MV_PCI_MSI_TRIGGER = 0xc38,
197 MV_PCI_SERR_MASK = 0xc28,
198 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
199 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
200 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
201 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
202 MV_PCI_ERR_COMMAND = 0x1d50,
204 PCI_IRQ_CAUSE_OFS = 0x1d58,
205 PCI_IRQ_MASK_OFS = 0x1d5c,
206 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
208 PCIE_IRQ_CAUSE_OFS = 0x1900,
209 PCIE_IRQ_MASK_OFS = 0x1910,
210 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
212 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
213 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
214 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
215 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
216 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
217 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
218 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
219 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
220 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
221 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
222 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
224 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
225 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
226 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
227 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
228 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
229 GPIO_INT = (1 << 22),
230 SELF_INT = (1 << 23),
231 TWSI_INT = (1 << 24),
232 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
233 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
234 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
236 /* SATAHC registers */
239 HC_IRQ_CAUSE_OFS = 0x14,
240 DMA_IRQ = (1 << 0), /* shift by port # */
241 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
242 DEV_IRQ = (1 << 8), /* shift by port # */
245 * Per-HC (Host-Controller) interrupt coalescing feature.
246 * This is present on all chip generations.
248 * Coalescing defers the interrupt until either the IO_THRESHOLD
249 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
251 HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
252 HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
254 SOC_LED_CTRL_OFS = 0x2c,
255 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
256 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
257 /* with dev activity LED */
259 /* Shadow block registers */
261 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
264 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
265 SATA_ACTIVE_OFS = 0x350,
266 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
267 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
270 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
274 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
275 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
276 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
277 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
280 SATA_IFCTL_OFS = 0x344,
281 SATA_TESTCTL_OFS = 0x348,
282 SATA_IFSTAT_OFS = 0x34c,
283 VENDOR_UNIQUE_FIS_OFS = 0x35c,
286 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
287 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
290 MV5_LTMODE_OFS = 0x30,
291 MV5_PHY_CTL_OFS = 0x0C,
292 SATA_INTERFACE_CFG_OFS = 0x050,
294 MV_M2_PREAMP_MASK = 0x7e0,
298 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
299 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
300 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
301 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
302 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
303 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
304 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
306 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
307 EDMA_ERR_IRQ_MASK_OFS = 0xc,
308 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
309 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
310 EDMA_ERR_DEV = (1 << 2), /* device error */
311 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
312 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
313 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
314 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
315 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
316 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
317 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
318 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
319 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
320 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
321 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
323 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
324 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
325 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
326 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
327 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
329 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
331 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
332 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
333 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
334 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
335 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
336 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
338 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
340 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
341 EDMA_ERR_OVERRUN_5 = (1 << 5),
342 EDMA_ERR_UNDERRUN_5 = (1 << 6),
344 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
345 EDMA_ERR_LNK_CTRL_RX_1 |
346 EDMA_ERR_LNK_CTRL_RX_3 |
347 EDMA_ERR_LNK_CTRL_TX,
349 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
359 EDMA_ERR_LNK_CTRL_RX_2 |
360 EDMA_ERR_LNK_DATA_RX |
361 EDMA_ERR_LNK_DATA_TX |
362 EDMA_ERR_TRANS_PROTO,
364 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
369 EDMA_ERR_UNDERRUN_5 |
370 EDMA_ERR_SELF_DIS_5 |
376 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
377 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
379 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
380 EDMA_REQ_Q_PTR_SHIFT = 5,
382 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
383 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
384 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
385 EDMA_RSP_Q_PTR_SHIFT = 3,
387 EDMA_CMD_OFS = 0x28, /* EDMA command register */
388 EDMA_EN = (1 << 0), /* enable EDMA */
389 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
390 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
392 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
393 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
394 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
396 EDMA_IORDY_TMOUT_OFS = 0x34,
397 EDMA_ARB_CFG_OFS = 0x38,
399 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
400 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
402 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
403 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
404 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
405 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
407 /* Host private flags (hp_flags) */
408 MV_HP_FLAG_MSI = (1 << 0),
409 MV_HP_ERRATA_50XXB0 = (1 << 1),
410 MV_HP_ERRATA_50XXB2 = (1 << 2),
411 MV_HP_ERRATA_60X1B2 = (1 << 3),
412 MV_HP_ERRATA_60X1C0 = (1 << 4),
413 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
414 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
415 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
416 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
417 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
418 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
419 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
421 /* Port private flags (pp_flags) */
422 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
423 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
424 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
425 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
426 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
429 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
430 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
431 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
432 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
433 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
435 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
436 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
439 /* DMA boundary 0xffff is required by the s/g splitting
440 * we need on /length/ in mv_fill-sg().
442 MV_DMA_BOUNDARY = 0xffffU,
444 /* mask of register bits containing lower 32 bits
445 * of EDMA request queue DMA address
447 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
449 /* ditto, for response queue */
450 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464 /* Command ReQuest Block: 32B */
480 /* Command ResPonse Block: 8B */
487 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
496 * We keep a local cache of a few frequently accessed port
497 * registers here, to avoid having to read them (very slow)
498 * when switching between EDMA and non-EDMA modes.
500 struct mv_cached_regs {
507 struct mv_port_priv {
508 struct mv_crqb *crqb;
510 struct mv_crpb *crpb;
512 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
513 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
515 unsigned int req_idx;
516 unsigned int resp_idx;
519 struct mv_cached_regs cached;
520 unsigned int delayed_eh_pmp_map;
523 struct mv_port_signal {
528 struct mv_host_priv {
531 struct mv_port_signal signal[8];
532 const struct mv_hw_ops *ops;
535 void __iomem *main_irq_cause_addr;
536 void __iomem *main_irq_mask_addr;
541 * These consistent DMA memory pools give us guaranteed
542 * alignment for hardware-accessed data structures,
543 * and less memory waste in accomplishing the alignment.
545 struct dma_pool *crqb_pool;
546 struct dma_pool *crpb_pool;
547 struct dma_pool *sg_tbl_pool;
551 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
553 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
554 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
556 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
558 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
559 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
562 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
563 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
564 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
565 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
566 static int mv_port_start(struct ata_port *ap);
567 static void mv_port_stop(struct ata_port *ap);
568 static int mv_qc_defer(struct ata_queued_cmd *qc);
569 static void mv_qc_prep(struct ata_queued_cmd *qc);
570 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
571 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
572 static int mv_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline);
574 static void mv_eh_freeze(struct ata_port *ap);
575 static void mv_eh_thaw(struct ata_port *ap);
576 static void mv6_dev_config(struct ata_device *dev);
578 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
580 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
581 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
583 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
585 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
586 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
588 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
590 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
591 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
593 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
595 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
596 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
598 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
600 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
601 void __iomem *mmio, unsigned int n_hc);
602 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
604 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
605 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
606 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port_no);
608 static int mv_stop_edma(struct ata_port *ap);
609 static int mv_stop_edma_engine(void __iomem *port_mmio);
610 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
612 static void mv_pmp_select(struct ata_port *ap, int pmp);
613 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
614 unsigned long deadline);
615 static int mv_softreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline);
617 static void mv_pmp_error_handler(struct ata_port *ap);
618 static void mv_process_crpb_entries(struct ata_port *ap,
619 struct mv_port_priv *pp);
621 static void mv_sff_irq_clear(struct ata_port *ap);
622 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
623 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
624 static void mv_bmdma_start(struct ata_queued_cmd *qc);
625 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
626 static u8 mv_bmdma_status(struct ata_port *ap);
627 static u8 mv_sff_check_status(struct ata_port *ap);
629 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
630 * because we have to allow room for worst case splitting of
631 * PRDs for 64K boundaries in mv_fill_sg().
633 static struct scsi_host_template mv5_sht = {
634 ATA_BASE_SHT(DRV_NAME),
635 .sg_tablesize = MV_MAX_SG_CT / 2,
636 .dma_boundary = MV_DMA_BOUNDARY,
639 static struct scsi_host_template mv6_sht = {
640 ATA_NCQ_SHT(DRV_NAME),
641 .can_queue = MV_MAX_Q_DEPTH - 1,
642 .sg_tablesize = MV_MAX_SG_CT / 2,
643 .dma_boundary = MV_DMA_BOUNDARY,
646 static struct ata_port_operations mv5_ops = {
647 .inherits = &ata_sff_port_ops,
649 .qc_defer = mv_qc_defer,
650 .qc_prep = mv_qc_prep,
651 .qc_issue = mv_qc_issue,
653 .freeze = mv_eh_freeze,
655 .hardreset = mv_hardreset,
656 .error_handler = ata_std_error_handler, /* avoid SFF EH */
657 .post_internal_cmd = ATA_OP_NULL,
659 .scr_read = mv5_scr_read,
660 .scr_write = mv5_scr_write,
662 .port_start = mv_port_start,
663 .port_stop = mv_port_stop,
666 static struct ata_port_operations mv6_ops = {
667 .inherits = &mv5_ops,
668 .dev_config = mv6_dev_config,
669 .scr_read = mv_scr_read,
670 .scr_write = mv_scr_write,
672 .pmp_hardreset = mv_pmp_hardreset,
673 .pmp_softreset = mv_softreset,
674 .softreset = mv_softreset,
675 .error_handler = mv_pmp_error_handler,
677 .sff_check_status = mv_sff_check_status,
678 .sff_irq_clear = mv_sff_irq_clear,
679 .check_atapi_dma = mv_check_atapi_dma,
680 .bmdma_setup = mv_bmdma_setup,
681 .bmdma_start = mv_bmdma_start,
682 .bmdma_stop = mv_bmdma_stop,
683 .bmdma_status = mv_bmdma_status,
686 static struct ata_port_operations mv_iie_ops = {
687 .inherits = &mv6_ops,
688 .dev_config = ATA_OP_NULL,
689 .qc_prep = mv_qc_prep_iie,
692 static const struct ata_port_info mv_port_info[] = {
694 .flags = MV_GEN_I_FLAGS,
695 .pio_mask = 0x1f, /* pio0-4 */
696 .udma_mask = ATA_UDMA6,
697 .port_ops = &mv5_ops,
700 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
701 .pio_mask = 0x1f, /* pio0-4 */
702 .udma_mask = ATA_UDMA6,
703 .port_ops = &mv5_ops,
706 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
707 .pio_mask = 0x1f, /* pio0-4 */
708 .udma_mask = ATA_UDMA6,
709 .port_ops = &mv5_ops,
712 .flags = MV_GEN_II_FLAGS,
713 .pio_mask = 0x1f, /* pio0-4 */
714 .udma_mask = ATA_UDMA6,
715 .port_ops = &mv6_ops,
718 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
719 .pio_mask = 0x1f, /* pio0-4 */
720 .udma_mask = ATA_UDMA6,
721 .port_ops = &mv6_ops,
724 .flags = MV_GEN_IIE_FLAGS,
725 .pio_mask = 0x1f, /* pio0-4 */
726 .udma_mask = ATA_UDMA6,
727 .port_ops = &mv_iie_ops,
730 .flags = MV_GEN_IIE_FLAGS,
731 .pio_mask = 0x1f, /* pio0-4 */
732 .udma_mask = ATA_UDMA6,
733 .port_ops = &mv_iie_ops,
736 .flags = MV_GEN_IIE_FLAGS,
737 .pio_mask = 0x1f, /* pio0-4 */
738 .udma_mask = ATA_UDMA6,
739 .port_ops = &mv_iie_ops,
743 static const struct pci_device_id mv_pci_tbl[] = {
744 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
745 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
746 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
747 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
748 /* RocketRAID 1720/174x have different identifiers */
749 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
750 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
751 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
753 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
754 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
755 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
756 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
757 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
759 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
762 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
764 /* Marvell 7042 support */
765 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
767 /* Highpoint RocketRAID PCIe series */
768 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
769 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
771 { } /* terminate list */
774 static const struct mv_hw_ops mv5xxx_ops = {
775 .phy_errata = mv5_phy_errata,
776 .enable_leds = mv5_enable_leds,
777 .read_preamp = mv5_read_preamp,
778 .reset_hc = mv5_reset_hc,
779 .reset_flash = mv5_reset_flash,
780 .reset_bus = mv5_reset_bus,
783 static const struct mv_hw_ops mv6xxx_ops = {
784 .phy_errata = mv6_phy_errata,
785 .enable_leds = mv6_enable_leds,
786 .read_preamp = mv6_read_preamp,
787 .reset_hc = mv6_reset_hc,
788 .reset_flash = mv6_reset_flash,
789 .reset_bus = mv_reset_pci_bus,
792 static const struct mv_hw_ops mv_soc_ops = {
793 .phy_errata = mv6_phy_errata,
794 .enable_leds = mv_soc_enable_leds,
795 .read_preamp = mv_soc_read_preamp,
796 .reset_hc = mv_soc_reset_hc,
797 .reset_flash = mv_soc_reset_flash,
798 .reset_bus = mv_soc_reset_bus,
805 static inline void writelfl(unsigned long data, void __iomem *addr)
808 (void) readl(addr); /* flush to avoid PCI posted write */
811 static inline unsigned int mv_hc_from_port(unsigned int port)
813 return port >> MV_PORT_HC_SHIFT;
816 static inline unsigned int mv_hardport_from_port(unsigned int port)
818 return port & MV_PORT_MASK;
822 * Consolidate some rather tricky bit shift calculations.
823 * This is hot-path stuff, so not a function.
824 * Simple code, with two return values, so macro rather than inline.
826 * port is the sole input, in range 0..7.
827 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
828 * hardport is the other output, in range 0..3.
830 * Note that port and hardport may be the same variable in some cases.
832 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
834 shift = mv_hc_from_port(port) * HC_SHIFT; \
835 hardport = mv_hardport_from_port(port); \
836 shift += hardport * 2; \
839 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
841 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
844 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
847 return mv_hc_base(base, mv_hc_from_port(port));
850 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
852 return mv_hc_base_from_port(base, port) +
853 MV_SATAHC_ARBTR_REG_SZ +
854 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
857 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
859 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
860 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
862 return hc_mmio + ofs;
865 static inline void __iomem *mv_host_base(struct ata_host *host)
867 struct mv_host_priv *hpriv = host->private_data;
871 static inline void __iomem *mv_ap_base(struct ata_port *ap)
873 return mv_port_base(mv_host_base(ap->host), ap->port_no);
876 static inline int mv_get_hc_count(unsigned long port_flags)
878 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
882 * mv_save_cached_regs - (re-)initialize cached port registers
883 * @ap: the port whose registers we are caching
885 * Initialize the local cache of port registers,
886 * so that reading them over and over again can
887 * be avoided on the hotter paths of this driver.
888 * This saves a few microseconds each time we switch
889 * to/from EDMA mode to perform (eg.) a drive cache flush.
891 static void mv_save_cached_regs(struct ata_port *ap)
893 void __iomem *port_mmio = mv_ap_base(ap);
894 struct mv_port_priv *pp = ap->private_data;
896 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
897 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
898 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
899 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
903 * mv_write_cached_reg - write to a cached port register
904 * @addr: hardware address of the register
905 * @old: pointer to cached value of the register
906 * @new: new value for the register
908 * Write a new value to a cached register,
909 * but only if the value is different from before.
911 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
919 static void mv_set_edma_ptrs(void __iomem *port_mmio,
920 struct mv_host_priv *hpriv,
921 struct mv_port_priv *pp)
926 * initialize request queue
928 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
929 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
931 WARN_ON(pp->crqb_dma & 0x3ff);
932 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
933 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
934 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
935 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
938 * initialize response queue
940 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
941 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
943 WARN_ON(pp->crpb_dma & 0xff);
944 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
945 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
946 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
947 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
950 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
953 * When writing to the main_irq_mask in hardware,
954 * we must ensure exclusivity between the interrupt coalescing bits
955 * and the corresponding individual port DONE_IRQ bits.
957 * Note that this register is really an "IRQ enable" register,
958 * not an "IRQ mask" register as Marvell's naming might suggest.
960 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
961 mask &= ~DONE_IRQ_0_3;
962 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
963 mask &= ~DONE_IRQ_4_7;
964 writelfl(mask, hpriv->main_irq_mask_addr);
967 static void mv_set_main_irq_mask(struct ata_host *host,
968 u32 disable_bits, u32 enable_bits)
970 struct mv_host_priv *hpriv = host->private_data;
971 u32 old_mask, new_mask;
973 old_mask = hpriv->main_irq_mask;
974 new_mask = (old_mask & ~disable_bits) | enable_bits;
975 if (new_mask != old_mask) {
976 hpriv->main_irq_mask = new_mask;
977 mv_write_main_irq_mask(new_mask, hpriv);
981 static void mv_enable_port_irqs(struct ata_port *ap,
982 unsigned int port_bits)
984 unsigned int shift, hardport, port = ap->port_no;
985 u32 disable_bits, enable_bits;
987 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
989 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
990 enable_bits = port_bits << shift;
991 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
994 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
995 void __iomem *port_mmio,
996 unsigned int port_irqs)
998 struct mv_host_priv *hpriv = ap->host->private_data;
999 int hardport = mv_hardport_from_port(ap->port_no);
1000 void __iomem *hc_mmio = mv_hc_base_from_port(
1001 mv_host_base(ap->host), ap->port_no);
1004 /* clear EDMA event indicators, if any */
1005 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1007 /* clear pending irq events */
1008 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1009 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1011 /* clear FIS IRQ Cause */
1012 if (IS_GEN_IIE(hpriv))
1013 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1015 mv_enable_port_irqs(ap, port_irqs);
1018 static void mv_set_irq_coalescing(struct ata_host *host,
1019 unsigned int count, unsigned int usecs)
1021 struct mv_host_priv *hpriv = host->private_data;
1022 void __iomem *mmio = hpriv->base, *hc_mmio;
1023 u32 coal_enable = 0;
1024 unsigned long flags;
1025 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1026 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1027 ALL_PORTS_COAL_DONE;
1029 /* Disable IRQ coalescing if either threshold is zero */
1030 if (!usecs || !count) {
1033 /* Respect maximum limits of the hardware */
1034 clks = usecs * COAL_CLOCKS_PER_USEC;
1035 if (clks > MAX_COAL_TIME_THRESHOLD)
1036 clks = MAX_COAL_TIME_THRESHOLD;
1037 if (count > MAX_COAL_IO_COUNT)
1038 count = MAX_COAL_IO_COUNT;
1041 spin_lock_irqsave(&host->lock, flags);
1042 mv_set_main_irq_mask(host, coal_disable, 0);
1044 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1046 * GEN_II/GEN_IIE with dual host controllers:
1047 * one set of global thresholds for the entire chip.
1049 writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
1050 writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
1051 /* clear leftover coal IRQ bit */
1052 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
1054 coal_enable = ALL_PORTS_COAL_DONE;
1055 clks = count = 0; /* force clearing of regular regs below */
1059 * All chips: independent thresholds for each HC on the chip.
1061 hc_mmio = mv_hc_base_from_port(mmio, 0);
1062 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1063 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1064 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1066 coal_enable |= PORTS_0_3_COAL_DONE;
1068 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1069 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1070 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1071 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1073 coal_enable |= PORTS_4_7_COAL_DONE;
1076 mv_set_main_irq_mask(host, 0, coal_enable);
1077 spin_unlock_irqrestore(&host->lock, flags);
1081 * mv_start_edma - Enable eDMA engine
1082 * @base: port base address
1083 * @pp: port private data
1085 * Verify the local cache of the eDMA state is accurate with a
1089 * Inherited from caller.
1091 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1092 struct mv_port_priv *pp, u8 protocol)
1094 int want_ncq = (protocol == ATA_PROT_NCQ);
1096 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1097 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1098 if (want_ncq != using_ncq)
1101 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1102 struct mv_host_priv *hpriv = ap->host->private_data;
1104 mv_edma_cfg(ap, want_ncq, 1);
1106 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1107 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1109 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
1110 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1114 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1116 void __iomem *port_mmio = mv_ap_base(ap);
1117 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1118 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1122 * Wait for the EDMA engine to finish transactions in progress.
1123 * No idea what a good "timeout" value might be, but measurements
1124 * indicate that it often requires hundreds of microseconds
1125 * with two drives in-use. So we use the 15msec value above
1126 * as a rough guess at what even more drives might require.
1128 for (i = 0; i < timeout; ++i) {
1129 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1130 if ((edma_stat & empty_idle) == empty_idle)
1134 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1138 * mv_stop_edma_engine - Disable eDMA engine
1139 * @port_mmio: io base address
1142 * Inherited from caller.
1144 static int mv_stop_edma_engine(void __iomem *port_mmio)
1148 /* Disable eDMA. The disable bit auto clears. */
1149 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1151 /* Wait for the chip to confirm eDMA is off. */
1152 for (i = 10000; i > 0; i--) {
1153 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
1154 if (!(reg & EDMA_EN))
1161 static int mv_stop_edma(struct ata_port *ap)
1163 void __iomem *port_mmio = mv_ap_base(ap);
1164 struct mv_port_priv *pp = ap->private_data;
1167 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1169 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1170 mv_wait_for_edma_empty_idle(ap);
1171 if (mv_stop_edma_engine(port_mmio)) {
1172 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1175 mv_edma_cfg(ap, 0, 0);
1180 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1183 for (b = 0; b < bytes; ) {
1184 DPRINTK("%p: ", start + b);
1185 for (w = 0; b < bytes && w < 4; w++) {
1186 printk("%08x ", readl(start + b));
1194 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1199 for (b = 0; b < bytes; ) {
1200 DPRINTK("%02x: ", b);
1201 for (w = 0; b < bytes && w < 4; w++) {
1202 (void) pci_read_config_dword(pdev, b, &dw);
1203 printk("%08x ", dw);
1210 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1211 struct pci_dev *pdev)
1214 void __iomem *hc_base = mv_hc_base(mmio_base,
1215 port >> MV_PORT_HC_SHIFT);
1216 void __iomem *port_base;
1217 int start_port, num_ports, p, start_hc, num_hcs, hc;
1220 start_hc = start_port = 0;
1221 num_ports = 8; /* shld be benign for 4 port devs */
1224 start_hc = port >> MV_PORT_HC_SHIFT;
1226 num_ports = num_hcs = 1;
1228 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1229 num_ports > 1 ? num_ports - 1 : start_port);
1232 DPRINTK("PCI config space regs:\n");
1233 mv_dump_pci_cfg(pdev, 0x68);
1235 DPRINTK("PCI regs:\n");
1236 mv_dump_mem(mmio_base+0xc00, 0x3c);
1237 mv_dump_mem(mmio_base+0xd00, 0x34);
1238 mv_dump_mem(mmio_base+0xf00, 0x4);
1239 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1240 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1241 hc_base = mv_hc_base(mmio_base, hc);
1242 DPRINTK("HC regs (HC %i):\n", hc);
1243 mv_dump_mem(hc_base, 0x1c);
1245 for (p = start_port; p < start_port + num_ports; p++) {
1246 port_base = mv_port_base(mmio_base, p);
1247 DPRINTK("EDMA regs (port %i):\n", p);
1248 mv_dump_mem(port_base, 0x54);
1249 DPRINTK("SATA regs (port %i):\n", p);
1250 mv_dump_mem(port_base+0x300, 0x60);
1255 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1259 switch (sc_reg_in) {
1263 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1266 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1275 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1277 unsigned int ofs = mv_scr_offset(sc_reg_in);
1279 if (ofs != 0xffffffffU) {
1280 *val = readl(mv_ap_base(link->ap) + ofs);
1286 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1288 unsigned int ofs = mv_scr_offset(sc_reg_in);
1290 if (ofs != 0xffffffffU) {
1291 writelfl(val, mv_ap_base(link->ap) + ofs);
1297 static void mv6_dev_config(struct ata_device *adev)
1300 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1302 * Gen-II does not support NCQ over a port multiplier
1303 * (no FIS-based switching).
1305 if (adev->flags & ATA_DFLAG_NCQ) {
1306 if (sata_pmp_attached(adev->link->ap)) {
1307 adev->flags &= ~ATA_DFLAG_NCQ;
1308 ata_dev_printk(adev, KERN_INFO,
1309 "NCQ disabled for command-based switching\n");
1314 static int mv_qc_defer(struct ata_queued_cmd *qc)
1316 struct ata_link *link = qc->dev->link;
1317 struct ata_port *ap = link->ap;
1318 struct mv_port_priv *pp = ap->private_data;
1321 * Don't allow new commands if we're in a delayed EH state
1322 * for NCQ and/or FIS-based switching.
1324 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1325 return ATA_DEFER_PORT;
1327 * If the port is completely idle, then allow the new qc.
1329 if (ap->nr_active_links == 0)
1333 * The port is operating in host queuing mode (EDMA) with NCQ
1334 * enabled, allow multiple NCQ commands. EDMA also allows
1335 * queueing multiple DMA commands but libata core currently
1338 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1339 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1342 return ATA_DEFER_PORT;
1345 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1347 struct mv_port_priv *pp = ap->private_data;
1348 void __iomem *port_mmio;
1350 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1351 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1352 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1354 ltmode = *old_ltmode & ~LTMODE_BIT8;
1355 haltcond = *old_haltcond | EDMA_ERR_DEV;
1358 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1359 ltmode = *old_ltmode | LTMODE_BIT8;
1361 haltcond &= ~EDMA_ERR_DEV;
1363 fiscfg |= FISCFG_WAIT_DEV_ERR;
1365 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1368 port_mmio = mv_ap_base(ap);
1369 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1370 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1371 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
1374 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1376 struct mv_host_priv *hpriv = ap->host->private_data;
1379 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1380 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1382 new = old | (1 << 22);
1384 new = old & ~(1 << 22);
1386 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1390 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1391 * @ap: Port being initialized
1393 * There are two DMA modes on these chips: basic DMA, and EDMA.
1395 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1396 * of basic DMA on the GEN_IIE versions of the chips.
1398 * This bit survives EDMA resets, and must be set for basic DMA
1399 * to function, and should be cleared when EDMA is active.
1401 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1403 struct mv_port_priv *pp = ap->private_data;
1404 u32 new, *old = &pp->cached.unknown_rsvd;
1410 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1414 * SOC chips have an issue whereby the HDD LEDs don't always blink
1415 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1416 * of the SOC takes care of it, generating a steady blink rate when
1417 * any drive on the chip is active.
1419 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1420 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1422 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1423 * LED operation works then, and provides better (more accurate) feedback.
1425 * Note that this code assumes that an SOC never has more than one HC onboard.
1427 static void mv_soc_led_blink_enable(struct ata_port *ap)
1429 struct ata_host *host = ap->host;
1430 struct mv_host_priv *hpriv = host->private_data;
1431 void __iomem *hc_mmio;
1434 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1436 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1437 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1438 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1439 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1442 static void mv_soc_led_blink_disable(struct ata_port *ap)
1444 struct ata_host *host = ap->host;
1445 struct mv_host_priv *hpriv = host->private_data;
1446 void __iomem *hc_mmio;
1450 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1453 /* disable led-blink only if no ports are using NCQ */
1454 for (port = 0; port < hpriv->n_ports; port++) {
1455 struct ata_port *this_ap = host->ports[port];
1456 struct mv_port_priv *pp = this_ap->private_data;
1458 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1462 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1463 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1464 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1465 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1468 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1471 struct mv_port_priv *pp = ap->private_data;
1472 struct mv_host_priv *hpriv = ap->host->private_data;
1473 void __iomem *port_mmio = mv_ap_base(ap);
1475 /* set up non-NCQ EDMA configuration */
1476 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1478 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1480 if (IS_GEN_I(hpriv))
1481 cfg |= (1 << 8); /* enab config burst size mask */
1483 else if (IS_GEN_II(hpriv)) {
1484 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1485 mv_60x1_errata_sata25(ap, want_ncq);
1487 } else if (IS_GEN_IIE(hpriv)) {
1488 int want_fbs = sata_pmp_attached(ap);
1490 * Possible future enhancement:
1492 * The chip can use FBS with non-NCQ, if we allow it,
1493 * But first we need to have the error handling in place
1494 * for this mode (datasheet section 7.3.15.4.2.3).
1495 * So disallow non-NCQ FBS for now.
1497 want_fbs &= want_ncq;
1499 mv_config_fbs(ap, want_ncq, want_fbs);
1502 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1503 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1506 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1508 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1510 cfg |= (1 << 18); /* enab early completion */
1512 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1513 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1514 mv_bmdma_enable_iie(ap, !want_edma);
1516 if (IS_SOC(hpriv)) {
1518 mv_soc_led_blink_enable(ap);
1520 mv_soc_led_blink_disable(ap);
1525 cfg |= EDMA_CFG_NCQ;
1526 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1529 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1532 static void mv_port_free_dma_mem(struct ata_port *ap)
1534 struct mv_host_priv *hpriv = ap->host->private_data;
1535 struct mv_port_priv *pp = ap->private_data;
1539 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1543 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1547 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1548 * For later hardware, we have one unique sg_tbl per NCQ tag.
1550 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1551 if (pp->sg_tbl[tag]) {
1552 if (tag == 0 || !IS_GEN_I(hpriv))
1553 dma_pool_free(hpriv->sg_tbl_pool,
1555 pp->sg_tbl_dma[tag]);
1556 pp->sg_tbl[tag] = NULL;
1562 * mv_port_start - Port specific init/start routine.
1563 * @ap: ATA channel to manipulate
1565 * Allocate and point to DMA memory, init port private memory,
1569 * Inherited from caller.
1571 static int mv_port_start(struct ata_port *ap)
1573 struct device *dev = ap->host->dev;
1574 struct mv_host_priv *hpriv = ap->host->private_data;
1575 struct mv_port_priv *pp;
1578 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1581 ap->private_data = pp;
1583 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1586 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1588 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1590 goto out_port_free_dma_mem;
1591 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1593 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1594 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1595 ap->flags |= ATA_FLAG_AN;
1597 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1598 * For later hardware, we need one unique sg_tbl per NCQ tag.
1600 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1601 if (tag == 0 || !IS_GEN_I(hpriv)) {
1602 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1603 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1604 if (!pp->sg_tbl[tag])
1605 goto out_port_free_dma_mem;
1607 pp->sg_tbl[tag] = pp->sg_tbl[0];
1608 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1611 mv_save_cached_regs(ap);
1612 mv_edma_cfg(ap, 0, 0);
1615 out_port_free_dma_mem:
1616 mv_port_free_dma_mem(ap);
1621 * mv_port_stop - Port specific cleanup/stop routine.
1622 * @ap: ATA channel to manipulate
1624 * Stop DMA, cleanup port memory.
1627 * This routine uses the host lock to protect the DMA stop.
1629 static void mv_port_stop(struct ata_port *ap)
1632 mv_enable_port_irqs(ap, 0);
1633 mv_port_free_dma_mem(ap);
1637 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1638 * @qc: queued command whose SG list to source from
1640 * Populate the SG list and mark the last entry.
1643 * Inherited from caller.
1645 static void mv_fill_sg(struct ata_queued_cmd *qc)
1647 struct mv_port_priv *pp = qc->ap->private_data;
1648 struct scatterlist *sg;
1649 struct mv_sg *mv_sg, *last_sg = NULL;
1652 mv_sg = pp->sg_tbl[qc->tag];
1653 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1654 dma_addr_t addr = sg_dma_address(sg);
1655 u32 sg_len = sg_dma_len(sg);
1658 u32 offset = addr & 0xffff;
1661 if (offset + len > 0x10000)
1662 len = 0x10000 - offset;
1664 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1665 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1666 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1667 mv_sg->reserved = 0;
1677 if (likely(last_sg))
1678 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1679 mb(); /* ensure data structure is visible to the chipset */
1682 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1684 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1685 (last ? CRQB_CMD_LAST : 0);
1686 *cmdw = cpu_to_le16(tmp);
1690 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1691 * @ap: Port associated with this ATA transaction.
1693 * We need this only for ATAPI bmdma transactions,
1694 * as otherwise we experience spurious interrupts
1695 * after libata-sff handles the bmdma interrupts.
1697 static void mv_sff_irq_clear(struct ata_port *ap)
1699 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1703 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1704 * @qc: queued command to check for chipset/DMA compatibility.
1706 * The bmdma engines cannot handle speculative data sizes
1707 * (bytecount under/over flow). So only allow DMA for
1708 * data transfer commands with known data sizes.
1711 * Inherited from caller.
1713 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1715 struct scsi_cmnd *scmd = qc->scsicmd;
1718 switch (scmd->cmnd[0]) {
1726 case GPCMD_SEND_DVD_STRUCTURE:
1727 case GPCMD_SEND_CUE_SHEET:
1728 return 0; /* DMA is safe */
1731 return -EOPNOTSUPP; /* use PIO instead */
1735 * mv_bmdma_setup - Set up BMDMA transaction
1736 * @qc: queued command to prepare DMA for.
1739 * Inherited from caller.
1741 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1743 struct ata_port *ap = qc->ap;
1744 void __iomem *port_mmio = mv_ap_base(ap);
1745 struct mv_port_priv *pp = ap->private_data;
1749 /* clear all DMA cmd bits */
1750 writel(0, port_mmio + BMDMA_CMD_OFS);
1752 /* load PRD table addr. */
1753 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1754 port_mmio + BMDMA_PRD_HIGH_OFS);
1755 writelfl(pp->sg_tbl_dma[qc->tag],
1756 port_mmio + BMDMA_PRD_LOW_OFS);
1758 /* issue r/w command */
1759 ap->ops->sff_exec_command(ap, &qc->tf);
1763 * mv_bmdma_start - Start a BMDMA transaction
1764 * @qc: queued command to start DMA on.
1767 * Inherited from caller.
1769 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1771 struct ata_port *ap = qc->ap;
1772 void __iomem *port_mmio = mv_ap_base(ap);
1773 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1774 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1776 /* start host DMA transaction */
1777 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1781 * mv_bmdma_stop - Stop BMDMA transfer
1782 * @qc: queued command to stop DMA on.
1784 * Clears the ATA_DMA_START flag in the bmdma control register
1787 * Inherited from caller.
1789 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1791 struct ata_port *ap = qc->ap;
1792 void __iomem *port_mmio = mv_ap_base(ap);
1795 /* clear start/stop bit */
1796 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1797 cmd &= ~ATA_DMA_START;
1798 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1800 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1801 ata_sff_dma_pause(ap);
1805 * mv_bmdma_status - Read BMDMA status
1806 * @ap: port for which to retrieve DMA status.
1808 * Read and return equivalent of the sff BMDMA status register.
1811 * Inherited from caller.
1813 static u8 mv_bmdma_status(struct ata_port *ap)
1815 void __iomem *port_mmio = mv_ap_base(ap);
1819 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1820 * and the ATA_DMA_INTR bit doesn't exist.
1822 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1823 if (reg & ATA_DMA_ACTIVE)
1824 status = ATA_DMA_ACTIVE;
1826 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1831 * mv_qc_prep - Host specific command preparation.
1832 * @qc: queued command to prepare
1834 * This routine simply redirects to the general purpose routine
1835 * if command is not DMA. Else, it handles prep of the CRQB
1836 * (command request block), does some sanity checking, and calls
1837 * the SG load routine.
1840 * Inherited from caller.
1842 static void mv_qc_prep(struct ata_queued_cmd *qc)
1844 struct ata_port *ap = qc->ap;
1845 struct mv_port_priv *pp = ap->private_data;
1847 struct ata_taskfile *tf;
1851 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1852 (qc->tf.protocol != ATA_PROT_NCQ))
1855 /* Fill in command request block
1857 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1858 flags |= CRQB_FLAG_READ;
1859 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1860 flags |= qc->tag << CRQB_TAG_SHIFT;
1861 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1863 /* get current queue index from software */
1864 in_index = pp->req_idx;
1866 pp->crqb[in_index].sg_addr =
1867 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1868 pp->crqb[in_index].sg_addr_hi =
1869 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1870 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1872 cw = &pp->crqb[in_index].ata_cmd[0];
1875 /* Sadly, the CRQB cannot accomodate all registers--there are
1876 * only 11 bytes...so we must pick and choose required
1877 * registers based on the command. So, we drop feature and
1878 * hob_feature for [RW] DMA commands, but they are needed for
1879 * NCQ. NCQ will drop hob_nsect, which is not needed there
1880 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1882 switch (tf->command) {
1884 case ATA_CMD_READ_EXT:
1886 case ATA_CMD_WRITE_EXT:
1887 case ATA_CMD_WRITE_FUA_EXT:
1888 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1890 case ATA_CMD_FPDMA_READ:
1891 case ATA_CMD_FPDMA_WRITE:
1892 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1893 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1896 /* The only other commands EDMA supports in non-queued and
1897 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1898 * of which are defined/used by Linux. If we get here, this
1899 * driver needs work.
1901 * FIXME: modify libata to give qc_prep a return value and
1902 * return error here.
1904 BUG_ON(tf->command);
1907 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1908 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1909 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1910 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1911 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1912 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1913 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1914 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1915 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1917 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1923 * mv_qc_prep_iie - Host specific command preparation.
1924 * @qc: queued command to prepare
1926 * This routine simply redirects to the general purpose routine
1927 * if command is not DMA. Else, it handles prep of the CRQB
1928 * (command request block), does some sanity checking, and calls
1929 * the SG load routine.
1932 * Inherited from caller.
1934 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1936 struct ata_port *ap = qc->ap;
1937 struct mv_port_priv *pp = ap->private_data;
1938 struct mv_crqb_iie *crqb;
1939 struct ata_taskfile *tf;
1943 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1944 (qc->tf.protocol != ATA_PROT_NCQ))
1947 /* Fill in Gen IIE command request block */
1948 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1949 flags |= CRQB_FLAG_READ;
1951 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1952 flags |= qc->tag << CRQB_TAG_SHIFT;
1953 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1954 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1956 /* get current queue index from software */
1957 in_index = pp->req_idx;
1959 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1960 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1961 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1962 crqb->flags = cpu_to_le32(flags);
1965 crqb->ata_cmd[0] = cpu_to_le32(
1966 (tf->command << 16) |
1969 crqb->ata_cmd[1] = cpu_to_le32(
1975 crqb->ata_cmd[2] = cpu_to_le32(
1976 (tf->hob_lbal << 0) |
1977 (tf->hob_lbam << 8) |
1978 (tf->hob_lbah << 16) |
1979 (tf->hob_feature << 24)
1981 crqb->ata_cmd[3] = cpu_to_le32(
1983 (tf->hob_nsect << 8)
1986 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1992 * mv_sff_check_status - fetch device status, if valid
1993 * @ap: ATA port to fetch status from
1995 * When using command issue via mv_qc_issue_fis(),
1996 * the initial ATA_BUSY state does not show up in the
1997 * ATA status (shadow) register. This can confuse libata!
1999 * So we have a hook here to fake ATA_BUSY for that situation,
2000 * until the first time a BUSY, DRQ, or ERR bit is seen.
2002 * The rest of the time, it simply returns the ATA status register.
2004 static u8 mv_sff_check_status(struct ata_port *ap)
2006 u8 stat = ioread8(ap->ioaddr.status_addr);
2007 struct mv_port_priv *pp = ap->private_data;
2009 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2010 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2011 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2019 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2020 * @fis: fis to be sent
2021 * @nwords: number of 32-bit words in the fis
2023 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2025 void __iomem *port_mmio = mv_ap_base(ap);
2026 u32 ifctl, old_ifctl, ifstat;
2027 int i, timeout = 200, final_word = nwords - 1;
2029 /* Initiate FIS transmission mode */
2030 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
2031 ifctl = 0x100 | (old_ifctl & 0xf);
2032 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
2034 /* Send all words of the FIS except for the final word */
2035 for (i = 0; i < final_word; ++i)
2036 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2038 /* Flag end-of-transmission, and then send the final word */
2039 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
2040 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2043 * Wait for FIS transmission to complete.
2044 * This typically takes just a single iteration.
2047 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
2048 } while (!(ifstat & 0x1000) && --timeout);
2050 /* Restore original port configuration */
2051 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
2053 /* See if it worked */
2054 if ((ifstat & 0x3000) != 0x1000) {
2055 ata_port_printk(ap, KERN_WARNING,
2056 "%s transmission error, ifstat=%08x\n",
2058 return AC_ERR_OTHER;
2064 * mv_qc_issue_fis - Issue a command directly as a FIS
2065 * @qc: queued command to start
2067 * Note that the ATA shadow registers are not updated
2068 * after command issue, so the device will appear "READY"
2069 * if polled, even while it is BUSY processing the command.
2071 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2073 * Note: we don't get updated shadow regs on *completion*
2074 * of non-data commands. So avoid sending them via this function,
2075 * as they will appear to have completed immediately.
2077 * GEN_IIE has special registers that we could get the result tf from,
2078 * but earlier chipsets do not. For now, we ignore those registers.
2080 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2082 struct ata_port *ap = qc->ap;
2083 struct mv_port_priv *pp = ap->private_data;
2084 struct ata_link *link = qc->dev->link;
2088 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2089 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2093 switch (qc->tf.protocol) {
2094 case ATAPI_PROT_PIO:
2095 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2097 case ATAPI_PROT_NODATA:
2098 ap->hsm_task_state = HSM_ST_FIRST;
2101 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2102 if (qc->tf.flags & ATA_TFLAG_WRITE)
2103 ap->hsm_task_state = HSM_ST_FIRST;
2105 ap->hsm_task_state = HSM_ST;
2108 ap->hsm_task_state = HSM_ST_LAST;
2112 if (qc->tf.flags & ATA_TFLAG_POLLING)
2113 ata_pio_queue_task(ap, qc, 0);
2118 * mv_qc_issue - Initiate a command to the host
2119 * @qc: queued command to start
2121 * This routine simply redirects to the general purpose routine
2122 * if command is not DMA. Else, it sanity checks our local
2123 * caches of the request producer/consumer indices then enables
2124 * DMA and bumps the request producer index.
2127 * Inherited from caller.
2129 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2131 static int limit_warnings = 10;
2132 struct ata_port *ap = qc->ap;
2133 void __iomem *port_mmio = mv_ap_base(ap);
2134 struct mv_port_priv *pp = ap->private_data;
2136 unsigned int port_irqs;
2138 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2140 switch (qc->tf.protocol) {
2143 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2144 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2145 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2147 /* Write the request in pointer to kick the EDMA to life */
2148 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2149 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
2154 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2156 * Someday, we might implement special polling workarounds
2157 * for these, but it all seems rather unnecessary since we
2158 * normally use only DMA for commands which transfer more
2159 * than a single block of data.
2161 * Much of the time, this could just work regardless.
2162 * So for now, just log the incident, and allow the attempt.
2164 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2166 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2167 ": attempting PIO w/multiple DRQ: "
2168 "this may fail due to h/w errata\n");
2171 case ATA_PROT_NODATA:
2172 case ATAPI_PROT_PIO:
2173 case ATAPI_PROT_NODATA:
2174 if (ap->flags & ATA_FLAG_PIO_POLLING)
2175 qc->tf.flags |= ATA_TFLAG_POLLING;
2179 if (qc->tf.flags & ATA_TFLAG_POLLING)
2180 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2182 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2185 * We're about to send a non-EDMA capable command to the
2186 * port. Turn off EDMA so there won't be problems accessing
2187 * shadow block, etc registers.
2190 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2191 mv_pmp_select(ap, qc->dev->link->pmp);
2193 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2194 struct mv_host_priv *hpriv = ap->host->private_data;
2196 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2198 * After any NCQ error, the READ_LOG_EXT command
2199 * from libata-eh *must* use mv_qc_issue_fis().
2200 * Otherwise it might fail, due to chip errata.
2202 * Rather than special-case it, we'll just *always*
2203 * use this method here for READ_LOG_EXT, making for
2206 if (IS_GEN_II(hpriv))
2207 return mv_qc_issue_fis(qc);
2209 return ata_sff_qc_issue(qc);
2212 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2214 struct mv_port_priv *pp = ap->private_data;
2215 struct ata_queued_cmd *qc;
2217 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2219 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2221 if (qc->tf.flags & ATA_TFLAG_POLLING)
2223 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2229 static void mv_pmp_error_handler(struct ata_port *ap)
2231 unsigned int pmp, pmp_map;
2232 struct mv_port_priv *pp = ap->private_data;
2234 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2236 * Perform NCQ error analysis on failed PMPs
2237 * before we freeze the port entirely.
2239 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2241 pmp_map = pp->delayed_eh_pmp_map;
2242 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2243 for (pmp = 0; pmp_map != 0; pmp++) {
2244 unsigned int this_pmp = (1 << pmp);
2245 if (pmp_map & this_pmp) {
2246 struct ata_link *link = &ap->pmp_link[pmp];
2247 pmp_map &= ~this_pmp;
2248 ata_eh_analyze_ncq_error(link);
2251 ata_port_freeze(ap);
2253 sata_pmp_error_handler(ap);
2256 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2258 void __iomem *port_mmio = mv_ap_base(ap);
2260 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2263 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2265 struct ata_eh_info *ehi;
2269 * Initialize EH info for PMPs which saw device errors
2271 ehi = &ap->link.eh_info;
2272 for (pmp = 0; pmp_map != 0; pmp++) {
2273 unsigned int this_pmp = (1 << pmp);
2274 if (pmp_map & this_pmp) {
2275 struct ata_link *link = &ap->pmp_link[pmp];
2277 pmp_map &= ~this_pmp;
2278 ehi = &link->eh_info;
2279 ata_ehi_clear_desc(ehi);
2280 ata_ehi_push_desc(ehi, "dev err");
2281 ehi->err_mask |= AC_ERR_DEV;
2282 ehi->action |= ATA_EH_RESET;
2283 ata_link_abort(link);
2288 static int mv_req_q_empty(struct ata_port *ap)
2290 void __iomem *port_mmio = mv_ap_base(ap);
2291 u32 in_ptr, out_ptr;
2293 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2294 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2295 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2296 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2297 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2300 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2302 struct mv_port_priv *pp = ap->private_data;
2304 unsigned int old_map, new_map;
2307 * Device error during FBS+NCQ operation:
2309 * Set a port flag to prevent further I/O being enqueued.
2310 * Leave the EDMA running to drain outstanding commands from this port.
2311 * Perform the post-mortem/EH only when all responses are complete.
2312 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2314 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2315 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2316 pp->delayed_eh_pmp_map = 0;
2318 old_map = pp->delayed_eh_pmp_map;
2319 new_map = old_map | mv_get_err_pmp_map(ap);
2321 if (old_map != new_map) {
2322 pp->delayed_eh_pmp_map = new_map;
2323 mv_pmp_eh_prep(ap, new_map & ~old_map);
2325 failed_links = hweight16(new_map);
2327 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2328 "failed_links=%d nr_active_links=%d\n",
2329 __func__, pp->delayed_eh_pmp_map,
2330 ap->qc_active, failed_links,
2331 ap->nr_active_links);
2333 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2334 mv_process_crpb_entries(ap, pp);
2337 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2338 return 1; /* handled */
2340 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2341 return 1; /* handled */
2344 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2347 * Possible future enhancement:
2349 * FBS+non-NCQ operation is not yet implemented.
2350 * See related notes in mv_edma_cfg().
2352 * Device error during FBS+non-NCQ operation:
2354 * We need to snapshot the shadow registers for each failed command.
2355 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2357 return 0; /* not handled */
2360 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2362 struct mv_port_priv *pp = ap->private_data;
2364 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2365 return 0; /* EDMA was not active: not handled */
2366 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2367 return 0; /* FBS was not active: not handled */
2369 if (!(edma_err_cause & EDMA_ERR_DEV))
2370 return 0; /* non DEV error: not handled */
2371 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2372 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2373 return 0; /* other problems: not handled */
2375 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2377 * EDMA should NOT have self-disabled for this case.
2378 * If it did, then something is wrong elsewhere,
2379 * and we cannot handle it here.
2381 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2382 ata_port_printk(ap, KERN_WARNING,
2383 "%s: err_cause=0x%x pp_flags=0x%x\n",
2384 __func__, edma_err_cause, pp->pp_flags);
2385 return 0; /* not handled */
2387 return mv_handle_fbs_ncq_dev_err(ap);
2390 * EDMA should have self-disabled for this case.
2391 * If it did not, then something is wrong elsewhere,
2392 * and we cannot handle it here.
2394 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2395 ata_port_printk(ap, KERN_WARNING,
2396 "%s: err_cause=0x%x pp_flags=0x%x\n",
2397 __func__, edma_err_cause, pp->pp_flags);
2398 return 0; /* not handled */
2400 return mv_handle_fbs_non_ncq_dev_err(ap);
2402 return 0; /* not handled */
2405 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2407 struct ata_eh_info *ehi = &ap->link.eh_info;
2408 char *when = "idle";
2410 ata_ehi_clear_desc(ehi);
2411 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2413 } else if (edma_was_enabled) {
2414 when = "EDMA enabled";
2416 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2417 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2420 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2421 ehi->err_mask |= AC_ERR_OTHER;
2422 ehi->action |= ATA_EH_RESET;
2423 ata_port_freeze(ap);
2427 * mv_err_intr - Handle error interrupts on the port
2428 * @ap: ATA channel to manipulate
2430 * Most cases require a full reset of the chip's state machine,
2431 * which also performs a COMRESET.
2432 * Also, if the port disabled DMA, update our cached copy to match.
2435 * Inherited from caller.
2437 static void mv_err_intr(struct ata_port *ap)
2439 void __iomem *port_mmio = mv_ap_base(ap);
2440 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2442 struct mv_port_priv *pp = ap->private_data;
2443 struct mv_host_priv *hpriv = ap->host->private_data;
2444 unsigned int action = 0, err_mask = 0;
2445 struct ata_eh_info *ehi = &ap->link.eh_info;
2446 struct ata_queued_cmd *qc;
2450 * Read and clear the SError and err_cause bits.
2451 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2452 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2454 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2455 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2457 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2458 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2459 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2460 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2462 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2464 if (edma_err_cause & EDMA_ERR_DEV) {
2466 * Device errors during FIS-based switching operation
2467 * require special handling.
2469 if (mv_handle_dev_err(ap, edma_err_cause))
2473 qc = mv_get_active_qc(ap);
2474 ata_ehi_clear_desc(ehi);
2475 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2476 edma_err_cause, pp->pp_flags);
2478 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2479 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2480 if (fis_cause & SATA_FIS_IRQ_AN) {
2481 u32 ec = edma_err_cause &
2482 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2483 sata_async_notification(ap);
2485 return; /* Just an AN; no need for the nukes */
2486 ata_ehi_push_desc(ehi, "SDB notify");
2490 * All generations share these EDMA error cause bits:
2492 if (edma_err_cause & EDMA_ERR_DEV) {
2493 err_mask |= AC_ERR_DEV;
2494 action |= ATA_EH_RESET;
2495 ata_ehi_push_desc(ehi, "dev error");
2497 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2498 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2499 EDMA_ERR_INTRL_PAR)) {
2500 err_mask |= AC_ERR_ATA_BUS;
2501 action |= ATA_EH_RESET;
2502 ata_ehi_push_desc(ehi, "parity error");
2504 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2505 ata_ehi_hotplugged(ehi);
2506 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2507 "dev disconnect" : "dev connect");
2508 action |= ATA_EH_RESET;
2512 * Gen-I has a different SELF_DIS bit,
2513 * different FREEZE bits, and no SERR bit:
2515 if (IS_GEN_I(hpriv)) {
2516 eh_freeze_mask = EDMA_EH_FREEZE_5;
2517 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2518 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2519 ata_ehi_push_desc(ehi, "EDMA self-disable");
2522 eh_freeze_mask = EDMA_EH_FREEZE;
2523 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2524 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2525 ata_ehi_push_desc(ehi, "EDMA self-disable");
2527 if (edma_err_cause & EDMA_ERR_SERR) {
2528 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2529 err_mask |= AC_ERR_ATA_BUS;
2530 action |= ATA_EH_RESET;
2535 err_mask = AC_ERR_OTHER;
2536 action |= ATA_EH_RESET;
2539 ehi->serror |= serr;
2540 ehi->action |= action;
2543 qc->err_mask |= err_mask;
2545 ehi->err_mask |= err_mask;
2547 if (err_mask == AC_ERR_DEV) {
2549 * Cannot do ata_port_freeze() here,
2550 * because it would kill PIO access,
2551 * which is needed for further diagnosis.
2555 } else if (edma_err_cause & eh_freeze_mask) {
2557 * Note to self: ata_port_freeze() calls ata_port_abort()
2559 ata_port_freeze(ap);
2566 ata_link_abort(qc->dev->link);
2572 static void mv_process_crpb_response(struct ata_port *ap,
2573 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2575 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2579 u16 edma_status = le16_to_cpu(response->flags);
2581 * edma_status from a response queue entry:
2582 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2583 * MSB is saved ATA status from command completion.
2586 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2589 * Error will be seen/handled by mv_err_intr().
2590 * So do nothing at all here.
2595 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2596 if (!ac_err_mask(ata_status))
2597 ata_qc_complete(qc);
2598 /* else: leave it for mv_err_intr() */
2600 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2605 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2607 void __iomem *port_mmio = mv_ap_base(ap);
2608 struct mv_host_priv *hpriv = ap->host->private_data;
2610 bool work_done = false;
2611 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2613 /* Get the hardware queue position index */
2614 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2615 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2617 /* Process new responses from since the last time we looked */
2618 while (in_index != pp->resp_idx) {
2620 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2622 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2624 if (IS_GEN_I(hpriv)) {
2625 /* 50xx: no NCQ, only one command active at a time */
2626 tag = ap->link.active_tag;
2628 /* Gen II/IIE: get command tag from CRPB entry */
2629 tag = le16_to_cpu(response->id) & 0x1f;
2631 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2635 /* Update the software queue position index in hardware */
2637 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2638 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2639 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2642 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2644 struct mv_port_priv *pp;
2645 int edma_was_enabled;
2647 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2648 mv_unexpected_intr(ap, 0);
2652 * Grab a snapshot of the EDMA_EN flag setting,
2653 * so that we have a consistent view for this port,
2654 * even if something we call of our routines changes it.
2656 pp = ap->private_data;
2657 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2659 * Process completed CRPB response(s) before other events.
2661 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2662 mv_process_crpb_entries(ap, pp);
2663 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2664 mv_handle_fbs_ncq_dev_err(ap);
2667 * Handle chip-reported errors, or continue on to handle PIO.
2669 if (unlikely(port_cause & ERR_IRQ)) {
2671 } else if (!edma_was_enabled) {
2672 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2674 ata_sff_host_intr(ap, qc);
2676 mv_unexpected_intr(ap, edma_was_enabled);
2681 * mv_host_intr - Handle all interrupts on the given host controller
2682 * @host: host specific structure
2683 * @main_irq_cause: Main interrupt cause register for the chip.
2686 * Inherited from caller.
2688 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2690 struct mv_host_priv *hpriv = host->private_data;
2691 void __iomem *mmio = hpriv->base, *hc_mmio;
2692 unsigned int handled = 0, port;
2694 /* If asserted, clear the "all ports" IRQ coalescing bit */
2695 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2696 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
2698 for (port = 0; port < hpriv->n_ports; port++) {
2699 struct ata_port *ap = host->ports[port];
2700 unsigned int p, shift, hardport, port_cause;
2702 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2704 * Each hc within the host has its own hc_irq_cause register,
2705 * where the interrupting ports bits get ack'd.
2707 if (hardport == 0) { /* first port on this hc ? */
2708 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2709 u32 port_mask, ack_irqs;
2711 * Skip this entire hc if nothing pending for any ports
2714 port += MV_PORTS_PER_HC - 1;
2718 * We don't need/want to read the hc_irq_cause register,
2719 * because doing so hurts performance, and
2720 * main_irq_cause already gives us everything we need.
2722 * But we do have to *write* to the hc_irq_cause to ack
2723 * the ports that we are handling this time through.
2725 * This requires that we create a bitmap for those
2726 * ports which interrupted us, and use that bitmap
2727 * to ack (only) those ports via hc_irq_cause.
2730 if (hc_cause & PORTS_0_3_COAL_DONE)
2731 ack_irqs = HC_COAL_IRQ;
2732 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2733 if ((port + p) >= hpriv->n_ports)
2735 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2736 if (hc_cause & port_mask)
2737 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2739 hc_mmio = mv_hc_base_from_port(mmio, port);
2740 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2744 * Handle interrupts signalled for this port:
2746 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2748 mv_port_intr(ap, port_cause);
2753 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2755 struct mv_host_priv *hpriv = host->private_data;
2756 struct ata_port *ap;
2757 struct ata_queued_cmd *qc;
2758 struct ata_eh_info *ehi;
2759 unsigned int i, err_mask, printed = 0;
2762 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2764 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2767 DPRINTK("All regs @ PCI error\n");
2768 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2770 writelfl(0, mmio + hpriv->irq_cause_ofs);
2772 for (i = 0; i < host->n_ports; i++) {
2773 ap = host->ports[i];
2774 if (!ata_link_offline(&ap->link)) {
2775 ehi = &ap->link.eh_info;
2776 ata_ehi_clear_desc(ehi);
2778 ata_ehi_push_desc(ehi,
2779 "PCI err cause 0x%08x", err_cause);
2780 err_mask = AC_ERR_HOST_BUS;
2781 ehi->action = ATA_EH_RESET;
2782 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2784 qc->err_mask |= err_mask;
2786 ehi->err_mask |= err_mask;
2788 ata_port_freeze(ap);
2791 return 1; /* handled */
2795 * mv_interrupt - Main interrupt event handler
2797 * @dev_instance: private data; in this case the host structure
2799 * Read the read only register to determine if any host
2800 * controllers have pending interrupts. If so, call lower level
2801 * routine to handle. Also check for PCI errors which are only
2805 * This routine holds the host lock while processing pending
2808 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2810 struct ata_host *host = dev_instance;
2811 struct mv_host_priv *hpriv = host->private_data;
2812 unsigned int handled = 0;
2813 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2814 u32 main_irq_cause, pending_irqs;
2816 spin_lock(&host->lock);
2818 /* for MSI: block new interrupts while in here */
2820 mv_write_main_irq_mask(0, hpriv);
2822 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2823 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2825 * Deal with cases where we either have nothing pending, or have read
2826 * a bogus register value which can indicate HW removal or PCI fault.
2828 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2829 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2830 handled = mv_pci_error(host, hpriv->base);
2832 handled = mv_host_intr(host, pending_irqs);
2835 /* for MSI: unmask; interrupt cause bits will retrigger now */
2837 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2839 spin_unlock(&host->lock);
2841 return IRQ_RETVAL(handled);
2844 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2848 switch (sc_reg_in) {
2852 ofs = sc_reg_in * sizeof(u32);
2861 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2863 struct mv_host_priv *hpriv = link->ap->host->private_data;
2864 void __iomem *mmio = hpriv->base;
2865 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2866 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2868 if (ofs != 0xffffffffU) {
2869 *val = readl(addr + ofs);
2875 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2877 struct mv_host_priv *hpriv = link->ap->host->private_data;
2878 void __iomem *mmio = hpriv->base;
2879 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2880 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2882 if (ofs != 0xffffffffU) {
2883 writelfl(val, addr + ofs);
2889 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2891 struct pci_dev *pdev = to_pci_dev(host->dev);
2894 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2897 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2899 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2902 mv_reset_pci_bus(host, mmio);
2905 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2907 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2910 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2913 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2916 tmp = readl(phy_mmio + MV5_PHY_MODE);
2918 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2919 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2922 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2926 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2928 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2930 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2932 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2935 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2938 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2939 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2941 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2944 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2946 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2948 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2951 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2954 tmp = readl(phy_mmio + MV5_PHY_MODE);
2956 tmp |= hpriv->signal[port].pre;
2957 tmp |= hpriv->signal[port].amps;
2958 writel(tmp, phy_mmio + MV5_PHY_MODE);
2963 #define ZERO(reg) writel(0, port_mmio + (reg))
2964 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2967 void __iomem *port_mmio = mv_port_base(mmio, port);
2969 mv_reset_channel(hpriv, mmio, port);
2971 ZERO(0x028); /* command */
2972 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2973 ZERO(0x004); /* timer */
2974 ZERO(0x008); /* irq err cause */
2975 ZERO(0x00c); /* irq err mask */
2976 ZERO(0x010); /* rq bah */
2977 ZERO(0x014); /* rq inp */
2978 ZERO(0x018); /* rq outp */
2979 ZERO(0x01c); /* respq bah */
2980 ZERO(0x024); /* respq outp */
2981 ZERO(0x020); /* respq inp */
2982 ZERO(0x02c); /* test control */
2983 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2987 #define ZERO(reg) writel(0, hc_mmio + (reg))
2988 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2991 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2999 tmp = readl(hc_mmio + 0x20);
3002 writel(tmp, hc_mmio + 0x20);
3006 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3009 unsigned int hc, port;
3011 for (hc = 0; hc < n_hc; hc++) {
3012 for (port = 0; port < MV_PORTS_PER_HC; port++)
3013 mv5_reset_hc_port(hpriv, mmio,
3014 (hc * MV_PORTS_PER_HC) + port);
3016 mv5_reset_one_hc(hpriv, mmio, hc);
3023 #define ZERO(reg) writel(0, mmio + (reg))
3024 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3026 struct mv_host_priv *hpriv = host->private_data;
3029 tmp = readl(mmio + MV_PCI_MODE_OFS);
3031 writel(tmp, mmio + MV_PCI_MODE_OFS);
3033 ZERO(MV_PCI_DISC_TIMER);
3034 ZERO(MV_PCI_MSI_TRIGGER);
3035 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
3036 ZERO(MV_PCI_SERR_MASK);
3037 ZERO(hpriv->irq_cause_ofs);
3038 ZERO(hpriv->irq_mask_ofs);
3039 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3040 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3041 ZERO(MV_PCI_ERR_ATTRIBUTE);
3042 ZERO(MV_PCI_ERR_COMMAND);
3046 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3050 mv5_reset_flash(hpriv, mmio);
3052 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
3054 tmp |= (1 << 5) | (1 << 6);
3055 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
3059 * mv6_reset_hc - Perform the 6xxx global soft reset
3060 * @mmio: base address of the HBA
3062 * This routine only applies to 6xxx parts.
3065 * Inherited from caller.
3067 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3070 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
3074 /* Following procedure defined in PCI "main command and status
3078 writel(t | STOP_PCI_MASTER, reg);
3080 for (i = 0; i < 1000; i++) {
3083 if (PCI_MASTER_EMPTY & t)
3086 if (!(PCI_MASTER_EMPTY & t)) {
3087 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3095 writel(t | GLOB_SFT_RST, reg);
3098 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3100 if (!(GLOB_SFT_RST & t)) {
3101 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3106 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3109 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3112 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3114 if (GLOB_SFT_RST & t) {
3115 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3122 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3125 void __iomem *port_mmio;
3128 tmp = readl(mmio + MV_RESET_CFG_OFS);
3129 if ((tmp & (1 << 0)) == 0) {
3130 hpriv->signal[idx].amps = 0x7 << 8;
3131 hpriv->signal[idx].pre = 0x1 << 5;
3135 port_mmio = mv_port_base(mmio, idx);
3136 tmp = readl(port_mmio + PHY_MODE2);
3138 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3139 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3142 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3144 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
3147 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3150 void __iomem *port_mmio = mv_port_base(mmio, port);
3152 u32 hp_flags = hpriv->hp_flags;
3154 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3156 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3159 if (fix_phy_mode2) {
3160 m2 = readl(port_mmio + PHY_MODE2);
3163 writel(m2, port_mmio + PHY_MODE2);
3167 m2 = readl(port_mmio + PHY_MODE2);
3168 m2 &= ~((1 << 16) | (1 << 31));
3169 writel(m2, port_mmio + PHY_MODE2);
3175 * Gen-II/IIe PHY_MODE3 errata RM#2:
3176 * Achieves better receiver noise performance than the h/w default:
3178 m3 = readl(port_mmio + PHY_MODE3);
3179 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3181 /* Guideline 88F5182 (GL# SATA-S11) */
3185 if (fix_phy_mode4) {
3186 u32 m4 = readl(port_mmio + PHY_MODE4);
3188 * Enforce reserved-bit restrictions on GenIIe devices only.
3189 * For earlier chipsets, force only the internal config field
3190 * (workaround for errata FEr SATA#10 part 1).
3192 if (IS_GEN_IIE(hpriv))
3193 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3195 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3196 writel(m4, port_mmio + PHY_MODE4);
3199 * Workaround for 60x1-B2 errata SATA#13:
3200 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3201 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3203 writel(m3, port_mmio + PHY_MODE3);
3205 /* Revert values of pre-emphasis and signal amps to the saved ones */
3206 m2 = readl(port_mmio + PHY_MODE2);
3208 m2 &= ~MV_M2_PREAMP_MASK;
3209 m2 |= hpriv->signal[port].amps;
3210 m2 |= hpriv->signal[port].pre;
3213 /* according to mvSata 3.6.1, some IIE values are fixed */
3214 if (IS_GEN_IIE(hpriv)) {
3219 writel(m2, port_mmio + PHY_MODE2);
3222 /* TODO: use the generic LED interface to configure the SATA Presence */
3223 /* & Acitivy LEDs on the board */
3224 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3230 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3233 void __iomem *port_mmio;
3236 port_mmio = mv_port_base(mmio, idx);
3237 tmp = readl(port_mmio + PHY_MODE2);
3239 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3240 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3244 #define ZERO(reg) writel(0, port_mmio + (reg))
3245 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3246 void __iomem *mmio, unsigned int port)
3248 void __iomem *port_mmio = mv_port_base(mmio, port);
3250 mv_reset_channel(hpriv, mmio, port);
3252 ZERO(0x028); /* command */
3253 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3254 ZERO(0x004); /* timer */
3255 ZERO(0x008); /* irq err cause */
3256 ZERO(0x00c); /* irq err mask */
3257 ZERO(0x010); /* rq bah */
3258 ZERO(0x014); /* rq inp */
3259 ZERO(0x018); /* rq outp */
3260 ZERO(0x01c); /* respq bah */
3261 ZERO(0x024); /* respq outp */
3262 ZERO(0x020); /* respq inp */
3263 ZERO(0x02c); /* test control */
3264 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
3269 #define ZERO(reg) writel(0, hc_mmio + (reg))
3270 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3273 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3283 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3284 void __iomem *mmio, unsigned int n_hc)
3288 for (port = 0; port < hpriv->n_ports; port++)
3289 mv_soc_reset_hc_port(hpriv, mmio, port);
3291 mv_soc_reset_one_hc(hpriv, mmio);
3296 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3302 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3307 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3309 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
3311 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3313 ifcfg |= (1 << 7); /* enable gen2i speed */
3314 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
3317 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3318 unsigned int port_no)
3320 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3323 * The datasheet warns against setting EDMA_RESET when EDMA is active
3324 * (but doesn't say what the problem might be). So we first try
3325 * to disable the EDMA engine before doing the EDMA_RESET operation.
3327 mv_stop_edma_engine(port_mmio);
3328 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3330 if (!IS_GEN_I(hpriv)) {
3331 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3332 mv_setup_ifcfg(port_mmio, 1);
3335 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3336 * link, and physical layers. It resets all SATA interface registers
3337 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
3339 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3340 udelay(25); /* allow reset propagation */
3341 writelfl(0, port_mmio + EDMA_CMD_OFS);
3343 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3345 if (IS_GEN_I(hpriv))
3349 static void mv_pmp_select(struct ata_port *ap, int pmp)
3351 if (sata_pmp_supported(ap)) {
3352 void __iomem *port_mmio = mv_ap_base(ap);
3353 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3354 int old = reg & 0xf;
3357 reg = (reg & ~0xf) | pmp;
3358 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3363 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3364 unsigned long deadline)
3366 mv_pmp_select(link->ap, sata_srst_pmp(link));
3367 return sata_std_hardreset(link, class, deadline);
3370 static int mv_softreset(struct ata_link *link, unsigned int *class,
3371 unsigned long deadline)
3373 mv_pmp_select(link->ap, sata_srst_pmp(link));
3374 return ata_sff_softreset(link, class, deadline);
3377 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3378 unsigned long deadline)
3380 struct ata_port *ap = link->ap;
3381 struct mv_host_priv *hpriv = ap->host->private_data;
3382 struct mv_port_priv *pp = ap->private_data;
3383 void __iomem *mmio = hpriv->base;
3384 int rc, attempts = 0, extra = 0;
3388 mv_reset_channel(hpriv, mmio, ap->port_no);
3389 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3391 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3393 /* Workaround for errata FEr SATA#10 (part 2) */
3395 const unsigned long *timing =
3396 sata_ehc_deb_timing(&link->eh_context);
3398 rc = sata_link_hardreset(link, timing, deadline + extra,
3400 rc = online ? -EAGAIN : rc;
3403 sata_scr_read(link, SCR_STATUS, &sstatus);
3404 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3405 /* Force 1.5gb/s link speed and try again */
3406 mv_setup_ifcfg(mv_ap_base(ap), 0);
3407 if (time_after(jiffies + HZ, deadline))
3408 extra = HZ; /* only extend it once, max */
3410 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3411 mv_save_cached_regs(ap);
3412 mv_edma_cfg(ap, 0, 0);
3417 static void mv_eh_freeze(struct ata_port *ap)
3420 mv_enable_port_irqs(ap, 0);
3423 static void mv_eh_thaw(struct ata_port *ap)
3425 struct mv_host_priv *hpriv = ap->host->private_data;
3426 unsigned int port = ap->port_no;
3427 unsigned int hardport = mv_hardport_from_port(port);
3428 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3429 void __iomem *port_mmio = mv_ap_base(ap);
3432 /* clear EDMA errors on this port */
3433 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3435 /* clear pending irq events */
3436 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3437 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3439 mv_enable_port_irqs(ap, ERR_IRQ);
3443 * mv_port_init - Perform some early initialization on a single port.
3444 * @port: libata data structure storing shadow register addresses
3445 * @port_mmio: base address of the port
3447 * Initialize shadow register mmio addresses, clear outstanding
3448 * interrupts on the port, and unmask interrupts for the future
3449 * start of the port.
3452 * Inherited from caller.
3454 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3456 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3459 /* PIO related setup
3461 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3463 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3464 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3465 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3466 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3467 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3468 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3470 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3471 /* special case: control/altstatus doesn't have ATA_REG_ address */
3472 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3475 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3477 /* Clear any currently outstanding port interrupt conditions */
3478 serr_ofs = mv_scr_offset(SCR_ERROR);
3479 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3480 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3482 /* unmask all non-transient EDMA error interrupts */
3483 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3485 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3486 readl(port_mmio + EDMA_CFG_OFS),
3487 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3488 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3491 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3493 struct mv_host_priv *hpriv = host->private_data;
3494 void __iomem *mmio = hpriv->base;
3497 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3498 return 0; /* not PCI-X capable */
3499 reg = readl(mmio + MV_PCI_MODE_OFS);
3500 if ((reg & MV_PCI_MODE_MASK) == 0)
3501 return 0; /* conventional PCI mode */
3502 return 1; /* chip is in PCI-X mode */
3505 static int mv_pci_cut_through_okay(struct ata_host *host)
3507 struct mv_host_priv *hpriv = host->private_data;
3508 void __iomem *mmio = hpriv->base;
3511 if (!mv_in_pcix_mode(host)) {
3512 reg = readl(mmio + PCI_COMMAND_OFS);
3513 if (reg & PCI_COMMAND_MRDTRIG)
3514 return 0; /* not okay */
3516 return 1; /* okay */
3519 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3521 struct pci_dev *pdev = to_pci_dev(host->dev);
3522 struct mv_host_priv *hpriv = host->private_data;
3523 u32 hp_flags = hpriv->hp_flags;
3525 switch (board_idx) {
3527 hpriv->ops = &mv5xxx_ops;
3528 hp_flags |= MV_HP_GEN_I;
3530 switch (pdev->revision) {
3532 hp_flags |= MV_HP_ERRATA_50XXB0;
3535 hp_flags |= MV_HP_ERRATA_50XXB2;
3538 dev_printk(KERN_WARNING, &pdev->dev,
3539 "Applying 50XXB2 workarounds to unknown rev\n");
3540 hp_flags |= MV_HP_ERRATA_50XXB2;
3547 hpriv->ops = &mv5xxx_ops;
3548 hp_flags |= MV_HP_GEN_I;
3550 switch (pdev->revision) {
3552 hp_flags |= MV_HP_ERRATA_50XXB0;
3555 hp_flags |= MV_HP_ERRATA_50XXB2;
3558 dev_printk(KERN_WARNING, &pdev->dev,
3559 "Applying B2 workarounds to unknown rev\n");
3560 hp_flags |= MV_HP_ERRATA_50XXB2;
3567 hpriv->ops = &mv6xxx_ops;
3568 hp_flags |= MV_HP_GEN_II;
3570 switch (pdev->revision) {
3572 hp_flags |= MV_HP_ERRATA_60X1B2;
3575 hp_flags |= MV_HP_ERRATA_60X1C0;
3578 dev_printk(KERN_WARNING, &pdev->dev,
3579 "Applying B2 workarounds to unknown rev\n");
3580 hp_flags |= MV_HP_ERRATA_60X1B2;
3586 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3587 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3588 (pdev->device == 0x2300 || pdev->device == 0x2310))
3591 * Highpoint RocketRAID PCIe 23xx series cards:
3593 * Unconfigured drives are treated as "Legacy"
3594 * by the BIOS, and it overwrites sector 8 with
3595 * a "Lgcy" metadata block prior to Linux boot.
3597 * Configured drives (RAID or JBOD) leave sector 8
3598 * alone, but instead overwrite a high numbered
3599 * sector for the RAID metadata. This sector can
3600 * be determined exactly, by truncating the physical
3601 * drive capacity to a nice even GB value.
3603 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3605 * Warn the user, lest they think we're just buggy.
3607 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3608 " BIOS CORRUPTS DATA on all attached drives,"
3609 " regardless of if/how they are configured."
3611 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3612 " use sectors 8-9 on \"Legacy\" drives,"
3613 " and avoid the final two gigabytes on"
3614 " all RocketRAID BIOS initialized drives.\n");
3618 hpriv->ops = &mv6xxx_ops;
3619 hp_flags |= MV_HP_GEN_IIE;
3620 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3621 hp_flags |= MV_HP_CUT_THROUGH;
3623 switch (pdev->revision) {
3624 case 0x2: /* Rev.B0: the first/only public release */
3625 hp_flags |= MV_HP_ERRATA_60X1C0;
3628 dev_printk(KERN_WARNING, &pdev->dev,
3629 "Applying 60X1C0 workarounds to unknown rev\n");
3630 hp_flags |= MV_HP_ERRATA_60X1C0;
3635 hpriv->ops = &mv_soc_ops;
3636 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3637 MV_HP_ERRATA_60X1C0;
3641 dev_printk(KERN_ERR, host->dev,
3642 "BUG: invalid board index %u\n", board_idx);
3646 hpriv->hp_flags = hp_flags;
3647 if (hp_flags & MV_HP_PCIE) {
3648 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3649 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3650 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3652 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3653 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3654 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3661 * mv_init_host - Perform some early initialization of the host.
3662 * @host: ATA host to initialize
3663 * @board_idx: controller index
3665 * If possible, do an early global reset of the host. Then do
3666 * our port init and clear/unmask all/relevant host interrupts.
3669 * Inherited from caller.
3671 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3673 int rc = 0, n_hc, port, hc;
3674 struct mv_host_priv *hpriv = host->private_data;
3675 void __iomem *mmio = hpriv->base;
3677 rc = mv_chip_id(host, board_idx);
3681 if (IS_SOC(hpriv)) {
3682 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3683 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3685 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3686 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3689 /* initialize shadow irq mask with register's value */
3690 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3692 /* global interrupt mask: 0 == mask everything */
3693 mv_set_main_irq_mask(host, ~0, 0);
3695 n_hc = mv_get_hc_count(host->ports[0]->flags);
3697 for (port = 0; port < host->n_ports; port++)
3698 hpriv->ops->read_preamp(hpriv, port, mmio);
3700 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3704 hpriv->ops->reset_flash(hpriv, mmio);
3705 hpriv->ops->reset_bus(host, mmio);
3706 hpriv->ops->enable_leds(hpriv, mmio);
3708 for (port = 0; port < host->n_ports; port++) {
3709 struct ata_port *ap = host->ports[port];
3710 void __iomem *port_mmio = mv_port_base(mmio, port);
3712 mv_port_init(&ap->ioaddr, port_mmio);
3715 if (!IS_SOC(hpriv)) {
3716 unsigned int offset = port_mmio - mmio;
3717 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3718 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3723 for (hc = 0; hc < n_hc; hc++) {
3724 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3726 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3727 "(before clear)=0x%08x\n", hc,
3728 readl(hc_mmio + HC_CFG_OFS),
3729 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3731 /* Clear any currently outstanding hc interrupt conditions */
3732 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3735 /* Clear any currently outstanding host interrupt conditions */
3736 writelfl(0, mmio + hpriv->irq_cause_ofs);
3738 /* and unmask interrupt generation for host regs */
3739 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3742 * enable only global host interrupts for now.
3743 * The per-port interrupts get done later as ports are set up.
3745 mv_set_main_irq_mask(host, 0, PCI_ERR);
3746 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3747 irq_coalescing_usecs);
3752 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3754 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3756 if (!hpriv->crqb_pool)
3759 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3761 if (!hpriv->crpb_pool)
3764 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3766 if (!hpriv->sg_tbl_pool)
3772 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3773 struct mbus_dram_target_info *dram)
3777 for (i = 0; i < 4; i++) {
3778 writel(0, hpriv->base + WINDOW_CTRL(i));
3779 writel(0, hpriv->base + WINDOW_BASE(i));
3782 for (i = 0; i < dram->num_cs; i++) {
3783 struct mbus_dram_window *cs = dram->cs + i;
3785 writel(((cs->size - 1) & 0xffff0000) |
3786 (cs->mbus_attr << 8) |
3787 (dram->mbus_dram_target_id << 4) | 1,
3788 hpriv->base + WINDOW_CTRL(i));
3789 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3794 * mv_platform_probe - handle a positive probe of an soc Marvell
3796 * @pdev: platform device found
3799 * Inherited from caller.
3801 static int mv_platform_probe(struct platform_device *pdev)
3803 static int printed_version;
3804 const struct mv_sata_platform_data *mv_platform_data;
3805 const struct ata_port_info *ppi[] =
3806 { &mv_port_info[chip_soc], NULL };
3807 struct ata_host *host;
3808 struct mv_host_priv *hpriv;
3809 struct resource *res;
3812 if (!printed_version++)
3813 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3816 * Simple resource validation ..
3818 if (unlikely(pdev->num_resources != 2)) {
3819 dev_err(&pdev->dev, "invalid number of resources\n");
3824 * Get the register base first
3826 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3831 mv_platform_data = pdev->dev.platform_data;
3832 n_ports = mv_platform_data->n_ports;
3834 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3835 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3837 if (!host || !hpriv)
3839 host->private_data = hpriv;
3840 hpriv->n_ports = n_ports;
3843 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3844 res->end - res->start + 1);
3845 hpriv->base -= MV_SATAHC0_REG_BASE;
3848 * (Re-)program MBUS remapping windows if we are asked to.
3850 if (mv_platform_data->dram != NULL)
3851 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3853 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3857 /* initialize adapter */
3858 rc = mv_init_host(host, chip_soc);
3862 dev_printk(KERN_INFO, &pdev->dev,
3863 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3866 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3867 IRQF_SHARED, &mv6_sht);
3872 * mv_platform_remove - unplug a platform interface
3873 * @pdev: platform device
3875 * A platform bus SATA device has been unplugged. Perform the needed
3876 * cleanup. Also called on module unload for any active devices.
3878 static int __devexit mv_platform_remove(struct platform_device *pdev)
3880 struct device *dev = &pdev->dev;
3881 struct ata_host *host = dev_get_drvdata(dev);
3883 ata_host_detach(host);
3887 static struct platform_driver mv_platform_driver = {
3888 .probe = mv_platform_probe,
3889 .remove = __devexit_p(mv_platform_remove),
3892 .owner = THIS_MODULE,
3898 static int mv_pci_init_one(struct pci_dev *pdev,
3899 const struct pci_device_id *ent);
3902 static struct pci_driver mv_pci_driver = {
3904 .id_table = mv_pci_tbl,
3905 .probe = mv_pci_init_one,
3906 .remove = ata_pci_remove_one,
3909 /* move to PCI layer or libata core? */
3910 static int pci_go_64(struct pci_dev *pdev)
3914 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3915 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3917 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3919 dev_printk(KERN_ERR, &pdev->dev,
3920 "64-bit DMA enable failed\n");
3925 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3927 dev_printk(KERN_ERR, &pdev->dev,
3928 "32-bit DMA enable failed\n");
3931 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3933 dev_printk(KERN_ERR, &pdev->dev,
3934 "32-bit consistent DMA enable failed\n");
3943 * mv_print_info - Dump key info to kernel log for perusal.
3944 * @host: ATA host to print info about
3946 * FIXME: complete this.
3949 * Inherited from caller.
3951 static void mv_print_info(struct ata_host *host)
3953 struct pci_dev *pdev = to_pci_dev(host->dev);
3954 struct mv_host_priv *hpriv = host->private_data;
3956 const char *scc_s, *gen;
3958 /* Use this to determine the HW stepping of the chip so we know
3959 * what errata to workaround
3961 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3964 else if (scc == 0x01)
3969 if (IS_GEN_I(hpriv))
3971 else if (IS_GEN_II(hpriv))
3973 else if (IS_GEN_IIE(hpriv))
3978 dev_printk(KERN_INFO, &pdev->dev,
3979 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3980 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3981 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3985 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3986 * @pdev: PCI device found
3987 * @ent: PCI device ID entry for the matched host
3990 * Inherited from caller.
3992 static int mv_pci_init_one(struct pci_dev *pdev,
3993 const struct pci_device_id *ent)
3995 static int printed_version;
3996 unsigned int board_idx = (unsigned int)ent->driver_data;
3997 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3998 struct ata_host *host;
3999 struct mv_host_priv *hpriv;
4002 if (!printed_version++)
4003 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4006 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4008 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4009 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4010 if (!host || !hpriv)
4012 host->private_data = hpriv;
4013 hpriv->n_ports = n_ports;
4015 /* acquire resources */
4016 rc = pcim_enable_device(pdev);
4020 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4022 pcim_pin_device(pdev);
4025 host->iomap = pcim_iomap_table(pdev);
4026 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4028 rc = pci_go_64(pdev);
4032 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4036 /* initialize adapter */
4037 rc = mv_init_host(host, board_idx);
4041 /* Enable message-switched interrupts, if requested */
4042 if (msi && pci_enable_msi(pdev) == 0)
4043 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4045 mv_dump_pci_cfg(pdev, 0x68);
4046 mv_print_info(host);
4048 pci_set_master(pdev);
4049 pci_try_set_mwi(pdev);
4050 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4051 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4055 static int mv_platform_probe(struct platform_device *pdev);
4056 static int __devexit mv_platform_remove(struct platform_device *pdev);
4058 static int __init mv_init(void)
4062 rc = pci_register_driver(&mv_pci_driver);
4066 rc = platform_driver_register(&mv_platform_driver);
4070 pci_unregister_driver(&mv_pci_driver);
4075 static void __exit mv_exit(void)
4078 pci_unregister_driver(&mv_pci_driver);
4080 platform_driver_unregister(&mv_platform_driver);
4083 MODULE_AUTHOR("Brett Russ");
4084 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4085 MODULE_LICENSE("GPL");
4086 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4087 MODULE_VERSION(DRV_VERSION);
4088 MODULE_ALIAS("platform:" DRV_NAME);
4090 module_init(mv_init);
4091 module_exit(mv_exit);