2 * MPC8610 HPCD Device Tree Source
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
14 model = "MPC8610HPCD";
15 compatible = "fsl,MPC8610HPCD";
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
38 timebase-frequency = <0>; // From uboot
39 bus-frequency = <0>; // From uboot
40 clock-frequency = <0>; // From uboot
45 device_type = "memory";
46 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
55 interrupt-parent = <&mpic>;
56 ranges = <0 0 0xf8000000 0x08000000
57 1 0 0xf0000000 0x08000000
58 2 0 0xe8400000 0x00008000
59 4 0 0xe8440000 0x00008000
60 5 0 0xe8480000 0x00008000
61 6 0 0xe84c0000 0x00008000
62 3 0 0xe8000000 0x00000020>;
65 compatible = "cfi-flash";
66 reg = <0 0 0x8000000>;
72 compatible = "cfi-flash";
73 reg = <1 0 0x8000000>;
79 compatible = "fsl,mpc8610-fcm-nand",
85 compatible = "fsl,mpc8610-fcm-nand",
91 compatible = "fsl,mpc8610-fcm-nand",
97 compatible = "fsl,mpc8610-fcm-nand",
103 compatible = "fsl,fpga-pixis";
109 #address-cells = <1>;
111 #interrupt-cells = <2>;
113 compatible = "fsl,mpc8610-immr", "simple-bus";
114 ranges = <0x0 0xe0000000 0x00100000>;
115 reg = <0xe0000000 0x1000>;
119 #address-cells = <1>;
122 compatible = "fsl-i2c";
123 reg = <0x3000 0x100>;
125 interrupt-parent = <&mpic>;
129 compatible = "cirrus,cs4270";
131 /* MCLK source is a stand-alone oscillator */
132 clock-frequency = <12288000>;
137 #address-cells = <1>;
140 compatible = "fsl-i2c";
141 reg = <0x3100 0x100>;
143 interrupt-parent = <&mpic>;
147 serial0: serial@4500 {
149 device_type = "serial";
150 compatible = "ns16550";
151 reg = <0x4500 0x100>;
152 clock-frequency = <0>;
154 interrupt-parent = <&mpic>;
157 serial1: serial@4600 {
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <0x4600 0x100>;
162 clock-frequency = <0>;
164 interrupt-parent = <&mpic>;
168 compatible = "fsl,diu";
171 interrupt-parent = <&mpic>;
174 mpic: interrupt-controller@40000 {
175 clock-frequency = <0>;
176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <2>;
179 reg = <0x40000 0x40000>;
180 compatible = "chrp,open-pic";
181 device_type = "open-pic";
186 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
187 reg = <0x41600 0x80>;
188 msi-available-ranges = <0 0x100>;
198 interrupt-parent = <&mpic>;
201 global-utilities@e0000 {
202 compatible = "fsl,mpc8610-guts";
203 reg = <0xe0000 0x1000>;
208 compatible = "fsl,mpc8610-ssi";
210 reg = <0x16000 0x100>;
211 interrupt-parent = <&mpic>;
213 fsl,mode = "i2s-slave";
214 codec-handle = <&cs4270>;
218 compatible = "fsl,mpc8610-ssi";
220 reg = <0x16100 0x100>;
221 interrupt-parent = <&mpic>;
226 #address-cells = <1>;
228 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
230 reg = <0x21300 0x4>; /* DMA general status register */
231 ranges = <0x0 0x21100 0x200>;
234 compatible = "fsl,mpc8610-dma-channel",
235 "fsl,eloplus-dma-channel";
238 interrupt-parent = <&mpic>;
242 compatible = "fsl,mpc8610-dma-channel",
243 "fsl,eloplus-dma-channel";
246 interrupt-parent = <&mpic>;
250 compatible = "fsl,mpc8610-dma-channel",
251 "fsl,eloplus-dma-channel";
254 interrupt-parent = <&mpic>;
258 compatible = "fsl,mpc8610-dma-channel",
259 "fsl,eloplus-dma-channel";
262 interrupt-parent = <&mpic>;
268 #address-cells = <1>;
270 compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
272 reg = <0xc300 0x4>; /* DMA general status register */
273 ranges = <0x0 0xc100 0x200>;
276 compatible = "fsl,mpc8610-dma-channel",
277 "fsl,mpc8540-dma-channel";
280 interrupt-parent = <&mpic>;
284 compatible = "fsl,mpc8610-dma-channel",
285 "fsl,mpc8540-dma-channel";
288 interrupt-parent = <&mpic>;
292 compatible = "fsl,mpc8610-dma-channel",
293 "fsl,mpc8540-dma-channel";
296 interrupt-parent = <&mpic>;
300 compatible = "fsl,mpc8610-dma-channel",
301 "fsl,mpc8540-dma-channel";
304 interrupt-parent = <&mpic>;
313 compatible = "fsl,mpc8610-pci";
315 #interrupt-cells = <1>;
317 #address-cells = <3>;
318 reg = <0xe0008000 0x1000>;
320 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
321 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
322 clock-frequency = <33333333>;
323 interrupt-parent = <&mpic>;
325 interrupt-map-mask = <0xf800 0 0 7>;
328 0x8800 0 0 1 &mpic 4 1
329 0x8800 0 0 2 &mpic 5 1
330 0x8800 0 0 3 &mpic 6 1
331 0x8800 0 0 4 &mpic 7 1
334 0x9000 0 0 1 &mpic 5 1
335 0x9000 0 0 2 &mpic 6 1
336 0x9000 0 0 3 &mpic 7 1
337 0x9000 0 0 4 &mpic 4 1
341 pci1: pcie@e000a000 {
343 compatible = "fsl,mpc8641-pcie";
345 #interrupt-cells = <1>;
347 #address-cells = <3>;
348 reg = <0xe000a000 0x1000>;
350 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
351 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
355 interrupt-map-mask = <0xf800 0 0 7>;
359 0xd800 0 0 1 &mpic 2 1
362 0xe000 0 0 1 &mpic 1 1
363 0xe000 0 0 2 &mpic 1 1
364 0xe000 0 0 3 &mpic 1 1
365 0xe000 0 0 4 &mpic 1 1
368 0xf800 0 0 1 &mpic 3 0
369 0xf800 0 0 2 &mpic 0 1
375 #address-cells = <3>;
377 ranges = <0x02000000 0x0 0xa0000000
378 0x02000000 0x0 0xa0000000
380 0x01000000 0x0 0x00000000
381 0x01000000 0x0 0x00000000
386 #address-cells = <3>;
387 ranges = <0x02000000 0x0 0xa0000000
388 0x02000000 0x0 0xa0000000
390 0x01000000 0x0 0x00000000
391 0x01000000 0x0 0x00000000
397 pci2: pcie@e0009000 {
398 #address-cells = <3>;
400 #interrupt-cells = <1>;
402 compatible = "fsl,mpc8641-pcie";
403 reg = <0xe0009000 0x00001000>;
404 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
405 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
407 interrupt-map-mask = <0xf800 0 0 7>;
408 interrupt-map = <0x0000 0 0 1 &mpic 4 1
409 0x0000 0 0 2 &mpic 5 1
410 0x0000 0 0 3 &mpic 6 1
411 0x0000 0 0 4 &mpic 7 1>;
412 interrupt-parent = <&mpic>;
414 clock-frequency = <33333333>;