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   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78 };
  79
  80 #ifdef CONFIG_ARCH_OMAP1
  81
  82 static struct omap_dm_timer dm_timers[] = {
  83         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  84         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  85         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  86         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  87         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  88         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  89         { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
  90         { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
  91 };
  92
  93 #elif defined(CONFIG_ARCH_OMAP2)
  94
  95 static struct omap_dm_timer dm_timers[] = {
  96         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
  97         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
  98         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
  99         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 100         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 101         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 102         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 103         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 104         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 105         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 106         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 107         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 108 };
 109
 110 static const char *dm_source_names[] = {
 111         "sys_ck",
 112         "func_32k_ck",
 113         "alt_ck"
 114 };
 115
 116 static struct clk *dm_source_clocks[3];
 117
 118 #else
 119
 120 #error OMAP architecture not supported!
 121
 122 #endif
 123
 124 static const int dm_timer_count = ARRAY_SIZE(dm_timers);
 125 static spinlock_t dm_timer_lock;
 126
 127 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 128 {
 129         return readl(timer->io_base + reg);
 130 }
 131
 132 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 133 {
 134         writel(value, timer->io_base + reg);
 135         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 136                 ;
 137 }
 138
 139 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 140 {
 141         int c;
 142
 143         c = 0;
 144         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 145                 c++;
 146                 if (c > 100000) {
 147                         printk(KERN_ERR "Timer failed to reset\n");
 148                         return;
 149                 }
 150         }
 151 }
 152
 153 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 154 {
 155         u32 l;
 156
 157         if (timer != &dm_timers[0]) {
 158                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 159                 omap_dm_timer_wait_for_reset(timer);
 160         }
 161         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
 162
 163         /* Set to smart-idle mode */
 164         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 165         l |= 0x02 << 3;
 166         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 167 }
 168
 169 static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
 170 {
 171 #ifdef CONFIG_ARCH_OMAP2
 172         clk_enable(timer->iclk);
 173         clk_enable(timer->fclk);
 174 #endif
 175         omap_dm_timer_reset(timer);
 176 }
 177
 178 struct omap_dm_timer *omap_dm_timer_request(void)
 179 {
 180         struct omap_dm_timer *timer = NULL;
 181         unsigned long flags;
 182         int i;
 183
 184         spin_lock_irqsave(&dm_timer_lock, flags);
 185         for (i = 0; i < dm_timer_count; i++) {
 186                 if (dm_timers[i].reserved)
 187                         continue;
 188
 189                 timer = &dm_timers[i];
 190                 timer->reserved = 1;
 191                 break;
 192         }
 193         spin_unlock_irqrestore(&dm_timer_lock, flags);
 194
 195         if (timer != NULL)
 196                 omap_dm_timer_prepare(timer);
 197
 198         return timer;
 199 }
 200
 201 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 202 {
 203         struct omap_dm_timer *timer;
 204         unsigned long flags;
 205
 206         spin_lock_irqsave(&dm_timer_lock, flags);
 207         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 208                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 209                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 210                        __FILE__, __LINE__, __FUNCTION__, id);
 211                 dump_stack();
 212                 return NULL;
 213         }
 214
 215         timer = &dm_timers[id-1];
 216         timer->reserved = 1;
 217         spin_unlock_irqrestore(&dm_timer_lock, flags);
 218
 219         omap_dm_timer_prepare(timer);
 220
 221         return timer;
 222 }
 223
 224 void omap_dm_timer_free(struct omap_dm_timer *timer)
 225 {
 226         omap_dm_timer_reset(timer);
 227 #ifdef CONFIG_ARCH_OMAP2
 228         clk_disable(timer->iclk);
 229         clk_disable(timer->fclk);
 230 #endif
 231         WARN_ON(!timer->reserved);
 232         timer->reserved = 0;
 233 }
 234
 235 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 236 {
 237         return timer->irq;
 238 }
 239
 240 #if defined(CONFIG_ARCH_OMAP1)
 241
 242 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 243 {
 244         BUG();
 245 }
 246
 247 /**
 248  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 249  * @inputmask: current value of idlect mask
 250  */
 251 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 252 {
 253         int i;
 254
 255         /* If ARMXOR cannot be idled this function call is unnecessary */
 256         if (!(inputmask & (1 << 1)))
 257                 return inputmask;
 258
 259         /* If any active timer is using ARMXOR return modified mask */
 260         for (i = 0; i < dm_timer_count; i++) {
 261                 u32 l;
 262
 263                 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
 264                 if (l & OMAP_TIMER_CTRL_ST) {
 265                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 266                                 inputmask &= ~(1 << 1);
 267                         else
 268                                 inputmask &= ~(1 << 2);
 269                 }
 270         }
 271
 272         return inputmask;
 273 }
 274
 275 #elif defined(CONFIG_ARCH_OMAP2)
 276
 277 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 278 {
 279         return timer->fclk;
 280 }
 281
 282 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 283 {
 284         BUG();
 285 }
 286
 287 #endif
 288
 289 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 290 {
 291         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 292 }
 293
 294 void omap_dm_timer_start(struct omap_dm_timer *timer)
 295 {
 296         u32 l;
 297
 298         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 299         if (!(l & OMAP_TIMER_CTRL_ST)) {
 300                 l |= OMAP_TIMER_CTRL_ST;
 301                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 302         }
 303 }
 304
 305 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 306 {
 307         u32 l;
 308
 309         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 310         if (l & OMAP_TIMER_CTRL_ST) {
 311                 l &= ~0x1;
 312                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 313         }
 314 }
 315
 316 #ifdef CONFIG_ARCH_OMAP1
 317
 318 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 319 {
 320         int n = (timer - dm_timers) << 1;
 321         u32 l;
 322
 323         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 324         l |= source << n;
 325         omap_writel(l, MOD_CONF_CTRL_1);
 326 }
 327
 328 #else
 329
 330 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 331 {
 332         if (source < 0 || source >= 3)
 333                 return;
 334
 335         clk_disable(timer->fclk);
 336         clk_set_parent(timer->fclk, dm_source_clocks[source]);
 337         clk_enable(timer->fclk);
 338
 339         /* When the functional clock disappears, too quick writes seem to
 340          * cause an abort. */
 341         __delay(15000);
 342 }
 343
 344 #endif
 345
 346 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 347                             unsigned int load)
 348 {
 349         u32 l;
 350
 351         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 352         if (autoreload)
 353                 l |= OMAP_TIMER_CTRL_AR;
 354         else
 355                 l &= ~OMAP_TIMER_CTRL_AR;
 356         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 357         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 358         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 359 }
 360
 361 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 362                              unsigned int match)
 363 {
 364         u32 l;
 365
 366         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 367         if (enable)
 368                 l |= OMAP_TIMER_CTRL_CE;
 369         else
 370                 l &= ~OMAP_TIMER_CTRL_CE;
 371         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 372         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 373 }
 374
 375
 376 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 377                            int toggle, int trigger)
 378 {
 379         u32 l;
 380
 381         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 382         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 383                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 384         if (def_on)
 385                 l |= OMAP_TIMER_CTRL_SCPWM;
 386         if (toggle)
 387                 l |= OMAP_TIMER_CTRL_PT;
 388         l |= trigger << 10;
 389         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 390 }
 391
 392 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 393 {
 394         u32 l;
 395
 396         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 397         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 398         if (prescaler >= 0x00 && prescaler <= 0x07) {
 399                 l |= OMAP_TIMER_CTRL_PRE;
 400                 l |= prescaler << 2;
 401         }
 402         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 403 }
 404
 405 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 406                                   unsigned int value)
 407 {
 408         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 409 }
 410
 411 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 412 {
 413         return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 414 }
 415
 416 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 417 {
 418         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 419 }
 420
 421 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 422 {
 423         return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 424 }
 425
 426 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 427 {
 428         return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 429 }
 430
 431 int omap_dm_timers_active(void)
 432 {
 433         int i;
 434
 435         for (i = 0; i < dm_timer_count; i++) {
 436                 struct omap_dm_timer *timer;
 437
 438                 timer = &dm_timers[i];
 439                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 440                     OMAP_TIMER_CTRL_ST)
 441                         return 1;
 442         }
 443         return 0;
 444 }
 445
 446 int omap_dm_timer_init(void)
 447 {
 448         struct omap_dm_timer *timer;
 449         int i;
 450
 451         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 452                 return -ENODEV;
 453
 454         spin_lock_init(&dm_timer_lock);
 455 #ifdef CONFIG_ARCH_OMAP2
 456         for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
 457                 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
 458                 BUG_ON(dm_source_clocks[i] == NULL);
 459         }
 460 #endif
 461
 462         for (i = 0; i < dm_timer_count; i++) {
 463 #ifdef CONFIG_ARCH_OMAP2
 464                 char clk_name[16];
 465 #endif
 466
 467                 timer = &dm_timers[i];
 468                 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
 469 #ifdef CONFIG_ARCH_OMAP2
 470                 sprintf(clk_name, "gpt%d_ick", i + 1);
 471                 timer->iclk = clk_get(NULL, clk_name);
 472                 sprintf(clk_name, "gpt%d_fck", i + 1);
 473                 timer->fclk = clk_get(NULL, clk_name);
 474 #endif
 475         }
 476
 477         return 0;
 478 }