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   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23
  24 #include <asm/delay.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/mux.h>
  30 #include <asm/arch/irqs.h>
  31 #include <asm/arch/dsp_common.h>
  32 #include <asm/arch/mcbsp.h>
  33
  34 #ifdef CONFIG_MCBSP_DEBUG
  35 #define DBG(x...)       printk(x)
  36 #else
  37 #define DBG(x...)                       do { } while (0)
  38 #endif
  39
  40 struct omap_mcbsp {
  41         u32                          io_base;
  42         u8                           id;
  43         u8                           free;
  44         omap_mcbsp_word_length       rx_word_length;
  45         omap_mcbsp_word_length       tx_word_length;
  46
  47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck = 0;
  70 static struct clk *mcbsp_api_ck = 0;
  71 static struct clk *mcbsp_dspxor_ck = 0;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick = 0;
  75 static struct clk *mcbsp1_fck = 0;
  76 static struct clk *mcbsp2_ick = 0;
  77 static struct clk *mcbsp2_fck = 0;
  78 static struct clk *sys_ck = 0;
  79 static struct clk *sys_clkout = 0;
  80 #endif
  81
  82 static void omap_mcbsp_dump_reg(u8 id)
  83 {
  84         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  85         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  86         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  87         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  88         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  89         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  90         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  91         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  92         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  93         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  94         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  95         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  96         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  97         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  98         DBG("***********************\n");
  99 }
 100
 101 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 102 {
 103         struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
 104
 105         DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 106
 107         complete(&mcbsp_tx->tx_irq_completion);
 108         return IRQ_HANDLED;
 109 }
 110
 111 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 112 {
 113         struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
 114
 115         DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 116
 117         complete(&mcbsp_rx->rx_irq_completion);
 118         return IRQ_HANDLED;
 119 }
 120
 121 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 122 {
 123         struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
 124
 125         DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 126
 127         /* We can free the channels */
 128         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 129         mcbsp_dma_tx->dma_tx_lch = -1;
 130
 131         complete(&mcbsp_dma_tx->tx_dma_completion);
 132 }
 133
 134 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 135 {
 136         struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
 137
 138         DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 142         mcbsp_dma_rx->dma_rx_lch = -1;
 143
 144         complete(&mcbsp_dma_rx->rx_dma_completion);
 145 }
 146
 147
 148 /*
 149  * omap_mcbsp_config simply write a config to the
 150  * appropriate McBSP.
 151  * You either call this function or set the McBSP registers
 152  * by yourself before calling omap_mcbsp_start().
 153  */
 154
 155 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 156 {
 157         u32 io_base = mcbsp[id].io_base;
 158
 159         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 160
 161         /* We write the given config */
 162         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 163         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 164         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 165         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 166         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 167         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 168         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 169         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 170         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 171         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 172         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 173 }
 174
 175
 176
 177 static int omap_mcbsp_check(unsigned int id)
 178 {
 179         if (cpu_is_omap730()) {
 180                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 181                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 182                        return -1;
 183                 }
 184                 return 0;
 185         }
 186
 187         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 188                 if (id > OMAP_MAX_MCBSP_COUNT) {
 189                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 190                         return -1;
 191                 }
 192                 return 0;
 193         }
 194
 195         return -1;
 196 }
 197
 198 #ifdef CONFIG_ARCH_OMAP1
 199 static void omap_mcbsp_dsp_request(void)
 200 {
 201         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 202                 clk_enable(mcbsp_dsp_ck);
 203                 clk_enable(mcbsp_api_ck);
 204
 205                 /* enable 12MHz clock to mcbsp 1 & 3 */
 206                 clk_enable(mcbsp_dspxor_ck);
 207
 208                 /*
 209                  * DSP external peripheral reset
 210                  * FIXME: This should be moved to dsp code
 211                  */
 212                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 213                              DSP_RSTCT2);
 214         }
 215 }
 216
 217 static void omap_mcbsp_dsp_free(void)
 218 {
 219         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 220                 clk_disable(mcbsp_dspxor_ck);
 221                 clk_disable(mcbsp_dsp_ck);
 222                 clk_disable(mcbsp_api_ck);
 223         }
 224 }
 225 #endif
 226
 227 #ifdef CONFIG_ARCH_OMAP2
 228 static void omap2_mcbsp2_mux_setup(void)
 229 {
 230         omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 231         omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 232         omap_cfg_reg(W15_24XX_MCBSP2_DR);
 233         omap_cfg_reg(V15_24XX_MCBSP2_DX);
 234         omap_cfg_reg(V14_24XX_GPIO117);
 235         omap_cfg_reg(W14_24XX_SYS_CLKOUT);
 236 }
 237 #endif
 238
 239 /*
 240  * We can choose between IRQ based or polled IO.
 241  * This needs to be called before omap_mcbsp_request().
 242  */
 243 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 244 {
 245         if (omap_mcbsp_check(id) < 0)
 246                 return -EINVAL;
 247
 248         spin_lock(&mcbsp[id].lock);
 249
 250         if (!mcbsp[id].free) {
 251                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 252                 spin_unlock(&mcbsp[id].lock);
 253                 return -EINVAL;
 254         }
 255
 256         mcbsp[id].io_type = io_type;
 257
 258         spin_unlock(&mcbsp[id].lock);
 259
 260         return 0;
 261 }
 262
 263 int omap_mcbsp_request(unsigned int id)
 264 {
 265         int err;
 266
 267         if (omap_mcbsp_check(id) < 0)
 268                 return -EINVAL;
 269
 270 #ifdef CONFIG_ARCH_OMAP1
 271         /*
 272          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 273          * are DSP public peripherals.
 274          */
 275         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 276                 omap_mcbsp_dsp_request();
 277 #endif
 278
 279 #ifdef CONFIG_ARCH_OMAP2
 280         if (cpu_is_omap24xx()) {
 281                 if (id == OMAP_MCBSP1) {
 282                         clk_enable(mcbsp1_ick);
 283                         clk_enable(mcbsp1_fck);
 284                 } else {
 285                         clk_enable(mcbsp2_ick);
 286                         clk_enable(mcbsp2_fck);
 287                 }
 288         }
 289 #endif
 290
 291         spin_lock(&mcbsp[id].lock);
 292         if (!mcbsp[id].free) {
 293                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 294                 spin_unlock(&mcbsp[id].lock);
 295                 return -1;
 296         }
 297
 298         mcbsp[id].free = 0;
 299         spin_unlock(&mcbsp[id].lock);
 300
 301         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 302                 /* We need to get IRQs here */
 303                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 304                                   "McBSP",
 305                                   (void *) (&mcbsp[id]));
 306                 if (err != 0) {
 307                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 308                                mcbsp[id].tx_irq, mcbsp[id].id);
 309                         return err;
 310                 }
 311
 312                 init_completion(&(mcbsp[id].tx_irq_completion));
 313
 314
 315                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 316                                   "McBSP",
 317                                   (void *) (&mcbsp[id]));
 318                 if (err != 0) {
 319                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 320                                mcbsp[id].rx_irq, mcbsp[id].id);
 321                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 322                         return err;
 323                 }
 324
 325                 init_completion(&(mcbsp[id].rx_irq_completion));
 326         }
 327
 328         return 0;
 329
 330 }
 331
 332 void omap_mcbsp_free(unsigned int id)
 333 {
 334         if (omap_mcbsp_check(id) < 0)
 335                 return;
 336
 337 #ifdef CONFIG_ARCH_OMAP1
 338         if (cpu_class_is_omap1()) {
 339                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 340                         omap_mcbsp_dsp_free();
 341         }
 342 #endif
 343
 344 #ifdef CONFIG_ARCH_OMAP2
 345         if (cpu_is_omap24xx()) {
 346                 if (id == OMAP_MCBSP1) {
 347                         clk_disable(mcbsp1_ick);
 348                         clk_disable(mcbsp1_fck);
 349                 } else {
 350                         clk_disable(mcbsp2_ick);
 351                         clk_disable(mcbsp2_fck);
 352                 }
 353         }
 354 #endif
 355
 356         spin_lock(&mcbsp[id].lock);
 357         if (mcbsp[id].free) {
 358                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 359                 spin_unlock(&mcbsp[id].lock);
 360                 return;
 361         }
 362
 363         mcbsp[id].free = 1;
 364         spin_unlock(&mcbsp[id].lock);
 365
 366         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 367                 /* Free IRQs */
 368                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 369                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 370         }
 371 }
 372
 373 /*
 374  * Here we start the McBSP, by enabling the sample
 375  * generator, both transmitter and receivers,
 376  * and the frame sync.
 377  */
 378 void omap_mcbsp_start(unsigned int id)
 379 {
 380         u32 io_base;
 381         u16 w;
 382
 383         if (omap_mcbsp_check(id) < 0)
 384                 return;
 385
 386         io_base = mcbsp[id].io_base;
 387
 388         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 389         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 390
 391         /* Start the sample generator */
 392         w = OMAP_MCBSP_READ(io_base, SPCR2);
 393         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 394
 395         /* Enable transmitter and receiver */
 396         w = OMAP_MCBSP_READ(io_base, SPCR2);
 397         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 398
 399         w = OMAP_MCBSP_READ(io_base, SPCR1);
 400         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 401
 402         udelay(100);
 403
 404         /* Start frame sync */
 405         w = OMAP_MCBSP_READ(io_base, SPCR2);
 406         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 407
 408         /* Dump McBSP Regs */
 409         omap_mcbsp_dump_reg(id);
 410
 411 }
 412
 413 void omap_mcbsp_stop(unsigned int id)
 414 {
 415         u32 io_base;
 416         u16 w;
 417
 418         if (omap_mcbsp_check(id) < 0)
 419                 return;
 420
 421         io_base = mcbsp[id].io_base;
 422
 423         /* Reset transmitter */
 424         w = OMAP_MCBSP_READ(io_base, SPCR2);
 425         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 426
 427         /* Reset receiver */
 428         w = OMAP_MCBSP_READ(io_base, SPCR1);
 429         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 430
 431         /* Reset the sample rate generator */
 432         w = OMAP_MCBSP_READ(io_base, SPCR2);
 433         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 434 }
 435
 436
 437 /* polled mcbsp i/o operations */
 438 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 439 {
 440         u32 base = mcbsp[id].io_base;
 441         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 442         /* if frame sync error - clear the error */
 443         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 444                 /* clear error */
 445                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 446                        base + OMAP_MCBSP_REG_SPCR2);
 447                 /* resend */
 448                 return -1;
 449         } else {
 450                 /* wait for transmit confirmation */
 451                 int attemps = 0;
 452                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 453                         if (attemps++ > 1000) {
 454                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 455                                        (~XRST),
 456                                        base + OMAP_MCBSP_REG_SPCR2);
 457                                 udelay(10);
 458                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 459                                        (XRST),
 460                                        base + OMAP_MCBSP_REG_SPCR2);
 461                                 udelay(10);
 462                                 printk(KERN_ERR
 463                                        " Could not write to McBSP Register\n");
 464                                 return -2;
 465                         }
 466                 }
 467         }
 468         return 0;
 469 }
 470
 471 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 472 {
 473         u32 base = mcbsp[id].io_base;
 474         /* if frame sync error - clear the error */
 475         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 476                 /* clear error */
 477                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 478                        base + OMAP_MCBSP_REG_SPCR1);
 479                 /* resend */
 480                 return -1;
 481         } else {
 482                 /* wait for recieve confirmation */
 483                 int attemps = 0;
 484                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 485                         if (attemps++ > 1000) {
 486                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 487                                        (~RRST),
 488                                        base + OMAP_MCBSP_REG_SPCR1);
 489                                 udelay(10);
 490                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 491                                        (RRST),
 492                                        base + OMAP_MCBSP_REG_SPCR1);
 493                                 udelay(10);
 494                                 printk(KERN_ERR
 495                                        " Could not read from McBSP Register\n");
 496                                 return -2;
 497                         }
 498                 }
 499         }
 500         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 501         return 0;
 502 }
 503
 504 /*
 505  * IRQ based word transmission.
 506  */
 507 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 508 {
 509         u32 io_base;
 510         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 511
 512         if (omap_mcbsp_check(id) < 0)
 513                 return;
 514
 515         io_base = mcbsp[id].io_base;
 516
 517         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 518
 519         if (word_length > OMAP_MCBSP_WORD_16)
 520                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 521         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 522 }
 523
 524 u32 omap_mcbsp_recv_word(unsigned int id)
 525 {
 526         u32 io_base;
 527         u16 word_lsb, word_msb = 0;
 528         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 529
 530         if (omap_mcbsp_check(id) < 0)
 531                 return -EINVAL;
 532
 533         io_base = mcbsp[id].io_base;
 534
 535         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 536
 537         if (word_length > OMAP_MCBSP_WORD_16)
 538                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 539         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 540
 541         return (word_lsb | (word_msb << 16));
 542 }
 543
 544
 545 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 546 {
 547         u32 io_base = mcbsp[id].io_base;
 548         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 549         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 550         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 551
 552         if (tx_word_length != rx_word_length)
 553                 return -EINVAL;
 554
 555         /* First we wait for the transmitter to be ready */
 556         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 557         while (!(spcr2 & XRDY)) {
 558                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 559                 if (attempts++ > 1000) {
 560                         /* We must reset the transmitter */
 561                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 562                         udelay(10);
 563                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 564                         udelay(10);
 565                         printk("McBSP transmitter not ready\n");
 566                         return -EAGAIN;
 567                 }
 568         }
 569
 570         /* Now we can push the data */
 571         if (tx_word_length > OMAP_MCBSP_WORD_16)
 572                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 573         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 574
 575         /* We wait for the receiver to be ready */
 576         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 577         while (!(spcr1 & RRDY)) {
 578                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 579                 if (attempts++ > 1000) {
 580                         /* We must reset the receiver */
 581                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 582                         udelay(10);
 583                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 584                         udelay(10);
 585                         printk("McBSP receiver not ready\n");
 586                         return -EAGAIN;
 587                 }
 588         }
 589
 590         /* Receiver is ready, let's read the dummy data */
 591         if (rx_word_length > OMAP_MCBSP_WORD_16)
 592                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 593         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 594
 595         return 0;
 596 }
 597
 598 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 599 {
 600         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 601         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 602         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 603         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 604
 605         if (tx_word_length != rx_word_length)
 606                 return -EINVAL;
 607
 608         /* First we wait for the transmitter to be ready */
 609         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 610         while (!(spcr2 & XRDY)) {
 611                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 612                 if (attempts++ > 1000) {
 613                         /* We must reset the transmitter */
 614                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 615                         udelay(10);
 616                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 617                         udelay(10);
 618                         printk("McBSP transmitter not ready\n");
 619                         return -EAGAIN;
 620                 }
 621         }
 622
 623         /* We first need to enable the bus clock */
 624         if (tx_word_length > OMAP_MCBSP_WORD_16)
 625                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 626         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 627
 628         /* We wait for the receiver to be ready */
 629         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 630         while (!(spcr1 & RRDY)) {
 631                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 632                 if (attempts++ > 1000) {
 633                         /* We must reset the receiver */
 634                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 635                         udelay(10);
 636                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 637                         udelay(10);
 638                         printk("McBSP receiver not ready\n");
 639                         return -EAGAIN;
 640                 }
 641         }
 642
 643         /* Receiver is ready, there is something for us */
 644         if (rx_word_length > OMAP_MCBSP_WORD_16)
 645                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 646         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 647
 648         word[0] = (word_lsb | (word_msb << 16));
 649
 650         return 0;
 651 }
 652
 653
 654 /*
 655  * Simple DMA based buffer rx/tx routines.
 656  * Nothing fancy, just a single buffer tx/rx through DMA.
 657  * The DMA resources are released once the transfer is done.
 658  * For anything fancier, you should use your own customized DMA
 659  * routines and callbacks.
 660  */
 661 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 662 {
 663         int dma_tx_ch;
 664         int src_port = 0;
 665         int dest_port = 0;
 666         int sync_dev = 0;
 667
 668         if (omap_mcbsp_check(id) < 0)
 669                 return -EINVAL;
 670
 671         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 672                              &mcbsp[id],
 673                              &dma_tx_ch)) {
 674                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 675                 return -EAGAIN;
 676         }
 677         mcbsp[id].dma_tx_lch = dma_tx_ch;
 678
 679         DBG("TX DMA on channel %d\n", dma_tx_ch);
 680
 681         init_completion(&(mcbsp[id].tx_dma_completion));
 682
 683         if (cpu_class_is_omap1()) {
 684                 src_port = OMAP_DMA_PORT_TIPB;
 685                 dest_port = OMAP_DMA_PORT_EMIFF;
 686         }
 687         if (cpu_is_omap24xx())
 688                 sync_dev = mcbsp[id].dma_tx_sync;
 689
 690         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 691                                      OMAP_DMA_DATA_TYPE_S16,
 692                                      length >> 1, 1,
 693                                      OMAP_DMA_SYNC_ELEMENT,
 694          sync_dev, 0);
 695
 696         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 697                                  src_port,
 698                                  OMAP_DMA_AMODE_CONSTANT,
 699                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 700                                  0, 0);
 701
 702         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 703                                 dest_port,
 704                                 OMAP_DMA_AMODE_POST_INC,
 705                                 buffer,
 706                                 0, 0);
 707
 708         omap_start_dma(mcbsp[id].dma_tx_lch);
 709         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 710         return 0;
 711 }
 712
 713
 714 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 715 {
 716         int dma_rx_ch;
 717         int src_port = 0;
 718         int dest_port = 0;
 719         int sync_dev = 0;
 720
 721         if (omap_mcbsp_check(id) < 0)
 722                 return -EINVAL;
 723
 724         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 725                              &mcbsp[id],
 726                              &dma_rx_ch)) {
 727                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 728                 return -EAGAIN;
 729         }
 730         mcbsp[id].dma_rx_lch = dma_rx_ch;
 731
 732         DBG("RX DMA on channel %d\n", dma_rx_ch);
 733
 734         init_completion(&(mcbsp[id].rx_dma_completion));
 735
 736         if (cpu_class_is_omap1()) {
 737                 src_port = OMAP_DMA_PORT_TIPB;
 738                 dest_port = OMAP_DMA_PORT_EMIFF;
 739         }
 740         if (cpu_is_omap24xx())
 741                 sync_dev = mcbsp[id].dma_rx_sync;
 742
 743         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 744                                      OMAP_DMA_DATA_TYPE_S16,
 745                                      length >> 1, 1,
 746                                      OMAP_DMA_SYNC_ELEMENT,
 747          sync_dev, 0);
 748
 749         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 750                                 src_port,
 751                                 OMAP_DMA_AMODE_CONSTANT,
 752                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 753                                 0, 0);
 754
 755         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 756                                  dest_port,
 757                                  OMAP_DMA_AMODE_POST_INC,
 758                                  buffer,
 759                                  0, 0);
 760
 761         omap_start_dma(mcbsp[id].dma_rx_lch);
 762         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 763         return 0;
 764 }
 765
 766
 767 /*
 768  * SPI wrapper.
 769  * Since SPI setup is much simpler than the generic McBSP one,
 770  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 771  * Once this is done, you can call omap_mcbsp_start().
 772  */
 773 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 774 {
 775         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 776
 777         if (omap_mcbsp_check(id) < 0)
 778                 return;
 779
 780         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 781
 782         /* SPI has only one frame */
 783         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 784         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 785
 786         /* Clock stop mode */
 787         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 788                 mcbsp_cfg.spcr1 |= (1 << 12);
 789         else
 790                 mcbsp_cfg.spcr1 |= (3 << 11);
 791
 792         /* Set clock parities */
 793         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 794                 mcbsp_cfg.pcr0 |= CLKRP;
 795         else
 796                 mcbsp_cfg.pcr0 &= ~CLKRP;
 797
 798         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 799                 mcbsp_cfg.pcr0 &= ~CLKXP;
 800         else
 801                 mcbsp_cfg.pcr0 |= CLKXP;
 802
 803         /* Set SCLKME to 0 and CLKSM to 1 */
 804         mcbsp_cfg.pcr0 &= ~SCLKME;
 805         mcbsp_cfg.srgr2 |= CLKSM;
 806
 807         /* Set FSXP */
 808         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 809                 mcbsp_cfg.pcr0 &= ~FSXP;
 810         else
 811                 mcbsp_cfg.pcr0 |= FSXP;
 812
 813         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 814                 mcbsp_cfg.pcr0 |= CLKXM;
 815                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 816                 mcbsp_cfg.pcr0 |= FSXM;
 817                 mcbsp_cfg.srgr2 &= ~FSGM;
 818                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 819                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 820         }
 821         else {
 822                 mcbsp_cfg.pcr0 &= ~CLKXM;
 823                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 824                 mcbsp_cfg.pcr0 &= ~FSXM;
 825                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 826                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 827         }
 828
 829         mcbsp_cfg.xcr2 &= ~XPHASE;
 830         mcbsp_cfg.rcr2 &= ~RPHASE;
 831
 832         omap_mcbsp_config(id, &mcbsp_cfg);
 833 }
 834
 835
 836 /*
 837  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 838  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 839  */
 840 struct omap_mcbsp_info {
 841         u32 virt_base;
 842         u8 dma_rx_sync, dma_tx_sync;
 843         u16 rx_irq, tx_irq;
 844 };
 845
 846 #ifdef CONFIG_ARCH_OMAP730
 847 static const struct omap_mcbsp_info mcbsp_730[] = {
 848         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 849                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 850                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 851                 .rx_irq = INT_730_McBSP1RX,
 852                 .tx_irq = INT_730_McBSP1TX },
 853         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 854                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 855                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 856                 .rx_irq = INT_730_McBSP2RX,
 857                 .tx_irq = INT_730_McBSP2TX },
 858 };
 859 #endif
 860
 861 #ifdef CONFIG_ARCH_OMAP15XX
 862 static const struct omap_mcbsp_info mcbsp_1510[] = {
 863         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 864                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 865                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 866                 .rx_irq = INT_McBSP1RX,
 867                 .tx_irq = INT_McBSP1TX },
 868         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 869                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 870                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 871                 .rx_irq = INT_1510_SPI_RX,
 872                 .tx_irq = INT_1510_SPI_TX },
 873         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 874                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 875                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 876                 .rx_irq = INT_McBSP3RX,
 877                 .tx_irq = INT_McBSP3TX },
 878 };
 879 #endif
 880
 881 #if defined(CONFIG_ARCH_OMAP16XX)
 882 static const struct omap_mcbsp_info mcbsp_1610[] = {
 883         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 884                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 885                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 886                 .rx_irq = INT_McBSP1RX,
 887                 .tx_irq = INT_McBSP1TX },
 888         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 889                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 890                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 891                 .rx_irq = INT_1610_McBSP2_RX,
 892                 .tx_irq = INT_1610_McBSP2_TX },
 893         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 894                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 895                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 896                 .rx_irq = INT_McBSP3RX,
 897                 .tx_irq = INT_McBSP3TX },
 898 };
 899 #endif
 900
 901 #if defined(CONFIG_ARCH_OMAP24XX)
 902 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 903         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 904                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 905                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 906                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 907                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 908                 },
 909         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 910                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 911                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 912                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 913                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 914                 },
 915 };
 916 #endif
 917
 918 static int __init omap_mcbsp_init(void)
 919 {
 920         int mcbsp_count = 0, i;
 921         static const struct omap_mcbsp_info *mcbsp_info;
 922
 923         printk("Initializing OMAP McBSP system\n");
 924
 925 #ifdef CONFIG_ARCH_OMAP1
 926         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 927         if (IS_ERR(mcbsp_dsp_ck)) {
 928                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 929                 return PTR_ERR(mcbsp_dsp_ck);
 930         }
 931         mcbsp_api_ck = clk_get(0, "api_ck");
 932         if (IS_ERR(mcbsp_api_ck)) {
 933                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 934                 return PTR_ERR(mcbsp_api_ck);
 935         }
 936         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 937         if (IS_ERR(mcbsp_dspxor_ck)) {
 938                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 939                 return PTR_ERR(mcbsp_dspxor_ck);
 940         }
 941 #endif
 942 #ifdef CONFIG_ARCH_OMAP2
 943         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 944         if (IS_ERR(mcbsp1_ick)) {
 945                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
 946                 return PTR_ERR(mcbsp1_ick);
 947         }
 948         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 949         if (IS_ERR(mcbsp1_fck)) {
 950                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
 951                 return PTR_ERR(mcbsp1_fck);
 952         }
 953         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 954         if (IS_ERR(mcbsp2_ick)) {
 955                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
 956                 return PTR_ERR(mcbsp2_ick);
 957         }
 958         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 959         if (IS_ERR(mcbsp2_fck)) {
 960                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
 961                 return PTR_ERR(mcbsp2_fck);
 962         }
 963 #endif
 964
 965 #ifdef CONFIG_ARCH_OMAP730
 966         if (cpu_is_omap730()) {
 967                 mcbsp_info = mcbsp_730;
 968                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 969         }
 970 #endif
 971 #ifdef CONFIG_ARCH_OMAP15XX
 972         if (cpu_is_omap15xx()) {
 973                 mcbsp_info = mcbsp_1510;
 974                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 975         }
 976 #endif
 977 #if defined(CONFIG_ARCH_OMAP16XX)
 978         if (cpu_is_omap16xx()) {
 979                 mcbsp_info = mcbsp_1610;
 980                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 981         }
 982 #endif
 983 #if defined(CONFIG_ARCH_OMAP24XX)
 984         if (cpu_is_omap24xx()) {
 985                 mcbsp_info = mcbsp_24xx;
 986                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
 987
 988                 /* REVISIT: where's the right place? */
 989                 omap2_mcbsp2_mux_setup();
 990                 sys_ck = clk_get(0, "sys_ck");
 991                 sys_clkout = clk_get(0, "sys_clkout");
 992                 clk_set_parent(sys_clkout, sys_ck);
 993                 clk_enable(sys_clkout);
 994         }
 995 #endif
 996         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
 997                 if (i >= mcbsp_count) {
 998                         mcbsp[i].io_base = 0;
 999                         mcbsp[i].free = 0;
1000                         continue;
1001                 }
1002                 mcbsp[i].id = i + 1;
1003                 mcbsp[i].free = 1;
1004                 mcbsp[i].dma_tx_lch = -1;
1005                 mcbsp[i].dma_rx_lch = -1;
1006
1007                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1008                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1009                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1010                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1011                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1012                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1013                 spin_lock_init(&mcbsp[i].lock);
1014         }
1015
1016         return 0;
1017 }
1018
1019 arch_initcall(omap_mcbsp_init);
1020
1021 EXPORT_SYMBOL(omap_mcbsp_config);
1022 EXPORT_SYMBOL(omap_mcbsp_request);
1023 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1024 EXPORT_SYMBOL(omap_mcbsp_free);
1025 EXPORT_SYMBOL(omap_mcbsp_start);
1026 EXPORT_SYMBOL(omap_mcbsp_stop);
1027 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1028 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1029 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1030 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1031 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1032 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1033 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);